This example generates 1b and 2b ECC error for DDR. The M4 enables the ESM instances (MAIN ESM0 and MCU ESM0). On generating an ECC error, the M4 receives the interrupt from MCU ESM (through the MAIN ESM error signal output routed to the MCU ESM). On receiving the interrupt, the handler clears the corresponding ECC error bit and restore the original value. If the interrupt is not received the test fails.
Parameter | Value |
---|---|
CPU + OS | m4fss0-0 nortos |
Toolchain | ti-arm-clang |
Board | am62x-sk, am62x-sk-lp, am62x-sip-sk |
Example folder | examples/drivers/ddr/ddr_ecc_test_mcu_esm/ |
Shown below is a sample output when the application is run,