46 #ifndef SAFETY_CHECKERS_SOC_H_
47 #define SAFETY_CHECKERS_SOC_H_
72 #define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS (0x400000UL)
73 #define SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS (0x680000UL)
74 #define SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS (0x4040000UL)
77 #define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM (0x02U)
78 #define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM (0x0AU)
79 #define SAFETY_CHECKERS_PM_PD_STAT_NUM (0x0AU)
80 #define SAFETY_CHECKERS_PM_MD_STAT_NUM (0x34U)
83 #define SAFETY_CHECKERS_PM_PLL0_LENGTH (0xA8U)
84 #define SAFETY_CHECKERS_PM_PLL1_LENGTH (0x9CU)
85 #define SAFETY_CHECKERS_PM_PLL2_LENGTH (0xA8U)
86 #define SAFETY_CHECKERS_PM_PLL8_LENGTH (0x84U)
87 #define SAFETY_CHECKERS_PM_PLL12_LENGTH (0x84U)
88 #define SAFETY_CHECKERS_PM_PLL15_LENGTH (0x88U)
89 #define SAFETY_CHECKERS_PM_PLL16_LENGTH (0x84U)
90 #define SAFETY_CHECKERS_PM_PLL17_LENGTH (0x84U)
91 #define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH (0x94U)
94 #define TIFS_CHECKER_FWL_MAX_NUM (0x10U)
99 #define SAFETY_CHECKERS_PM_PSC_REGDUMP_SIZE (SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM + \
100 SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM + \
101 SAFETY_CHECKERS_PM_PD_STAT_NUM + \
102 SAFETY_CHECKERS_PM_MD_STAT_NUM)
112 #define SAFETY_CHECKERS_PM_PLL_REGDUMP_SIZE (137U)
120 #define SAFETY_CHECKERS_RM_REGDUMP_SIZE (3107U)
123 #define SAFETY_CHECKERS_RM_BA0_IR (CSL_TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG_BASE)
124 #define SAFETY_CHECKERS_RM_BA1_IR (CSL_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
125 #define SAFETY_CHECKERS_RM_BA2_IR (CSL_MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
126 #define SAFETY_CHECKERS_RM_BA3_IR (CSL_CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG_BASE)
129 #define SAFETY_CHECKERS_RM_IR_REG0_NUM (26U)
130 #define SAFETY_CHECKERS_RM_IR_REG1_NUM (13U)
131 #define SAFETY_CHECKERS_RM_IR_REG2_NUM (36U)
132 #define SAFETY_CHECKERS_RM_IR_REG3_NUM (42U)
135 #define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM (2U)
138 #define SAFETY_CHECKERS_RM_BA0_IA_IMAP (CSL_DMASS0_INTAGGR_IMAP_BASE)
141 #define SAFETY_CHECKERS_RM_REG0_IA_IMAP (1536U)
144 #define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP (1U)
147 #define SAFETY_CHECKERS_RM_BA0_RA (CSL_DMASS0_BCDMA_RING_BASE)
148 #define SAFETY_CHECKERS_RM_BA1_RA (CSL_DMASS0_PKTDMA_RING_BASE)
149 #define SAFETY_CHECKERS_RM_BA2_RA (CSL_DMASS0_RINGACC_CFG_BASE)
152 #define SAFETY_CHECKERS_RM_RA_REG0_NUM (82U)
153 #define SAFETY_CHECKERS_RM_RA_REG1_NUM (150U)
154 #define SAFETY_CHECKERS_RM_RA_REG2_NUM (20U)
157 #define SAFETY_CHECKERS_RM_SUBMOD0_RA (3U)
158 #define SAFETY_CHECKERS_RM_RA_SUBMOD1 (5U)
161 #define SAFETY_CHECKERS_RM_BA0_UDMA_TX (CSL_DMASS0_BCDMA_TCHAN_BASE)
162 #define SAFETY_CHECKERS_RM_BA1_UDMA_TX (CSL_DMASS0_PKTDMA_TCHAN_BASE)
165 #define SAFETY_CHECKERS_RM_REG0_UDMA_TX (22U)
166 #define SAFETY_CHECKERS_RM_REG1_UDMA_TX (29U)
169 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX (5U)
172 #define SAFETY_CHECKERS_RM_BA0_UDMA_RX (CSL_DMASS0_BCDMA_RCHAN_BASE)
173 #define SAFETY_CHECKERS_RM_BA1_UDMA_RX (CSL_DMASS0_PKTDMA_RCHAN_BASE)
176 #define SAFETY_CHECKERS_RM_REG0_UDMA_RX (28U)
177 #define SAFETY_CHECKERS_RM_REG1_UDMA_RX (24U)
180 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX (4U)
183 #define SAFETY_CHECKERS_RM_BA0_UDMA_FLW (CSL_DMASS0_PKTDMA_RFLOW_BASE)
186 #define SAFETY_CHECKERS_RM_REG0_UDMA_FLW (51U)
189 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW (1U)
192 #define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG (CSL_DMASS0_BCDMA_GCFG_BASE)
193 #define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG (CSL_DMASS0_PKTDMA_GCFG_BASE)
196 #define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG (1U)
197 #define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG (1U)
200 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG (13U)
201 #define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG (14U)
222 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
223 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
224 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U,
228 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
229 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
230 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU};
233 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
234 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
235 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U,
239 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
240 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
243 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
244 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
247 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
248 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U};
251 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
252 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
255 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
256 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
259 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
260 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
261 0x8CU, 0x90U, 0x94U};
313 {
SAFETY_CHECKERS_RM_BA0_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
314 {
SAFETY_CHECKERS_RM_BA1_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
315 {
SAFETY_CHECKERS_RM_BA2_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
316 {
SAFETY_CHECKERS_RM_BA3_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
318 {
SAFETY_CHECKERS_RM_BA0_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG0_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
320 {
SAFETY_CHECKERS_RM_BA0_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
321 {
SAFETY_CHECKERS_RM_BA1_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
322 {
SAFETY_CHECKERS_RM_BA2_RA,
SAFETY_CHECKERS_RM_RA_SUBMOD1,
SAFETY_CHECKERS_RM_RA_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
324 {
SAFETY_CHECKERS_RM_BA0_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG0_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
325 {
SAFETY_CHECKERS_RM_BA1_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG1_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
327 {
SAFETY_CHECKERS_RM_BA0_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG0_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
328 {
SAFETY_CHECKERS_RM_BA1_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG1_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
330 {
SAFETY_CHECKERS_RM_BA0_UDMA_FLW,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
332 {
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
333 {
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},