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AM62x MCU+ SDK
08.04.00
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51 #ifndef SOC_TISCI_DEVICES_H
52 #define SOC_TISCI_DEVICES_H
60 #define TISCI_DEV_CMP_EVENT_INTROUTER0 1
61 #define TISCI_DEV_DBGSUSPENDROUTER0 2
62 #define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3
63 #define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5
64 #define TISCI_DEV_TIMESYNC_EVENT_ROUTER0 6
65 #define TISCI_DEV_MCU_M4FSS0 7
66 #define TISCI_DEV_MCU_M4FSS0_CBASS_0 8
67 #define TISCI_DEV_MCU_M4FSS0_CORE0 9
68 #define TISCI_DEV_CPSW0 13
69 #define TISCI_DEV_CPT2_AGGR0 14
70 #define TISCI_DEV_STM0 15
71 #define TISCI_DEV_DCC0 16
72 #define TISCI_DEV_DCC1 17
73 #define TISCI_DEV_DCC2 18
74 #define TISCI_DEV_DCC3 19
75 #define TISCI_DEV_DCC4 20
76 #define TISCI_DEV_DCC5 21
77 #define TISCI_DEV_SMS0 22
78 #define TISCI_DEV_MCU_DCC0 23
79 #define TISCI_DEV_DEBUGSS_WRAP0 24
80 #define TISCI_DEV_DMASS0 25
81 #define TISCI_DEV_DMASS0_BCDMA_0 26
82 #define TISCI_DEV_DMASS0_CBASS_0 27
83 #define TISCI_DEV_DMASS0_INTAGGR_0 28
84 #define TISCI_DEV_DMASS0_IPCSS_0 29
85 #define TISCI_DEV_DMASS0_PKTDMA_0 30
86 #define TISCI_DEV_DMASS0_RINGACC_0 33
87 #define TISCI_DEV_MCU_TIMER0 35
88 #define TISCI_DEV_TIMER0 36
89 #define TISCI_DEV_TIMER1 37
90 #define TISCI_DEV_TIMER2 38
91 #define TISCI_DEV_TIMER3 39
92 #define TISCI_DEV_TIMER4 40
93 #define TISCI_DEV_TIMER5 41
94 #define TISCI_DEV_TIMER6 42
95 #define TISCI_DEV_TIMER7 43
96 #define TISCI_DEV_MCU_TIMER1 48
97 #define TISCI_DEV_MCU_TIMER2 49
98 #define TISCI_DEV_MCU_TIMER3 50
99 #define TISCI_DEV_ECAP0 51
100 #define TISCI_DEV_ECAP1 52
101 #define TISCI_DEV_ECAP2 53
102 #define TISCI_DEV_ELM0 54
103 #define TISCI_DEV_EMIF_DATA_ISO_VD 55
104 #define TISCI_DEV_MMCSD0 57
105 #define TISCI_DEV_MMCSD1 58
106 #define TISCI_DEV_EQEP0 59
107 #define TISCI_DEV_EQEP1 60
108 #define TISCI_DEV_WKUP_GTC0 61
109 #define TISCI_DEV_EQEP2 62
110 #define TISCI_DEV_ESM0 63
111 #define TISCI_DEV_WKUP_ESM0 64
112 #define TISCI_DEV_FSS0 73
113 #define TISCI_DEV_FSS0_FSAS_0 74
114 #define TISCI_DEV_FSS0_OSPI_0 75
115 #define TISCI_DEV_GICSS0 76
116 #define TISCI_DEV_GPIO0 77
117 #define TISCI_DEV_GPIO1 78
118 #define TISCI_DEV_MCU_GPIO0 79
119 #define TISCI_DEV_GPMC0 80
120 #define TISCI_DEV_ICSSM0 81
121 #define TISCI_DEV_LED0 83
122 #define TISCI_DEV_DDPA0 85
123 #define TISCI_DEV_EPWM0 86
124 #define TISCI_DEV_EPWM1 87
125 #define TISCI_DEV_EPWM2 88
126 #define TISCI_DEV_WKUP_VTM0 95
127 #define TISCI_DEV_MAILBOX0 96
128 #define TISCI_DEV_MAIN2MCU_VD 97
129 #define TISCI_DEV_MCAN0 98
130 #define TISCI_DEV_MCU_MCRC64_0 100
131 #define TISCI_DEV_MCU2MAIN_VD 101
132 #define TISCI_DEV_I2C0 102
133 #define TISCI_DEV_I2C1 103
134 #define TISCI_DEV_I2C2 104
135 #define TISCI_DEV_I2C3 105
136 #define TISCI_DEV_MCU_I2C0 106
137 #define TISCI_DEV_WKUP_I2C0 107
138 #define TISCI_DEV_WKUP_TIMER0 110
139 #define TISCI_DEV_WKUP_TIMER1 111
140 #define TISCI_DEV_WKUP_UART0 114
141 #define TISCI_DEV_MCRC64_0 116
142 #define TISCI_DEV_WKUP_RTCSS0 117
143 #define TISCI_DEV_R5FSS0_SS0 118
144 #define TISCI_DEV_R5FSS0 119
145 #define TISCI_DEV_R5FSS0_CORE0 121
146 #define TISCI_DEV_RTI0 125
147 #define TISCI_DEV_RTI1 126
148 #define TISCI_DEV_RTI2 127
149 #define TISCI_DEV_RTI3 128
150 #define TISCI_DEV_RTI15 130
151 #define TISCI_DEV_MCU_RTI0 131
152 #define TISCI_DEV_WKUP_RTI0 132
153 #define TISCI_DEV_COMPUTE_CLUSTER0 134
154 #define TISCI_DEV_A53SS0_CORE_0 135
155 #define TISCI_DEV_A53SS0_CORE_1 136
156 #define TISCI_DEV_A53SS0_CORE_2 137
157 #define TISCI_DEV_A53SS0_CORE_3 138
158 #define TISCI_DEV_PSCSS0 139
159 #define TISCI_DEV_WKUP_PSC0 140
160 #define TISCI_DEV_MCSPI0 141
161 #define TISCI_DEV_MCSPI1 142
162 #define TISCI_DEV_MCSPI2 143
163 #define TISCI_DEV_UART0 146
164 #define TISCI_DEV_MCU_MCSPI0 147
165 #define TISCI_DEV_MCU_MCSPI1 148
166 #define TISCI_DEV_MCU_UART0 149
167 #define TISCI_DEV_SPINLOCK0 150
168 #define TISCI_DEV_UART1 152
169 #define TISCI_DEV_UART2 153
170 #define TISCI_DEV_UART3 154
171 #define TISCI_DEV_UART4 155
172 #define TISCI_DEV_UART5 156
173 #define TISCI_DEV_BOARD0 157
174 #define TISCI_DEV_UART6 158
175 #define TISCI_DEV_USB0 161
176 #define TISCI_DEV_USB1 162
177 #define TISCI_DEV_PBIST0 163
178 #define TISCI_DEV_PBIST1 164
179 #define TISCI_DEV_WKUP_PBIST0 165
180 #define TISCI_DEV_A53SS0 166
181 #define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167
182 #define TISCI_DEV_PSC0_FW_0 168
183 #define TISCI_DEV_PSC0 169
184 #define TISCI_DEV_DDR16SS0 170
185 #define TISCI_DEV_DEBUGSS0 171
186 #define TISCI_DEV_A53_RS_BW_LIMITER0 172
187 #define TISCI_DEV_A53_WS_BW_LIMITER1 173
188 #define TISCI_DEV_GPU_RS_BW_LIMITER2 174
189 #define TISCI_DEV_GPU_WS_BW_LIMITER3 175
190 #define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176
191 #define TISCI_DEV_EMIF_CFG_ISO_VD 177
192 #define TISCI_DEV_MAIN_USB0_ISO_VD 178
193 #define TISCI_DEV_MAIN_USB1_ISO_VD 179
194 #define TISCI_DEV_MCU_MCU_16FF0 180
195 #define TISCI_DEV_CPT2_AGGR1 181
196 #define TISCI_DEV_CSI_RX_IF0 182
197 #define TISCI_DEV_DCC6 183
198 #define TISCI_DEV_MMCSD2 184
199 #define TISCI_DEV_DPHY_RX0 185
200 #define TISCI_DEV_DSS0 186
201 #define TISCI_DEV_GPU0 187
202 #define TISCI_DEV_MCU_MCAN0 188
203 #define TISCI_DEV_MCU_MCAN1 189
204 #define TISCI_DEV_MCASP0 190
205 #define TISCI_DEV_MCASP1 191
206 #define TISCI_DEV_MCASP2 192
207 #define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193
208 #define TISCI_DEV_HSM0 225
209 #define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227