Introduction

DMSC controls the power management, security and resource management of the device.

Macros
#define	TISCI_DEV_CMP_EVENT_INTROUTER0 1
	This file contains: More...

#define	TISCI_DEV_DBGSUSPENDROUTER0 2

#define	TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3

#define	TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5

#define	TISCI_DEV_TIMESYNC_EVENT_ROUTER0 6

#define	TISCI_DEV_MCU_M4FSS0 7

#define	TISCI_DEV_MCU_M4FSS0_CBASS_0 8

#define	TISCI_DEV_MCU_M4FSS0_CORE0 9

#define	TISCI_DEV_CPSW0 13

#define	TISCI_DEV_CPT2_AGGR0 14

#define	TISCI_DEV_STM0 15

#define	TISCI_DEV_DCC0 16

#define	TISCI_DEV_DCC1 17

#define	TISCI_DEV_DCC2 18

#define	TISCI_DEV_DCC3 19

#define	TISCI_DEV_DCC4 20

#define	TISCI_DEV_DCC5 21

#define	TISCI_DEV_SMS0 22

#define	TISCI_DEV_MCU_DCC0 23

#define	TISCI_DEV_DEBUGSS_WRAP0 24

#define	TISCI_DEV_DMASS0 25

#define	TISCI_DEV_DMASS0_BCDMA_0 26

#define	TISCI_DEV_DMASS0_CBASS_0 27

#define	TISCI_DEV_DMASS0_INTAGGR_0 28

#define	TISCI_DEV_DMASS0_IPCSS_0 29

#define	TISCI_DEV_DMASS0_PKTDMA_0 30

#define	TISCI_DEV_DMASS0_RINGACC_0 33

#define	TISCI_DEV_MCU_TIMER0 35

#define	TISCI_DEV_TIMER0 36

#define	TISCI_DEV_TIMER1 37

#define	TISCI_DEV_TIMER2 38

#define	TISCI_DEV_TIMER3 39

#define	TISCI_DEV_TIMER4 40

#define	TISCI_DEV_TIMER5 41

#define	TISCI_DEV_TIMER6 42

#define	TISCI_DEV_TIMER7 43

#define	TISCI_DEV_MCU_TIMER1 48

#define	TISCI_DEV_MCU_TIMER2 49

#define	TISCI_DEV_MCU_TIMER3 50

#define	TISCI_DEV_ECAP0 51

#define	TISCI_DEV_ECAP1 52

#define	TISCI_DEV_ECAP2 53

#define	TISCI_DEV_ELM0 54

#define	TISCI_DEV_EMIF_DATA_ISO_VD 55

#define	TISCI_DEV_MMCSD0 57

#define	TISCI_DEV_MMCSD1 58

#define	TISCI_DEV_EQEP0 59

#define	TISCI_DEV_EQEP1 60

#define	TISCI_DEV_WKUP_GTC0 61

#define	TISCI_DEV_EQEP2 62

#define	TISCI_DEV_ESM0 63

#define	TISCI_DEV_WKUP_ESM0 64

#define	TISCI_DEV_FSS0 73

#define	TISCI_DEV_FSS0_FSAS_0 74

#define	TISCI_DEV_FSS0_OSPI_0 75

#define	TISCI_DEV_GICSS0 76

#define	TISCI_DEV_GPIO0 77

#define	TISCI_DEV_GPIO1 78

#define	TISCI_DEV_MCU_GPIO0 79

#define	TISCI_DEV_GPMC0 80

#define	TISCI_DEV_ICSSM0 81

#define	TISCI_DEV_LED0 83

#define	TISCI_DEV_DDPA0 85

#define	TISCI_DEV_EPWM0 86

#define	TISCI_DEV_EPWM1 87

#define	TISCI_DEV_EPWM2 88

#define	TISCI_DEV_WKUP_VTM0 95

#define	TISCI_DEV_MAILBOX0 96

#define	TISCI_DEV_MAIN2MCU_VD 97

#define	TISCI_DEV_MCAN0 98

#define	TISCI_DEV_MCU_MCRC64_0 100

#define	TISCI_DEV_MCU2MAIN_VD 101

#define	TISCI_DEV_I2C0 102

#define	TISCI_DEV_I2C1 103

#define	TISCI_DEV_I2C2 104

#define	TISCI_DEV_I2C3 105

#define	TISCI_DEV_MCU_I2C0 106

#define	TISCI_DEV_WKUP_I2C0 107

#define	TISCI_DEV_WKUP_TIMER0 110

#define	TISCI_DEV_WKUP_TIMER1 111

#define	TISCI_DEV_WKUP_UART0 114

#define	TISCI_DEV_MCRC64_0 116

#define	TISCI_DEV_WKUP_RTCSS0 117

#define	TISCI_DEV_R5FSS0_SS0 118

#define	TISCI_DEV_R5FSS0 119

#define	TISCI_DEV_R5FSS0_CORE0 121

#define	TISCI_DEV_RTI0 125

#define	TISCI_DEV_RTI1 126

#define	TISCI_DEV_RTI2 127

#define	TISCI_DEV_RTI3 128

#define	TISCI_DEV_RTI15 130

#define	TISCI_DEV_MCU_RTI0 131

#define	TISCI_DEV_WKUP_RTI0 132

#define	TISCI_DEV_COMPUTE_CLUSTER0 134

#define	TISCI_DEV_A53SS0_CORE_0 135

#define	TISCI_DEV_A53SS0_CORE_1 136

#define	TISCI_DEV_A53SS0_CORE_2 137

#define	TISCI_DEV_A53SS0_CORE_3 138

#define	TISCI_DEV_PSCSS0 139

#define	TISCI_DEV_WKUP_PSC0 140

#define	TISCI_DEV_MCSPI0 141

#define	TISCI_DEV_MCSPI1 142

#define	TISCI_DEV_MCSPI2 143

#define	TISCI_DEV_UART0 146

#define	TISCI_DEV_MCU_MCSPI0 147

#define	TISCI_DEV_MCU_MCSPI1 148

#define	TISCI_DEV_MCU_UART0 149

#define	TISCI_DEV_SPINLOCK0 150

#define	TISCI_DEV_UART1 152

#define	TISCI_DEV_UART2 153

#define	TISCI_DEV_UART3 154

#define	TISCI_DEV_UART4 155

#define	TISCI_DEV_UART5 156

#define	TISCI_DEV_BOARD0 157

#define	TISCI_DEV_UART6 158

#define	TISCI_DEV_USB0 161

#define	TISCI_DEV_USB1 162

#define	TISCI_DEV_PBIST0 163

#define	TISCI_DEV_PBIST1 164

#define	TISCI_DEV_WKUP_PBIST0 165

#define	TISCI_DEV_A53SS0 166

#define	TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167

#define	TISCI_DEV_PSC0_FW_0 168

#define	TISCI_DEV_PSC0 169

#define	TISCI_DEV_DDR16SS0 170

#define	TISCI_DEV_DEBUGSS0 171

#define	TISCI_DEV_A53_RS_BW_LIMITER0 172

#define	TISCI_DEV_A53_WS_BW_LIMITER1 173

#define	TISCI_DEV_GPU_RS_BW_LIMITER2 174

#define	TISCI_DEV_GPU_WS_BW_LIMITER3 175

#define	TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176

#define	TISCI_DEV_EMIF_CFG_ISO_VD 177

#define	TISCI_DEV_MAIN_USB0_ISO_VD 178

#define	TISCI_DEV_MAIN_USB1_ISO_VD 179

#define	TISCI_DEV_MCU_MCU_16FF0 180

#define	TISCI_DEV_CPT2_AGGR1 181

#define	TISCI_DEV_CSI_RX_IF0 182

#define	TISCI_DEV_DCC6 183

#define	TISCI_DEV_MMCSD2 184

#define	TISCI_DEV_DPHY_RX0 185

#define	TISCI_DEV_DSS0 186

#define	TISCI_DEV_GPU0 187

#define	TISCI_DEV_MCU_MCAN0 188

#define	TISCI_DEV_MCU_MCAN1 189

#define	TISCI_DEV_MCASP0 190

#define	TISCI_DEV_MCASP1 191

#define	TISCI_DEV_MCASP2 192

#define	TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193

#define	TISCI_DEV_HSM0 225

#define	TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227

Macro Definition Documentation

◆ TISCI_DEV_CMP_EVENT_INTROUTER0

#define TISCI_DEV_CMP_EVENT_INTROUTER0 1

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

Data version: 220811_185331

◆ TISCI_DEV_DBGSUSPENDROUTER0

#define TISCI_DEV_DBGSUSPENDROUTER0 2

◆ TISCI_DEV_MAIN_GPIOMUX_INTROUTER0

#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3

◆ TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0

#define TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0 5

◆ TISCI_DEV_TIMESYNC_EVENT_ROUTER0

#define TISCI_DEV_TIMESYNC_EVENT_ROUTER0 6

◆ TISCI_DEV_MCU_M4FSS0

#define TISCI_DEV_MCU_M4FSS0 7

◆ TISCI_DEV_MCU_M4FSS0_CBASS_0

#define TISCI_DEV_MCU_M4FSS0_CBASS_0 8

◆ TISCI_DEV_MCU_M4FSS0_CORE0

#define TISCI_DEV_MCU_M4FSS0_CORE0 9

◆ TISCI_DEV_CPSW0

#define TISCI_DEV_CPSW0 13

◆ TISCI_DEV_CPT2_AGGR0

#define TISCI_DEV_CPT2_AGGR0 14

◆ TISCI_DEV_STM0

#define TISCI_DEV_STM0 15

◆ TISCI_DEV_DCC0

#define TISCI_DEV_DCC0 16

◆ TISCI_DEV_DCC1

#define TISCI_DEV_DCC1 17

◆ TISCI_DEV_DCC2

#define TISCI_DEV_DCC2 18

◆ TISCI_DEV_DCC3

#define TISCI_DEV_DCC3 19

◆ TISCI_DEV_DCC4

#define TISCI_DEV_DCC4 20

◆ TISCI_DEV_DCC5

#define TISCI_DEV_DCC5 21

◆ TISCI_DEV_SMS0

#define TISCI_DEV_SMS0 22

◆ TISCI_DEV_MCU_DCC0

#define TISCI_DEV_MCU_DCC0 23

◆ TISCI_DEV_DEBUGSS_WRAP0

#define TISCI_DEV_DEBUGSS_WRAP0 24

◆ TISCI_DEV_DMASS0

#define TISCI_DEV_DMASS0 25

◆ TISCI_DEV_DMASS0_BCDMA_0

#define TISCI_DEV_DMASS0_BCDMA_0 26

◆ TISCI_DEV_DMASS0_CBASS_0

#define TISCI_DEV_DMASS0_CBASS_0 27

◆ TISCI_DEV_DMASS0_INTAGGR_0

#define TISCI_DEV_DMASS0_INTAGGR_0 28

◆ TISCI_DEV_DMASS0_IPCSS_0

#define TISCI_DEV_DMASS0_IPCSS_0 29

◆ TISCI_DEV_DMASS0_PKTDMA_0

#define TISCI_DEV_DMASS0_PKTDMA_0 30

◆ TISCI_DEV_DMASS0_RINGACC_0

#define TISCI_DEV_DMASS0_RINGACC_0 33

◆ TISCI_DEV_MCU_TIMER0

#define TISCI_DEV_MCU_TIMER0 35

◆ TISCI_DEV_TIMER0

#define TISCI_DEV_TIMER0 36

◆ TISCI_DEV_TIMER1

#define TISCI_DEV_TIMER1 37

◆ TISCI_DEV_TIMER2

#define TISCI_DEV_TIMER2 38

◆ TISCI_DEV_TIMER3

#define TISCI_DEV_TIMER3 39

◆ TISCI_DEV_TIMER4

#define TISCI_DEV_TIMER4 40

◆ TISCI_DEV_TIMER5

#define TISCI_DEV_TIMER5 41

◆ TISCI_DEV_TIMER6

#define TISCI_DEV_TIMER6 42

◆ TISCI_DEV_TIMER7

#define TISCI_DEV_TIMER7 43

◆ TISCI_DEV_MCU_TIMER1

#define TISCI_DEV_MCU_TIMER1 48

◆ TISCI_DEV_MCU_TIMER2

#define TISCI_DEV_MCU_TIMER2 49

◆ TISCI_DEV_MCU_TIMER3

#define TISCI_DEV_MCU_TIMER3 50

◆ TISCI_DEV_ECAP0

#define TISCI_DEV_ECAP0 51

◆ TISCI_DEV_ECAP1

#define TISCI_DEV_ECAP1 52

◆ TISCI_DEV_ECAP2

#define TISCI_DEV_ECAP2 53

◆ TISCI_DEV_ELM0

#define TISCI_DEV_ELM0 54

◆ TISCI_DEV_EMIF_DATA_ISO_VD

#define TISCI_DEV_EMIF_DATA_ISO_VD 55

◆ TISCI_DEV_MMCSD0

#define TISCI_DEV_MMCSD0 57

◆ TISCI_DEV_MMCSD1

#define TISCI_DEV_MMCSD1 58

◆ TISCI_DEV_EQEP0

#define TISCI_DEV_EQEP0 59

◆ TISCI_DEV_EQEP1

#define TISCI_DEV_EQEP1 60

◆ TISCI_DEV_WKUP_GTC0

#define TISCI_DEV_WKUP_GTC0 61

◆ TISCI_DEV_EQEP2

#define TISCI_DEV_EQEP2 62

◆ TISCI_DEV_ESM0

#define TISCI_DEV_ESM0 63

◆ TISCI_DEV_WKUP_ESM0

#define TISCI_DEV_WKUP_ESM0 64

◆ TISCI_DEV_FSS0

#define TISCI_DEV_FSS0 73

◆ TISCI_DEV_FSS0_FSAS_0

#define TISCI_DEV_FSS0_FSAS_0 74

◆ TISCI_DEV_FSS0_OSPI_0

#define TISCI_DEV_FSS0_OSPI_0 75

◆ TISCI_DEV_GICSS0

#define TISCI_DEV_GICSS0 76

◆ TISCI_DEV_GPIO0

#define TISCI_DEV_GPIO0 77

◆ TISCI_DEV_GPIO1

#define TISCI_DEV_GPIO1 78

◆ TISCI_DEV_MCU_GPIO0

#define TISCI_DEV_MCU_GPIO0 79

◆ TISCI_DEV_GPMC0

#define TISCI_DEV_GPMC0 80

◆ TISCI_DEV_ICSSM0

#define TISCI_DEV_ICSSM0 81

◆ TISCI_DEV_LED0

#define TISCI_DEV_LED0 83

◆ TISCI_DEV_DDPA0

#define TISCI_DEV_DDPA0 85

◆ TISCI_DEV_EPWM0

#define TISCI_DEV_EPWM0 86

◆ TISCI_DEV_EPWM1

#define TISCI_DEV_EPWM1 87

◆ TISCI_DEV_EPWM2

#define TISCI_DEV_EPWM2 88

◆ TISCI_DEV_WKUP_VTM0

#define TISCI_DEV_WKUP_VTM0 95

◆ TISCI_DEV_MAILBOX0

#define TISCI_DEV_MAILBOX0 96

◆ TISCI_DEV_MAIN2MCU_VD

#define TISCI_DEV_MAIN2MCU_VD 97

◆ TISCI_DEV_MCAN0

#define TISCI_DEV_MCAN0 98

◆ TISCI_DEV_MCU_MCRC64_0

#define TISCI_DEV_MCU_MCRC64_0 100

◆ TISCI_DEV_MCU2MAIN_VD

#define TISCI_DEV_MCU2MAIN_VD 101

◆ TISCI_DEV_I2C0

#define TISCI_DEV_I2C0 102

◆ TISCI_DEV_I2C1

#define TISCI_DEV_I2C1 103

◆ TISCI_DEV_I2C2

#define TISCI_DEV_I2C2 104

◆ TISCI_DEV_I2C3

#define TISCI_DEV_I2C3 105

◆ TISCI_DEV_MCU_I2C0

#define TISCI_DEV_MCU_I2C0 106

◆ TISCI_DEV_WKUP_I2C0

#define TISCI_DEV_WKUP_I2C0 107

◆ TISCI_DEV_WKUP_TIMER0

#define TISCI_DEV_WKUP_TIMER0 110

◆ TISCI_DEV_WKUP_TIMER1

#define TISCI_DEV_WKUP_TIMER1 111

◆ TISCI_DEV_WKUP_UART0

#define TISCI_DEV_WKUP_UART0 114

◆ TISCI_DEV_MCRC64_0

#define TISCI_DEV_MCRC64_0 116

◆ TISCI_DEV_WKUP_RTCSS0

#define TISCI_DEV_WKUP_RTCSS0 117

◆ TISCI_DEV_R5FSS0_SS0

#define TISCI_DEV_R5FSS0_SS0 118

◆ TISCI_DEV_R5FSS0

#define TISCI_DEV_R5FSS0 119

◆ TISCI_DEV_R5FSS0_CORE0

#define TISCI_DEV_R5FSS0_CORE0 121

◆ TISCI_DEV_RTI0

#define TISCI_DEV_RTI0 125

◆ TISCI_DEV_RTI1

#define TISCI_DEV_RTI1 126

◆ TISCI_DEV_RTI2

#define TISCI_DEV_RTI2 127

◆ TISCI_DEV_RTI3

#define TISCI_DEV_RTI3 128

◆ TISCI_DEV_RTI15

#define TISCI_DEV_RTI15 130

◆ TISCI_DEV_MCU_RTI0

#define TISCI_DEV_MCU_RTI0 131

◆ TISCI_DEV_WKUP_RTI0

#define TISCI_DEV_WKUP_RTI0 132

◆ TISCI_DEV_COMPUTE_CLUSTER0

#define TISCI_DEV_COMPUTE_CLUSTER0 134

◆ TISCI_DEV_A53SS0_CORE_0

#define TISCI_DEV_A53SS0_CORE_0 135

◆ TISCI_DEV_A53SS0_CORE_1

#define TISCI_DEV_A53SS0_CORE_1 136

◆ TISCI_DEV_A53SS0_CORE_2

#define TISCI_DEV_A53SS0_CORE_2 137

◆ TISCI_DEV_A53SS0_CORE_3

#define TISCI_DEV_A53SS0_CORE_3 138

◆ TISCI_DEV_PSCSS0

#define TISCI_DEV_PSCSS0 139

◆ TISCI_DEV_WKUP_PSC0

#define TISCI_DEV_WKUP_PSC0 140

◆ TISCI_DEV_MCSPI0

#define TISCI_DEV_MCSPI0 141

◆ TISCI_DEV_MCSPI1

#define TISCI_DEV_MCSPI1 142

◆ TISCI_DEV_MCSPI2

#define TISCI_DEV_MCSPI2 143

◆ TISCI_DEV_UART0

#define TISCI_DEV_UART0 146

◆ TISCI_DEV_MCU_MCSPI0

#define TISCI_DEV_MCU_MCSPI0 147

◆ TISCI_DEV_MCU_MCSPI1

#define TISCI_DEV_MCU_MCSPI1 148

◆ TISCI_DEV_MCU_UART0

#define TISCI_DEV_MCU_UART0 149

◆ TISCI_DEV_SPINLOCK0

#define TISCI_DEV_SPINLOCK0 150

◆ TISCI_DEV_UART1

#define TISCI_DEV_UART1 152

◆ TISCI_DEV_UART2

#define TISCI_DEV_UART2 153

◆ TISCI_DEV_UART3

#define TISCI_DEV_UART3 154

◆ TISCI_DEV_UART4

#define TISCI_DEV_UART4 155

◆ TISCI_DEV_UART5

#define TISCI_DEV_UART5 156

◆ TISCI_DEV_BOARD0

#define TISCI_DEV_BOARD0 157

◆ TISCI_DEV_UART6

#define TISCI_DEV_UART6 158

◆ TISCI_DEV_USB0

#define TISCI_DEV_USB0 161

◆ TISCI_DEV_USB1

#define TISCI_DEV_USB1 162

◆ TISCI_DEV_PBIST0

#define TISCI_DEV_PBIST0 163

◆ TISCI_DEV_PBIST1

#define TISCI_DEV_PBIST1 164

◆ TISCI_DEV_WKUP_PBIST0

#define TISCI_DEV_WKUP_PBIST0 165

◆ TISCI_DEV_A53SS0

#define TISCI_DEV_A53SS0 166

◆ TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0

#define TISCI_DEV_COMPUTE_CLUSTER0_PBIST_0 167

◆ TISCI_DEV_PSC0_FW_0

#define TISCI_DEV_PSC0_FW_0 168

◆ TISCI_DEV_PSC0

#define TISCI_DEV_PSC0 169

◆ TISCI_DEV_DDR16SS0

#define TISCI_DEV_DDR16SS0 170

◆ TISCI_DEV_DEBUGSS0

#define TISCI_DEV_DEBUGSS0 171

◆ TISCI_DEV_A53_RS_BW_LIMITER0

#define TISCI_DEV_A53_RS_BW_LIMITER0 172

◆ TISCI_DEV_A53_WS_BW_LIMITER1

#define TISCI_DEV_A53_WS_BW_LIMITER1 173

◆ TISCI_DEV_GPU_RS_BW_LIMITER2

#define TISCI_DEV_GPU_RS_BW_LIMITER2 174

◆ TISCI_DEV_GPU_WS_BW_LIMITER3

#define TISCI_DEV_GPU_WS_BW_LIMITER3 175

◆ TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0

#define TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176

◆ TISCI_DEV_EMIF_CFG_ISO_VD

#define TISCI_DEV_EMIF_CFG_ISO_VD 177

◆ TISCI_DEV_MAIN_USB0_ISO_VD

#define TISCI_DEV_MAIN_USB0_ISO_VD 178

◆ TISCI_DEV_MAIN_USB1_ISO_VD

#define TISCI_DEV_MAIN_USB1_ISO_VD 179

◆ TISCI_DEV_MCU_MCU_16FF0

#define TISCI_DEV_MCU_MCU_16FF0 180

◆ TISCI_DEV_CPT2_AGGR1

#define TISCI_DEV_CPT2_AGGR1 181

◆ TISCI_DEV_CSI_RX_IF0

#define TISCI_DEV_CSI_RX_IF0 182

◆ TISCI_DEV_DCC6

#define TISCI_DEV_DCC6 183

◆ TISCI_DEV_MMCSD2

#define TISCI_DEV_MMCSD2 184

◆ TISCI_DEV_DPHY_RX0

#define TISCI_DEV_DPHY_RX0 185

◆ TISCI_DEV_DSS0

#define TISCI_DEV_DSS0 186

◆ TISCI_DEV_GPU0

#define TISCI_DEV_GPU0 187

◆ TISCI_DEV_MCU_MCAN0

#define TISCI_DEV_MCU_MCAN0 188

◆ TISCI_DEV_MCU_MCAN1

#define TISCI_DEV_MCU_MCAN1 189

◆ TISCI_DEV_MCASP0

#define TISCI_DEV_MCASP0 190

◆ TISCI_DEV_MCASP1

#define TISCI_DEV_MCASP1 191

◆ TISCI_DEV_MCASP2

#define TISCI_DEV_MCASP2 192

◆ TISCI_DEV_CLK_32K_RC_SEL_DEV_VD

#define TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193

◆ TISCI_DEV_HSM0

#define TISCI_DEV_HSM0 225

◆ TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD

#define TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227