Various resources of the SOC like the number of DMA channels, number of interrupt router outputs, number of interrupt aggregator virtual interrupt numbers etc. are usually managed by a resource management system or a resource manager.
In the case of AM62X devices, this is managed by the DM Firmware (Divice Manager Firmware) running on the DM R5 core. Once the DM firmware is loaded on DM R5 and is initialized, it will read a certain configuration data regarding the resources we would be using. Rom bootloader (RBL) should have loaded this as part of bootflow. This is largely an array of resource assignment entries, with each entry specifying the start number of the resource, count or number of resource needed, type of resource, host id of the core which will request for this resource, etc. Later when the request for a specific resource is made, the DM firmware will cross check the request parameters with this already sent configuration data, and the requested resources will only be allocated if that falls within the range in this configuration data. We call this the Resource Management Board Configuration or RM boardcfg.
sciclient_defaultBoardcfg_rm.c
file at path {SDK_ROOT_DIRECTORY}\source\drivers\sciclient\sciclient_default_boardcfg\am62x\
location..resasg_entries = {
. This is an array of resource assignment entries. Resource assignment entries are structs with members
{SDK_ROOT_DIRECTORY}\source\drivers\sciclient\include\tisci\am62x\tisci_hosts.h
file.HOST ID | Core |
---|---|
TISCI_HOST_ID_TIFS (0U) | TIFS ARM Cortex M4 |
TISCI_HOST_ID_DM (254U) | DM(Non Secure): Device Management |
TISCI_HOST_ID_MAIN_0_R5_0 (35U) | Cortex R5FSS0_0 (Secure Context) |
TISCI_HOST_ID_MAIN_0_R5_1 (36U) | Cortex R5FSS0_0 (Non-Secure Context) |
TISCI_HOST_ID_MAIN_0_R5_2 (37U) | Cortex R5FSS0_0 (Secure Context) |
TISCI_HOST_ID_MAIN_0_R5_3 (38U) | Cortex R5FSS0_0 (Non-Secure Context) |
TISCI_HOST_ID_A53_0 (10U) | Cortex A53SS0_0 (Secure Context) |
TISCI_HOST_ID_A53_0 (11U) | Cortex A53SS0_0 (Secure Context) |
TISCI_HOST_ID_A53_0 (12U) | Cortex A53SS0_1 (Non-Secure Context) |
TISCI_HOST_ID_A53_0 (13U) | Cortex A53SS0_1 (Non-Secure Context) |
TISCI_HOST_ID_M4_0 (30U) | Cortex M4 (Non-Secure Context) |
TISCI_HOST_ID_GPU_0 (31U) | GPU (Non-Secure Context) |
TISCI_HOST_ID_A53_4 (14U) | Cortex Cortex A53SS0_0 (Non-Secure Context) |
TISCI_HOST_ID_DM2TIFS (250U) | DM2TIFS(Secure): DM to TIFS communication |
TISCI_HOST_ID_TIFS2DM (251U) | TIFS2DM(Non Secure): TIFS to DM communication |
sciclient_set_boardcfg
application are updated with these changes. For this one can follow SYSFW Board Config Generation section