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AM62Px MCU+ SDK
11.01.00
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AM62Px MCU+ SDK
11.01.00
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UDMA PDMA channel Static TR parameters.
Data Fields | |
| uint32_t | elemSize |
| uint32_t | elemCnt |
| uint32_t | fifoCnt |
| uint8_t | burst |
| uint8_t | acc32 |
| uint8_t | eol |
| uint8_t | isAasrcCh |
| uint8_t | groupMode |
| uint8_t | dmaReqReset |
| uint8_t | lastSlot |
| uint8_t | firstSlot |
| uint16_t | dmaReqMask |
| uint32_t | orderTable0 |
| uint32_t | orderTable1 |
| uint32_t Udma_ChPdmaPrms::elemSize |
[IN] Element size. This field specifies how much data is transferred in each write which is performed by the PDMA. This is the X static TR parameter of PDMA.
In case of MCAN TX/RX PDMA channel, this is not used and should be set to 0.
Refer Udma_PdmaElemSize for supported values.
| uint32_t Udma_ChPdmaPrms::elemCnt |
[IN] Element count. This field specifies how many elements to transfer each time a trigger is received on the PDMA channel. This is the Y static TR parameter of PDMA.
In case of MCAN PDMA channel, this represents the buffer size. In case of MCAN TX, this field specifies how many bytes should be written to an MCAN TX buffer. This field includes the 8 byte MCAN header on the initial packet fragment. The PDMA will break up the source packet into fragments of this buffer size, copying the 8 byte MCAN header for the initial fragment, and then skipping it for each additional fragment and thus reusing the header from the first fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72. In case of MCAN RX, this field specifies how many bytes should be read from an MCAN RX buffer. This field includes the 8 byte MCAN header on the initial packet fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72.
| uint32_t Udma_ChPdmaPrms::fifoCnt |
[IN] FIFO count. This field specifies how many full FIFO operations comprise a complete packet. When the count has been reached, the PDMA will close the packet with an 'EOP' indication. If this parameter is set to 0, then no packet delineation is supplied by the PDMA and all framing is controlled via the UDMA TR.
This is the Z static TR parameter of PDMA. This is NA for TX and should be set to 0. In case of MCAN RX, this represents the buffer count. This field specifies how many MCAN RX buffers should be read before closing the CPPI packet with an 'EOP' indication. When this count is greater than 1, multiple MCAN RX buffers will be read into a single CPPI packet buffer. The 8 byte MCAN header will be skipped on subsequent MCAN buffer reads. Setting this field to NULL will suppress all packet delineation, and should be avoided.
| uint8_t Udma_ChPdmaPrms::burst |
[IN] Burst mode. Enable VBUSP burst mode for this channel.
Since MCAN buffers are stored in linear memory, the burst mode for MCAN is a simple linear burst across the transfer window. The max burst size is set to the 72 byte size of the MCAN buffer. This will allow a full MCAN packet to be read out as a single burst.
| uint8_t Udma_ChPdmaPrms::acc32 |
[IN] 32b access. Enable 32b access mode.
When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide.
| uint8_t Udma_ChPdmaPrms::eol |
[IN] EOL mode. Enable eol mode.
EOL mode. Normally, when the Z count of FIFO operations has been reached, the PDMA will close the packet with an 'EOP' indication. When this flag is set, the PDMA will instead trigger an EOL at the completion of Z.
| uint8_t Udma_ChPdmaPrms::isAasrcCh |
[IN] Is peer paired AASRC
Flag to indicate if the paired peer channel is of AASRC
| uint8_t Udma_ChPdmaPrms::groupMode |
[IN] Group mode
Group mode. It will look for Group Mode DMA requests, and access the Group Mode FIFOs. When clear, the channel is 'Stream Mode'. It will look for Stream FIFO DMA requests, and access the Stream Mode FIFOs.
| uint8_t Udma_ChPdmaPrms::dmaReqReset |
[IN] DMA request reset
When set, resets any latched DMA request using the DmaReqMask. This bit is self-clearing. It should be used to synchronize the AASRC event status with the PDMA in the event that the AASRC has been previously used and it is not known if the PDMA may have latched, and is holding, previous DMA requests.
| uint8_t Udma_ChPdmaPrms::lastSlot |
[IN] Last slot index
This is the index (0-15) of the last slot in the TX/RX FIFO ordering table used by this channel. The ordering table is read to get the FIFO index to access for each slot, starting with the first and ending with the last.
| uint8_t Udma_ChPdmaPrms::firstSlot |
[IN] First slot index
This is the index (0-15) of the first slot in the TX/RX FIFO ordering table used by this channel. The ordering table is read to get the FIFO index to access for each slot, starting with the first and ending with the last.
| uint16_t Udma_ChPdmaPrms::dmaReqMask |
[IN] DMA request mask
This field holds a set of flags indicating which AASRC DMA requests must fire in order for this channel to activate.
In Steam Mode, these 16 flags correspond to the 16 DMA requests for each TX/RX FIFO. The flags corresponding to all TX/RX FIFOs involved with the channel should be set to 1.
In Group Mode, these flags indicate which Group Mode DMA requests must fire. In this case, only bits 3:0 are relevant and only one bit should be set to 1 as a DMA channel only services a single group.
| uint32_t Udma_ChPdmaPrms::orderTable0 |
[IN] Order Table 0
FIFO index values is determined by this reg value. 31:28 Entry7 FIFO Index for slot 7 27:24 Entry6 FIFO Index for slot 6 23:20 Entry5 FIFO Index for slot 5 19:16 Entry4 FIFO Index for slot 4 15:12 Entry3 FIFO Index for slot 3 11:8 Entry2 FIFO Index for slot 2 7:4 Entry1 FIFO Index for slot 1 3:0 Entry0 FIFO Index for slot 0 Note: This is a single register that is shared by all RX or TX threads
| uint32_t Udma_ChPdmaPrms::orderTable1 |
[IN] Order Table 1
FIFO index values is determined by this reg value 31:28 Entry15 FIFO Index for slot 15 27:24 Entry14 FIFO Index for slot 14 23:20 Entry13 FIFO Index for slot 13 19:16 Entry12 FIFO Index for slot 12 15:12 Entry11 FIFO Index for slot 11 11:8 Entry10 FIFO Index for slot 10 7:4 Entry9 FIFO Index for slot 9 3:0 Entry8 FIFO Index for slot 8 Note: This is a single register that is shared by all RX or TX threads
1.8.20