CSL_dss_common1Regs Struct Reference

Data Fields
volatile uint8_t	Resv_36 [36]
volatile uint32_t	DISPC_IRQ_EOI
volatile uint32_t	DISPC_IRQSTATUS_RAW
volatile uint32_t	DISPC_IRQSTATUS
volatile uint32_t	DISPC_IRQENABLE_SET
volatile uint8_t	Resv_64 [12]
volatile uint32_t	DISPC_IRQENABLE_CLR
volatile uint32_t	VID_IRQENABLE_0
volatile uint32_t	VID_IRQENABLE_1
volatile uint8_t	Resv_84 [8]
volatile uint32_t	DISPC_SECURE
volatile uint32_t	VID_IRQSTATUS_0
volatile uint32_t	VID_IRQSTATUS_1
volatile uint8_t	Resv_112 [16]
volatile uint32_t	VP_IRQENABLE_0
volatile uint32_t	VP_IRQENABLE_1
volatile uint8_t	Resv_124 [4]
volatile uint32_t	VP_IRQSTATUS_0
volatile uint32_t	VP_IRQSTATUS_1

Field Documentation

Resv_36

volatile uint8_t CSL_dss_common1Regs::Resv_36[36]

DISPC_IRQ_EOI

volatile uint32_t CSL_dss_common1Regs::DISPC_IRQ_EOI

DISPC_IRQSTATUS_RAW

volatile uint32_t CSL_dss_common1Regs::DISPC_IRQSTATUS_RAW

DISPC_IRQSTATUS

volatile uint32_t CSL_dss_common1Regs::DISPC_IRQSTATUS

DISPC_IRQENABLE_SET

volatile uint32_t CSL_dss_common1Regs::DISPC_IRQENABLE_SET

Resv_64

volatile uint8_t CSL_dss_common1Regs::Resv_64[12]

DISPC_IRQENABLE_CLR

volatile uint32_t CSL_dss_common1Regs::DISPC_IRQENABLE_CLR

VID_IRQENABLE_0

volatile uint32_t CSL_dss_common1Regs::VID_IRQENABLE_0

VID_IRQENABLE_1

volatile uint32_t CSL_dss_common1Regs::VID_IRQENABLE_1

Resv_84

volatile uint8_t CSL_dss_common1Regs::Resv_84[8]

DISPC_SECURE

volatile uint32_t CSL_dss_common1Regs::DISPC_SECURE

VID_IRQSTATUS_0

volatile uint32_t CSL_dss_common1Regs::VID_IRQSTATUS_0

VID_IRQSTATUS_1

volatile uint32_t CSL_dss_common1Regs::VID_IRQSTATUS_1

Resv_112

volatile uint8_t CSL_dss_common1Regs::Resv_112[16]

VP_IRQENABLE_0

volatile uint32_t CSL_dss_common1Regs::VP_IRQENABLE_0

VP_IRQENABLE_1

volatile uint32_t CSL_dss_common1Regs::VP_IRQENABLE_1

Resv_124

volatile uint8_t CSL_dss_common1Regs::Resv_124[4]

VP_IRQSTATUS_0

volatile uint32_t CSL_dss_common1Regs::VP_IRQSTATUS_0

VP_IRQSTATUS_1

volatile uint32_t CSL_dss_common1Regs::VP_IRQSTATUS_1