Detailed Description

Advance Signal Configuration for the LCD.

Data Fields
uint32_t	hVAlign

uint32_t	hVClkControl

uint32_t	hVClkRiseFall

uint32_t	acBI

uint32_t	acB

uint32_t	vSyncGated

uint32_t	hSyncGated

uint32_t	pixelClockGated

uint32_t	pixelDataGated

uint32_t	pixelGated

Field Documentation

◆ hVAlign

uint32_t CSL_DssVpLcdAdvSignalCfg::hVAlign

Defines the alignment between HSYNC and VSYNC assertion. For valid values see CSL_DssVpLcdHVSyncAlign

◆ hVClkControl

uint32_t CSL_DssVpLcdAdvSignalCfg::hVClkControl

HSYNC/VSYNC pixel clock control on/off. For valid values see CSL_DssVpLcdHVClkControl

◆ hVClkRiseFall

uint32_t CSL_DssVpLcdAdvSignalCfg::hVClkRiseFall

Program HSYNC/VSYNC rise or fall For valid values see Fvid2_EdgePolarity

◆ acBI

uint32_t CSL_DssVpLcdAdvSignalCfg::acBI

AC bias pin transitions per interrupt. Value (from 0 to 15) used to specify the number of AC bias pin transitions

◆ acB

uint32_t CSL_DssVpLcdAdvSignalCfg::acB

AC bias pin frequency RW 0x00 Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge buildup within the display

◆ vSyncGated

uint32_t CSL_DssVpLcdAdvSignalCfg::vSyncGated

VSYNC gated enabled FALSE: VSYNC gated disabled TRUE: VSYNC gated enabled

◆ hSyncGated

uint32_t CSL_DssVpLcdAdvSignalCfg::hSyncGated

HSYNC gated enabled FALSE: HSYNC gated disabled TRUE: HSYNC gated enabled

◆ pixelClockGated

uint32_t CSL_DssVpLcdAdvSignalCfg::pixelClockGated

Pixel clock gated enabled FALSE: Pixel clock gated disabled TRUE: Pixel clock gated enabled

◆ pixelDataGated

uint32_t CSL_DssVpLcdAdvSignalCfg::pixelDataGated

Pixel data gated enabled FALSE: Pixel data gated disabled TRUE: Pixel data gated enabled

◆ pixelGated

uint32_t CSL_DssVpLcdAdvSignalCfg::pixelGated

Pixel gated enable (only for TFT) FALSE: Pixel clock always toggles (only in TFT mode) TRUE: Pixel clock toggles only when there is valid data to display (only in TFT mode)