Data Structures
struct	SDL_VTM_cfg1Regs_VD

struct	SDL_VTM_cfg1Regs_TMPSENS

struct	SDL_VTM_cfg1Regs

struct	SDL_VTM_cfg2Regs_TMPSENS

struct	SDL_VTM_cfg2Regs

Macros
#define	SDL_VTM_TS_MAX_NUM (8U)

#define	SDL_VTM_CFG1_PID (0x00000000U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0 (0x00000004U)

#define	SDL_VTM_CFG1_VD_DEVINFO(VTM_VD) (0x00000100U+((VTM_VD)*0x20U))

#define	SDL_VTM_CFG1_VD_OPPVID(VTM_VD) (0x00000104U+((VTM_VD)*0x20U))

#define	SDL_VTM_CFG1_VD_EVT_STAT(VTM_VD) (0x00000108U+((VTM_VD)*0x20U))

#define	SDL_VTM_CFG1_VD_EVT_SET(VTM_VD) (0x0000010CU+((VTM_VD)*0x20U))

#define	SDL_VTM_CFG1_VD_EVT_CLR(VTM_VD) (0x00000110U+((VTM_VD)*0x20U))

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET (0x00000204U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR (0x00000208U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET (0x00000214U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR (0x00000218U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET (0x00000224U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR (0x00000228U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET (0x00000234U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR (0x00000238U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET (0x00000244U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR (0x00000248U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET (0x00000254U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR (0x00000258U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL(TMPSENS) (0x00000300U+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG1_TMPSENS_STAT(TMPSENS) (0x00000308U+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG1_TMPSENS_TH(TMPSENS) (0x0000030CU+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG1_TMPSENS_TH2(TMPSENS) (0x00000310U+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG1_DEVINFO_VD_MAP_MASK (0x00000F00U)

#define	SDL_VTM_CFG1_DEVINFO_VD_MAP_SHIFT (0x00000008U)

#define	SDL_VTM_CFG1_DEVINFO_VD_MAP_MAX (0x0000000FU)

#define	SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MASK (0x00001000U)

#define	SDL_VTM_CFG1_DEVINFO_AVS0_SUP_SHIFT (0x0000000CU)

#define	SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MAX (0x00000001U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MASK (0x0000FF00U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_SHIFT (0x00000008U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MASK (0x00FF0000U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MASK (0xFF000000U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_SHIFT (0x00000018U)

#define	SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MASK (0x0000FF00U)

#define	SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_SHIFT (0x00000008U)

#define	SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MASK (0x00FF0000U)

#define	SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MASK (0xFF000000U)

#define	SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_SHIFT (0x00000018U)

#define	SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MASK (0x00000001U)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MASK (0x00000002U)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MASK (0x00000004U)

#define	SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MASK (0x00FF0000U)

#define	SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MASK (0x00FF0000U)

#define	SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MASK (0x00000100U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_SHIFT (0x00000008U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MASK (0x00000200U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_SHIFT (0x00000009U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MASK (0x00000400U)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_SHIFT (0x0000000AU)

#define	SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MASK (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MAX (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MASK (0x00000400U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_SHIFT (0x0000000AU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MASK (0x00000800U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_SHIFT (0x0000000BU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MASK (0x00001000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_SHIFT (0x0000000CU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MASK (0x00002000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_SHIFT (0x0000000DU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MASK (0x00004000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_SHIFT (0x0000000EU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MASK (0x00008000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_SHIFT (0x0000000FU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MASK (0x000F0000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MAX (0x0000000FU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MASK (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MAX (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MASK (0x00000400U)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_SHIFT (0x0000000AU)

#define	SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MAX (0x00000001U)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MASK (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MAX (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MASK (0x03FF0000U)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MAX (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MASK (0x000003FFU)

#define	SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MAX (0x000003FFU)

#define	SDL_VTM_CFG1_PID_Y_MINOR_MASK (0x0000003FU)

#define	SDL_VTM_CFG1_PID_Y_MINOR_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_PID_Y_MINOR_MAX (0x0000003FU)

#define	SDL_VTM_CFG1_PID_CUSTOM_MASK (0x000000C0U)

#define	SDL_VTM_CFG1_PID_CUSTOM_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_PID_CUSTOM_MAX (0x00000003U)

#define	SDL_VTM_CFG1_PID_X_MAJOR_MASK (0x00000700U)

#define	SDL_VTM_CFG1_PID_X_MAJOR_SHIFT (0x00000008U)

#define	SDL_VTM_CFG1_PID_X_MAJOR_MAX (0x00000007U)

#define	SDL_VTM_CFG1_PID_R_RTL_MASK (0x0000F800U)

#define	SDL_VTM_CFG1_PID_R_RTL_SHIFT (0x0000000BU)

#define	SDL_VTM_CFG1_PID_R_RTL_MAX (0x0000001FU)

#define	SDL_VTM_CFG1_PID_FUNC_MASK (0x0FFF0000U)

#define	SDL_VTM_CFG1_PID_FUNC_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_PID_FUNC_MAX (0x00000FFFU)

#define	SDL_VTM_CFG1_PID_BU_MASK (0x30000000U)

#define	SDL_VTM_CFG1_PID_BU_SHIFT (0x0000001CU)

#define	SDL_VTM_CFG1_PID_BU_MAX (0x00000003U)

#define	SDL_VTM_CFG1_PID_SCHEME_MASK (0xC0000000U)

#define	SDL_VTM_CFG1_PID_SCHEME_SHIFT (0x0000001EU)

#define	SDL_VTM_CFG1_PID_SCHEME_MAX (0x00000003U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MASK (0x0000000FU)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MAX (0x0000000FU)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MASK (0x000000F0U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MAX (0x0000000FU)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MASK (0x00001000U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_SHIFT (0x0000000CU)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MAX (0x00000001U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MASK (0x000F0000U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_SHIFT (0x00000010U)

#define	SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MAX (0x0000000FU)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

#define	SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

#define	SDL_VTM_CFG2_CLK_CTRL (0x00000008U)

#define	SDL_VTM_CFG2_MISC_CTRL (0x0000000CU)

#define	SDL_VTM_CFG2_MISC_CTRL2 (0x00000010U)

#define	SDL_VTM_CFG2_SAMPLE_CTRL (0x00000020U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL(TMPSENS) (0x00000300U+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG2_TMPSENS_TRIM(TMPSENS) (0x00000304U+((TMPSENS)*0x20U))

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MASK (0x00000010U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CONT_SHIFT (0x00000004U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MAX (0x00000001U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MASK (0x00000020U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_SOC_SHIFT (0x00000005U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MAX (0x00000001U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MASK (0x00000040U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_SHIFT (0x00000006U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MAX (0x00000001U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MASK (0x00000800U)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_SHIFT (0x0000000BU)

#define	SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MAX (0x00000001U)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MASK (0x0000001FU)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_SHIFT (0x00000000U)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MAX (0x0000001FU)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MASK (0x00003F00U)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_SHIFT (0x00000008U)

#define	SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MAX (0x0000003FU)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MASK (0x80000000U)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_SHIFT (0x0000001FU)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MAX (0x00000001U)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MASK (0x0000001FU)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_SHIFT (0x00000000U)

#define	SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MAX (0x0000001FU)

#define	SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MASK (0x00000001U)

#define	SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_SHIFT (0x00000000U)

#define	SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MAX (0x00000001U)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MASK (0x03FF0000U)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_SHIFT (0x00000010U)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MAX (0x000003FFU)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MASK (0x000003FFU)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_SHIFT (0x00000000U)

#define	SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MAX (0x000003FFU)

#define	SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MASK (0x0000FFFFU)

#define	SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_SHIFT (0x00000000U)

#define	SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MAX (0x0000FFFFU)

Macro Definition Documentation

◆ SDL_VTM_TS_MAX_NUM

#define SDL_VTM_TS_MAX_NUM (8U)

◆ SDL_VTM_CFG1_PID

#define SDL_VTM_CFG1_PID (0x00000000U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0

#define SDL_VTM_CFG1_DEVINFO_PWR0 (0x00000004U)

◆ SDL_VTM_CFG1_VD_DEVINFO

#define SDL_VTM_CFG1_VD_DEVINFO ( VTM_VD ) (0x00000100U+((VTM_VD)*0x20U))

◆ SDL_VTM_CFG1_VD_OPPVID

#define SDL_VTM_CFG1_VD_OPPVID ( VTM_VD ) (0x00000104U+((VTM_VD)*0x20U))

◆ SDL_VTM_CFG1_VD_EVT_STAT

#define SDL_VTM_CFG1_VD_EVT_STAT ( VTM_VD ) (0x00000108U+((VTM_VD)*0x20U))

◆ SDL_VTM_CFG1_VD_EVT_SET

#define SDL_VTM_CFG1_VD_EVT_SET ( VTM_VD ) (0x0000010CU+((VTM_VD)*0x20U))

◆ SDL_VTM_CFG1_VD_EVT_CLR

#define SDL_VTM_CFG1_VD_EVT_CLR ( VTM_VD ) (0x00000110U+((VTM_VD)*0x20U))

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET (0x00000204U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR (0x00000208U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET (0x00000214U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR (0x00000218U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET (0x00000224U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR (0x00000228U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET (0x00000234U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR (0x00000238U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET (0x00000244U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR (0x00000248U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET (0x00000254U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR (0x00000258U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL

#define SDL_VTM_CFG1_TMPSENS_CTRL ( TMPSENS ) (0x00000300U+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG1_TMPSENS_STAT

#define SDL_VTM_CFG1_TMPSENS_STAT ( TMPSENS ) (0x00000308U+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG1_TMPSENS_TH

#define SDL_VTM_CFG1_TMPSENS_TH ( TMPSENS ) (0x0000030CU+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG1_TMPSENS_TH2

#define SDL_VTM_CFG1_TMPSENS_TH2 ( TMPSENS ) (0x00000310U+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG1_DEVINFO_VD_MAP_MASK

#define SDL_VTM_CFG1_DEVINFO_VD_MAP_MASK (0x00000F00U)

◆ SDL_VTM_CFG1_DEVINFO_VD_MAP_SHIFT

#define SDL_VTM_CFG1_DEVINFO_VD_MAP_SHIFT (0x00000008U)

◆ SDL_VTM_CFG1_DEVINFO_VD_MAP_MAX

#define SDL_VTM_CFG1_DEVINFO_VD_MAP_MAX (0x0000000FU)

◆ SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MASK

#define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MASK (0x00001000U)

◆ SDL_VTM_CFG1_DEVINFO_AVS0_SUP_SHIFT

#define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_SHIFT (0x0000000CU)

◆ SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MAX

#define SDL_VTM_CFG1_DEVINFO_AVS0_SUP_MAX (0x00000001U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MASK

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_SHIFT

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MAX

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_0_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MASK

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MASK (0x0000FF00U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_SHIFT

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_SHIFT (0x00000008U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MAX

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_1_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MASK

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MASK (0x00FF0000U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_SHIFT

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MAX

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_2_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MASK

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MASK (0xFF000000U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_SHIFT

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_SHIFT (0x00000018U)

◆ SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MAX

#define SDL_VTM_CFG1_VTM_VD_OPPVID_OPP_3_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MASK

#define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_SHIFT

#define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MAX

#define SDL_VTM_CFG1_OPPVID_OPP_LOW_DFLT_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MASK

#define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MASK (0x0000FF00U)

◆ SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_SHIFT

#define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_SHIFT (0x00000008U)

◆ SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MAX

#define SDL_VTM_CFG1_OPPVID_OPP_NOM_DFLT_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MASK

#define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MASK (0x00FF0000U)

◆ SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_SHIFT

#define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MAX

#define SDL_VTM_CFG1_OPPVID_OPP_ODR_DFLT_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MASK

#define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MASK (0xFF000000U)

◆ SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_SHIFT

#define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_SHIFT (0x00000018U)

◆ SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MAX

#define SDL_VTM_CFG1_OPPVID_OPP_TRB_DFLT_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MASK

#define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MASK (0x00000001U)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_SHIFT

#define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MAX

#define SDL_VTM_CFG1_EVT_STAT_GT_TH1_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MASK

#define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MASK (0x00000002U)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_SHIFT

#define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MAX

#define SDL_VTM_CFG1_EVT_STAT_GT_TH2_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MASK

#define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MASK (0x00000004U)

◆ SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_SHIFT

#define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MAX

#define SDL_VTM_CFG1_EVT_STAT_LT_TH0_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MASK

#define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MASK (0x00FF0000U)

◆ SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_SHIFT

#define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MAX

#define SDL_VTM_CFG1_EVT_SET_TSENS_EVT_SEL_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MASK

#define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MASK (0x00FF0000U)

◆ SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_SHIFT

#define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MAX

#define SDL_VTM_CFG1_EVT_CLR_TSENS_EVT_SEL_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MASK

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MASK (0x00000100U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_SHIFT

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_SHIFT (0x00000008U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MAX

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH1_EN_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MASK

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MASK (0x00000200U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_SHIFT

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_SHIFT (0x00000009U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MAX

#define SDL_VTM_CFG1_TMPSENS_CTRL_GT_TH2_EN_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MASK

#define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MASK (0x00000400U)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_SHIFT

#define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_SHIFT (0x0000000AU)

◆ SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MAX

#define SDL_VTM_CFG1_TMPSENS_CTRL_LT_TH0_EN_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MASK (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_OUT_MAX (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MASK (0x00000400U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_SHIFT (0x0000000AU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_DATA_VALID_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MASK (0x00000800U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_SHIFT (0x0000000BU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_EOC_FC_UPDATE_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MASK (0x00001000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_SHIFT (0x0000000CU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH1_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MASK (0x00002000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_SHIFT (0x0000000DU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_GT_TH2_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MASK (0x00004000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_SHIFT (0x0000000EU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_LT_TH0_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MASK (0x00008000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_SHIFT (0x0000000FU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_MAXT_OUTRG_ALERT_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MASK (0x000F0000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_VD_MAP_MAX (0x0000000FU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MASK (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_DTEMP_MAX (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MASK

#define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MASK (0x00000400U)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_SHIFT

#define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_SHIFT (0x0000000AU)

◆ SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MAX

#define SDL_VTM_CFG1_TMPSENS_STAT_EOCZ_MAX (0x00000001U)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MASK

#define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MASK (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_SHIFT

#define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MAX

#define SDL_VTM_CFG1_TMPSENS_TH_TH0_VAL_MAX (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MASK

#define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MASK (0x03FF0000U)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_SHIFT

#define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MAX

#define SDL_VTM_CFG1_TMPSENS_TH_TH1_VAL_MAX (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MASK

#define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MASK (0x000003FFU)

◆ SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_SHIFT

#define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MAX

#define SDL_VTM_CFG1_TMPSENS_TH2_TH2_VAL_MAX (0x000003FFU)

◆ SDL_VTM_CFG1_PID_Y_MINOR_MASK

#define SDL_VTM_CFG1_PID_Y_MINOR_MASK (0x0000003FU)

◆ SDL_VTM_CFG1_PID_Y_MINOR_SHIFT

#define SDL_VTM_CFG1_PID_Y_MINOR_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_PID_Y_MINOR_MAX

#define SDL_VTM_CFG1_PID_Y_MINOR_MAX (0x0000003FU)

◆ SDL_VTM_CFG1_PID_CUSTOM_MASK

#define SDL_VTM_CFG1_PID_CUSTOM_MASK (0x000000C0U)

◆ SDL_VTM_CFG1_PID_CUSTOM_SHIFT

#define SDL_VTM_CFG1_PID_CUSTOM_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_PID_CUSTOM_MAX

#define SDL_VTM_CFG1_PID_CUSTOM_MAX (0x00000003U)

◆ SDL_VTM_CFG1_PID_X_MAJOR_MASK

#define SDL_VTM_CFG1_PID_X_MAJOR_MASK (0x00000700U)

◆ SDL_VTM_CFG1_PID_X_MAJOR_SHIFT

#define SDL_VTM_CFG1_PID_X_MAJOR_SHIFT (0x00000008U)

◆ SDL_VTM_CFG1_PID_X_MAJOR_MAX

#define SDL_VTM_CFG1_PID_X_MAJOR_MAX (0x00000007U)

◆ SDL_VTM_CFG1_PID_R_RTL_MASK

#define SDL_VTM_CFG1_PID_R_RTL_MASK (0x0000F800U)

◆ SDL_VTM_CFG1_PID_R_RTL_SHIFT

#define SDL_VTM_CFG1_PID_R_RTL_SHIFT (0x0000000BU)

◆ SDL_VTM_CFG1_PID_R_RTL_MAX

#define SDL_VTM_CFG1_PID_R_RTL_MAX (0x0000001FU)

◆ SDL_VTM_CFG1_PID_FUNC_MASK

#define SDL_VTM_CFG1_PID_FUNC_MASK (0x0FFF0000U)

◆ SDL_VTM_CFG1_PID_FUNC_SHIFT

#define SDL_VTM_CFG1_PID_FUNC_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_PID_FUNC_MAX

#define SDL_VTM_CFG1_PID_FUNC_MAX (0x00000FFFU)

◆ SDL_VTM_CFG1_PID_BU_MASK

#define SDL_VTM_CFG1_PID_BU_MASK (0x30000000U)

◆ SDL_VTM_CFG1_PID_BU_SHIFT

#define SDL_VTM_CFG1_PID_BU_SHIFT (0x0000001CU)

◆ SDL_VTM_CFG1_PID_BU_MAX

#define SDL_VTM_CFG1_PID_BU_MAX (0x00000003U)

◆ SDL_VTM_CFG1_PID_SCHEME_MASK

#define SDL_VTM_CFG1_PID_SCHEME_MASK (0xC0000000U)

◆ SDL_VTM_CFG1_PID_SCHEME_SHIFT

#define SDL_VTM_CFG1_PID_SCHEME_SHIFT (0x0000001EU)

◆ SDL_VTM_CFG1_PID_SCHEME_MAX

#define SDL_VTM_CFG1_PID_SCHEME_MAX (0x00000003U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MASK

#define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MASK (0x0000000FU)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_SHIFT

#define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MAX

#define SDL_VTM_CFG1_DEVINFO_PWR0_CVD_CT_MAX (0x0000000FU)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MASK

#define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MASK (0x000000F0U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_SHIFT

#define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MAX

#define SDL_VTM_CFG1_DEVINFO_PWR0_TMPSENS_CT_MAX (0x0000000FU)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MASK

#define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MASK (0x00001000U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_SHIFT

#define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_SHIFT (0x0000000CU)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MAX

#define SDL_VTM_CFG1_DEVINFO_PWR0_VDD_RTC_MAX (0x00000001U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MASK

#define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MASK (0x000F0000U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_SHIFT

#define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_SHIFT (0x00000010U)

◆ SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MAX

#define SDL_VTM_CFG1_DEVINFO_PWR0_VTM_VD_MAP_MAX (0x0000000FU)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MASK (0x000000FFU)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD_MAX (0x000000FFU)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH1_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_GT_TH2_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_RAW_STAT_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_STAT_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_SET_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MASK (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_SHIFT (0x00000000U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD0_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MASK (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_SHIFT (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD1_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MASK (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_SHIFT (0x00000002U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD2_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MASK (0x00000008U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_SHIFT (0x00000003U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD3_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MASK (0x00000010U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_SHIFT (0x00000004U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD4_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MASK (0x00000020U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_SHIFT (0x00000005U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD5_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MASK (0x00000040U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_SHIFT (0x00000006U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD6_MAX (0x00000001U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MASK

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MASK (0x00000080U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_SHIFT

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_SHIFT (0x00000007U)

◆ SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MAX

#define SDL_VTM_CFG1_LT_TH0_INT_EN_CLR_INT_VD7_MAX (0x00000001U)

◆ SDL_VTM_CFG2_CLK_CTRL

#define SDL_VTM_CFG2_CLK_CTRL (0x00000008U)

◆ SDL_VTM_CFG2_MISC_CTRL

#define SDL_VTM_CFG2_MISC_CTRL (0x0000000CU)

◆ SDL_VTM_CFG2_MISC_CTRL2

#define SDL_VTM_CFG2_MISC_CTRL2 (0x00000010U)

◆ SDL_VTM_CFG2_SAMPLE_CTRL

#define SDL_VTM_CFG2_SAMPLE_CTRL (0x00000020U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL

#define SDL_VTM_CFG2_TMPSENS_CTRL ( TMPSENS ) (0x00000300U+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG2_TMPSENS_TRIM

#define SDL_VTM_CFG2_TMPSENS_TRIM ( TMPSENS ) (0x00000304U+((TMPSENS)*0x20U))

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MASK

#define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MASK (0x00000010U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CONT_SHIFT

#define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_SHIFT (0x00000004U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MAX

#define SDL_VTM_CFG2_TMPSENS_CTRL_CONT_MAX (0x00000001U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MASK

#define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MASK (0x00000020U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_SOC_SHIFT

#define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_SHIFT (0x00000005U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MAX

#define SDL_VTM_CFG2_TMPSENS_CTRL_SOC_MAX (0x00000001U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MASK

#define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MASK (0x00000040U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_SHIFT

#define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_SHIFT (0x00000006U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MAX

#define SDL_VTM_CFG2_TMPSENS_CTRL_CLRZ_MAX (0x00000001U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MASK

#define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MASK (0x00000800U)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_SHIFT

#define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_SHIFT (0x0000000BU)

◆ SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MAX

#define SDL_VTM_CFG2_TMPSENS_CTRL_MAXT_OUTRG_EN_MAX (0x00000001U)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MASK

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MASK (0x0000001FU)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_SHIFT

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_SHIFT (0x00000000U)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MAX

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMG_MAX (0x0000001FU)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MASK

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MASK (0x00003F00U)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_SHIFT

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_SHIFT (0x00000008U)

◆ SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MAX

#define SDL_VTM_CFG2_TMPSENS_TRIM_TRIMO_MAX (0x0000003FU)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MASK

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MASK (0x80000000U)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_SHIFT

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_SHIFT (0x0000001FU)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MAX

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_SEL_MAX (0x00000001U)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MASK

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MASK (0x0000001FU)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_SHIFT

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_SHIFT (0x00000000U)

◆ SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MAX

#define SDL_VTM_CFG2_CLK_CTRL_TSENS_CLK_DIV_MAX (0x0000001FU)

◆ SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MASK

#define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MASK (0x00000001U)

◆ SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_SHIFT

#define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_SHIFT (0x00000000U)

◆ SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MAX

#define SDL_VTM_CFG2_MISC_CTRL_ANY_MAXT_OUTRG_ALERT_EN_MAX (0x00000001U)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MASK

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MASK (0x03FF0000U)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_SHIFT

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_SHIFT (0x00000010U)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MAX

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR0_MAX (0x000003FFU)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MASK

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MASK (0x000003FFU)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_SHIFT

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_SHIFT (0x00000000U)

◆ SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MAX

#define SDL_VTM_CFG2_MISC_CTRL2_MAXT_OUTRG_ALERT_THR_MAX (0x000003FFU)

◆ SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MASK

#define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MASK (0x0000FFFFU)

◆ SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_SHIFT

#define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_SHIFT (0x00000000U)

◆ SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MAX

#define SDL_VTM_CFG2_SAMPLE_CTRL_SAMPLE_PER_CNT_MAX (0x0000FFFFU)

Data Structures

Macros