Introduction

DMSC controls the power management, security and resource management of the device.

Macros
#define	TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_THREAD_ID (0U)
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#define	TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_NUM_MESSAGES (11U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID (1U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_THREAD_ID (2U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_NUM_MESSAGES (11U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID (3U)

#define	TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

#define	TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_THREAD_ID (4U)

#define	TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_NUM_MESSAGES (1U)

#define	TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_THREAD_ID (5U)

#define	TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (1U)

#define	TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_THREAD_ID (6U)

#define	TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_NUM_MESSAGES (1U)

#define	TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_THREAD_ID (7U)

#define	TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (1U)

#define	TISCI_SEC_PROXY_A53_0_READ_RESPONSE_THREAD_ID (8U)

#define	TISCI_SEC_PROXY_A53_0_READ_RESPONSE_NUM_MESSAGES (11U)

#define	TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_THREAD_ID (9U)

#define	TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

#define	TISCI_SEC_PROXY_A53_1_READ_RESPONSE_THREAD_ID (10U)

#define	TISCI_SEC_PROXY_A53_1_READ_RESPONSE_NUM_MESSAGES (11U)

#define	TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_THREAD_ID (11U)

#define	TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

#define	TISCI_SEC_PROXY_A53_2_READ_RESPONSE_THREAD_ID (12U)

#define	TISCI_SEC_PROXY_A53_2_READ_RESPONSE_NUM_MESSAGES (6U)

#define	TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_THREAD_ID (13U)

#define	TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

#define	TISCI_SEC_PROXY_A53_3_READ_RESPONSE_THREAD_ID (14U)

#define	TISCI_SEC_PROXY_A53_3_READ_RESPONSE_NUM_MESSAGES (6U)

#define	TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_THREAD_ID (15U)

#define	TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

#define	TISCI_SEC_PROXY_A53_4_READ_RESPONSE_THREAD_ID (16U)

#define	TISCI_SEC_PROXY_A53_4_READ_RESPONSE_NUM_MESSAGES (6U)

#define	TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_THREAD_ID (17U)

#define	TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

#define	TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_THREAD_ID (18U)

#define	TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_NUM_MESSAGES (6U)

#define	TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID (19U)

#define	TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

#define	TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_THREAD_ID (20U)

#define	TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_NUM_MESSAGES (4U)

#define	TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_THREAD_ID (21U)

#define	TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_NUM_MESSAGES (4U)

#define	TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_THREAD_ID (22U)

#define	TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_NUM_MESSAGES (4U)

#define	TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_THREAD_ID (23U)

#define	TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_NUM_MESSAGES (2U)

#define	TISCI_SEC_PROXY_HSM_READ_RESPONSE_THREAD_ID (0U)

#define	TISCI_SEC_PROXY_HSM_READ_RESPONSE_NUM_MESSAGES (8U)

#define	TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_THREAD_ID (1U)

#define	TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_NUM_MESSAGES (8U)

Macro Definition Documentation

◆ TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_THREAD_ID (0U)

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

System Firmware Source File

Secure Proxy indices for AM62PX device

Data version: 240826_164236 Thread ID macro for WKUP_0_R5_0 response

◆ TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_WKUP_0_R5_0_READ_RESPONSE_NUM_MESSAGES (11U)

Num messages macro for WKUP_0_R5_0 response

◆ TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID (1U)

Thread ID macro for WKUP_0_R5_0 low_priority

◆ TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_WKUP_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

Num messages macro for WKUP_0_R5_0 low_priority

◆ TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_THREAD_ID (2U)

Thread ID macro for WKUP_0_R5_1 response

◆ TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_WKUP_0_R5_1_READ_RESPONSE_NUM_MESSAGES (11U)

Num messages macro for WKUP_0_R5_1 response

◆ TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_THREAD_ID (3U)

Thread ID macro for WKUP_0_R5_1 low_priority

◆ TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_WKUP_0_R5_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

Num messages macro for WKUP_0_R5_1 low_priority

◆ TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_THREAD_ID (4U)

Thread ID macro for GPU_0 response

◆ TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_GPU_0_READ_RESPONSE_NUM_MESSAGES (1U)

Num messages macro for GPU_0 response

◆ TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_THREAD_ID (5U)

Thread ID macro for GPU_0 low_priority

◆ TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_GPU_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (1U)

Num messages macro for GPU_0 low_priority

◆ TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_THREAD_ID (6U)

Thread ID macro for GPU_1 response

◆ TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_GPU_1_READ_RESPONSE_NUM_MESSAGES (1U)

Num messages macro for GPU_1 response

◆ TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_THREAD_ID (7U)

Thread ID macro for GPU_1 low_priority

◆ TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_GPU_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (1U)

Num messages macro for GPU_1 low_priority

◆ TISCI_SEC_PROXY_A53_0_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_A53_0_READ_RESPONSE_THREAD_ID (8U)

Thread ID macro for A53_0 response

◆ TISCI_SEC_PROXY_A53_0_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_0_READ_RESPONSE_NUM_MESSAGES (11U)

Num messages macro for A53_0 response

◆ TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_THREAD_ID (9U)

Thread ID macro for A53_0 low_priority

◆ TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

Num messages macro for A53_0 low_priority

◆ TISCI_SEC_PROXY_A53_1_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_A53_1_READ_RESPONSE_THREAD_ID (10U)

Thread ID macro for A53_1 response

◆ TISCI_SEC_PROXY_A53_1_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_1_READ_RESPONSE_NUM_MESSAGES (11U)

Num messages macro for A53_1 response

◆ TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_THREAD_ID (11U)

Thread ID macro for A53_1 low_priority

◆ TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_1_WRITE_LOW_PRIORITY_NUM_MESSAGES (10U)

Num messages macro for A53_1 low_priority

◆ TISCI_SEC_PROXY_A53_2_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_A53_2_READ_RESPONSE_THREAD_ID (12U)

Thread ID macro for A53_2 response

◆ TISCI_SEC_PROXY_A53_2_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_2_READ_RESPONSE_NUM_MESSAGES (6U)

Num messages macro for A53_2 response

◆ TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_THREAD_ID (13U)

Thread ID macro for A53_2 low_priority

◆ TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_2_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

Num messages macro for A53_2 low_priority

◆ TISCI_SEC_PROXY_A53_3_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_A53_3_READ_RESPONSE_THREAD_ID (14U)

Thread ID macro for A53_3 response

◆ TISCI_SEC_PROXY_A53_3_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_3_READ_RESPONSE_NUM_MESSAGES (6U)

Num messages macro for A53_3 response

◆ TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_THREAD_ID (15U)

Thread ID macro for A53_3 low_priority

◆ TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_3_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

Num messages macro for A53_3 low_priority

◆ TISCI_SEC_PROXY_A53_4_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_A53_4_READ_RESPONSE_THREAD_ID (16U)

Thread ID macro for A53_4 response

◆ TISCI_SEC_PROXY_A53_4_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_4_READ_RESPONSE_NUM_MESSAGES (6U)

Num messages macro for A53_4 response

◆ TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_THREAD_ID (17U)

Thread ID macro for A53_4 low_priority

◆ TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_A53_4_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

Num messages macro for A53_4 low_priority

◆ TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_THREAD_ID (18U)

Thread ID macro for MCU_0_R5_0 response

◆ TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_MCU_0_R5_0_READ_RESPONSE_NUM_MESSAGES (6U)

Num messages macro for MCU_0_R5_0 response

◆ TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_THREAD_ID (19U)

Thread ID macro for MCU_0_R5_0 low_priority

◆ TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_MCU_0_R5_0_WRITE_LOW_PRIORITY_NUM_MESSAGES (5U)

Num messages macro for MCU_0_R5_0 low_priority

◆ TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_THREAD_ID (20U)

Thread ID macro for DM2TIFS response

◆ TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_DM2TIFS_READ_RESPONSE_NUM_MESSAGES (4U)

Num messages macro for DM2TIFS response

◆ TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_THREAD_ID (21U)

Thread ID macro for DM2TIFS low_priority

◆ TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_DM2TIFS_WRITE_LOW_PRIORITY_NUM_MESSAGES (4U)

Num messages macro for DM2TIFS low_priority

◆ TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_THREAD_ID (22U)

Thread ID macro for TIFS2DM response

◆ TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_TIFS2DM_READ_RESPONSE_NUM_MESSAGES (4U)

Num messages macro for TIFS2DM response

◆ TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_THREAD_ID (23U)

Thread ID macro for TIFS2DM low_priority

◆ TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_TIFS2DM_WRITE_LOW_PRIORITY_NUM_MESSAGES (2U)

Num messages macro for TIFS2DM low_priority

◆ TISCI_SEC_PROXY_HSM_READ_RESPONSE_THREAD_ID

#define TISCI_SEC_PROXY_HSM_READ_RESPONSE_THREAD_ID (0U)

Thread ID macro for HSM response

◆ TISCI_SEC_PROXY_HSM_READ_RESPONSE_NUM_MESSAGES

#define TISCI_SEC_PROXY_HSM_READ_RESPONSE_NUM_MESSAGES (8U)

Num messages macro for HSM response

◆ TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_THREAD_ID

#define TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_THREAD_ID (1U)

Thread ID macro for HSM low_priority

◆ TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_NUM_MESSAGES

#define TISCI_SEC_PROXY_HSM_WRITE_LOW_PRIORITY_NUM_MESSAGES (8U)

Num messages macro for HSM low_priority