Data Structures
struct	SDL_ecc_aggrRegs

Macros
#define	SDL_ECC_AGGR_REV (0x00000000U)

#define	SDL_ECC_AGGR_VECTOR (0x00000008U)

#define	SDL_ECC_AGGR_STAT (0x0000000CU)

#define	SDL_ECC_AGGR_RESERVED_SVBUS(RESERVED_SVBUS) (0x00000010U+((RESERVED_SVBUS)*0x4U))

#define	SDL_ECC_AGGR_SEC_EOI_REG (0x0000003CU)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0 (0x00000040U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0 (0x00000080U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0 (0x000000C0U)

#define	SDL_ECC_AGGR_DED_EOI_REG (0x0000013CU)

#define	SDL_ECC_AGGR_DED_STATUS_REG0 (0x00000140U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0 (0x00000180U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0 (0x000001C0U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET (0x00000200U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR (0x00000204U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET (0x00000208U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR (0x0000020CU)

#define	SDL_ECC_AGGR_REV_SCHEME_MASK (0xC0000000U)

#define	SDL_ECC_AGGR_REV_SCHEME_SHIFT (0x0000001EU)

#define	SDL_ECC_AGGR_REV_SCHEME_MAX (0x00000003U)

#define	SDL_ECC_AGGR_REV_BU_MASK (0x30000000U)

#define	SDL_ECC_AGGR_REV_BU_SHIFT (0x0000001CU)

#define	SDL_ECC_AGGR_REV_BU_MAX (0x00000003U)

#define	SDL_ECC_AGGR_REV_MODULE_ID_MASK (0x0FFF0000U)

#define	SDL_ECC_AGGR_REV_MODULE_ID_SHIFT (0x00000010U)

#define	SDL_ECC_AGGR_REV_MODULE_ID_MAX (0x00000FFFU)

#define	SDL_ECC_AGGR_REV_REVRTL_MASK (0x0000F800U)

#define	SDL_ECC_AGGR_REV_REVRTL_SHIFT (0x0000000BU)

#define	SDL_ECC_AGGR_REV_REVRTL_MAX (0x0000001FU)

#define	SDL_ECC_AGGR_REV_REVMAJ_MASK (0x00000700U)

#define	SDL_ECC_AGGR_REV_REVMAJ_SHIFT (0x00000008U)

#define	SDL_ECC_AGGR_REV_REVMAJ_MAX (0x00000007U)

#define	SDL_ECC_AGGR_REV_CUSTOM_MASK (0x000000C0U)

#define	SDL_ECC_AGGR_REV_CUSTOM_SHIFT (0x00000006U)

#define	SDL_ECC_AGGR_REV_CUSTOM_MAX (0x00000003U)

#define	SDL_ECC_AGGR_REV_REVMIN_MASK (0x0000003FU)

#define	SDL_ECC_AGGR_REV_REVMIN_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_REV_REVMIN_MAX (0x0000003FU)

#define	SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK (0x000007FFU)

#define	SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX (0x000007FFU)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (0x0000000FU)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX (0x00000001U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00FF0000U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (0x00000010U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX (0x000000FFU)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (0x00000018U)

#define	SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX (0x00000001U)

#define	SDL_ECC_AGGR_STAT_NUM_RAMS_MASK (0x000007FFU)

#define	SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_STAT_NUM_RAMS_MAX (0x000007FFU)

#define	SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK (0xFFFFFFFFU)

#define	SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX (0xFFFFFFFFU)

#define	SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK (0x00000001U)

#define	SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK (0x00000001U)

#define	SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK (0x00000002U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK (0x00000002U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX (0x00000001U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK (0x00000003U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX (0x00000003U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK (0x0000000CU)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX (0x00000003U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK (0x00000003U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT (0x00000000U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX (0x00000003U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK (0x0000000CU)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT (0x00000002U)

#define	SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX (0x00000003U)

Macro Definition Documentation

◆ SDL_ECC_AGGR_REV

#define SDL_ECC_AGGR_REV (0x00000000U)

◆ SDL_ECC_AGGR_VECTOR

#define SDL_ECC_AGGR_VECTOR (0x00000008U)

◆ SDL_ECC_AGGR_STAT

#define SDL_ECC_AGGR_STAT (0x0000000CU)

◆ SDL_ECC_AGGR_RESERVED_SVBUS

#define SDL_ECC_AGGR_RESERVED_SVBUS ( RESERVED_SVBUS ) (0x00000010U+((RESERVED_SVBUS)*0x4U))

◆ SDL_ECC_AGGR_SEC_EOI_REG

#define SDL_ECC_AGGR_SEC_EOI_REG (0x0000003CU)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0

#define SDL_ECC_AGGR_SEC_STATUS_REG0 (0x00000040U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0 (0x00000080U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0 (0x000000C0U)

◆ SDL_ECC_AGGR_DED_EOI_REG

#define SDL_ECC_AGGR_DED_EOI_REG (0x0000013CU)

◆ SDL_ECC_AGGR_DED_STATUS_REG0

#define SDL_ECC_AGGR_DED_STATUS_REG0 (0x00000140U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0 (0x00000180U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0 (0x000001C0U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET

#define SDL_ECC_AGGR_AGGR_ENABLE_SET (0x00000200U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR (0x00000204U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET

#define SDL_ECC_AGGR_AGGR_STATUS_SET (0x00000208U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR

#define SDL_ECC_AGGR_AGGR_STATUS_CLR (0x0000020CU)

◆ SDL_ECC_AGGR_REV_SCHEME_MASK

#define SDL_ECC_AGGR_REV_SCHEME_MASK (0xC0000000U)

◆ SDL_ECC_AGGR_REV_SCHEME_SHIFT

#define SDL_ECC_AGGR_REV_SCHEME_SHIFT (0x0000001EU)

◆ SDL_ECC_AGGR_REV_SCHEME_MAX

#define SDL_ECC_AGGR_REV_SCHEME_MAX (0x00000003U)

◆ SDL_ECC_AGGR_REV_BU_MASK

#define SDL_ECC_AGGR_REV_BU_MASK (0x30000000U)

◆ SDL_ECC_AGGR_REV_BU_SHIFT

#define SDL_ECC_AGGR_REV_BU_SHIFT (0x0000001CU)

◆ SDL_ECC_AGGR_REV_BU_MAX

#define SDL_ECC_AGGR_REV_BU_MAX (0x00000003U)

◆ SDL_ECC_AGGR_REV_MODULE_ID_MASK

#define SDL_ECC_AGGR_REV_MODULE_ID_MASK (0x0FFF0000U)

◆ SDL_ECC_AGGR_REV_MODULE_ID_SHIFT

#define SDL_ECC_AGGR_REV_MODULE_ID_SHIFT (0x00000010U)

◆ SDL_ECC_AGGR_REV_MODULE_ID_MAX

#define SDL_ECC_AGGR_REV_MODULE_ID_MAX (0x00000FFFU)

◆ SDL_ECC_AGGR_REV_REVRTL_MASK

#define SDL_ECC_AGGR_REV_REVRTL_MASK (0x0000F800U)

◆ SDL_ECC_AGGR_REV_REVRTL_SHIFT

#define SDL_ECC_AGGR_REV_REVRTL_SHIFT (0x0000000BU)

◆ SDL_ECC_AGGR_REV_REVRTL_MAX

#define SDL_ECC_AGGR_REV_REVRTL_MAX (0x0000001FU)

◆ SDL_ECC_AGGR_REV_REVMAJ_MASK

#define SDL_ECC_AGGR_REV_REVMAJ_MASK (0x00000700U)

◆ SDL_ECC_AGGR_REV_REVMAJ_SHIFT

#define SDL_ECC_AGGR_REV_REVMAJ_SHIFT (0x00000008U)

◆ SDL_ECC_AGGR_REV_REVMAJ_MAX

#define SDL_ECC_AGGR_REV_REVMAJ_MAX (0x00000007U)

◆ SDL_ECC_AGGR_REV_CUSTOM_MASK

#define SDL_ECC_AGGR_REV_CUSTOM_MASK (0x000000C0U)

◆ SDL_ECC_AGGR_REV_CUSTOM_SHIFT

#define SDL_ECC_AGGR_REV_CUSTOM_SHIFT (0x00000006U)

◆ SDL_ECC_AGGR_REV_CUSTOM_MAX

#define SDL_ECC_AGGR_REV_CUSTOM_MAX (0x00000003U)

◆ SDL_ECC_AGGR_REV_REVMIN_MASK

#define SDL_ECC_AGGR_REV_REVMIN_MASK (0x0000003FU)

◆ SDL_ECC_AGGR_REV_REVMIN_SHIFT

#define SDL_ECC_AGGR_REV_REVMIN_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_REV_REVMIN_MAX

#define SDL_ECC_AGGR_REV_REVMIN_MAX (0x0000003FU)

◆ SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK

#define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK (0x000007FFU)

◆ SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT

#define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX

#define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX (0x000007FFU)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (0x0000000FU)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX (0x00000001U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00FF0000U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (0x00000010U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX (0x000000FFU)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (0x00000018U)

◆ SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX

#define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX (0x00000001U)

◆ SDL_ECC_AGGR_STAT_NUM_RAMS_MASK

#define SDL_ECC_AGGR_STAT_NUM_RAMS_MASK (0x000007FFU)

◆ SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT

#define SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_STAT_NUM_RAMS_MAX

#define SDL_ECC_AGGR_STAT_NUM_RAMS_MAX (0x000007FFU)

◆ SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK

#define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK (0xFFFFFFFFU)

◆ SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT

#define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX

#define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX (0xFFFFFFFFU)

◆ SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK

#define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK (0x00000001U)

◆ SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT

#define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX

#define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX

#define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK

#define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK (0x00000001U)

◆ SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT

#define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX

#define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX

#define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX

#define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX

#define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK (0x00000002U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX

#define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK (0x00000002U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX

#define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX (0x00000001U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK

#define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK (0x00000003U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT

#define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX

#define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX (0x00000003U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK

#define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK (0x0000000CU)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT

#define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX

#define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX (0x00000003U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK (0x00000003U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT (0x00000000U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX (0x00000003U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK (0x0000000CU)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT (0x00000002U)

◆ SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX

#define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX (0x00000003U)

Data Structures

Macros