The most recent Keywriter package available (otp_keywriter_am62px_11_01_00) is based on the MCU+ SDK version 11.01.00 and it is available on the 'Secure resources' portal of ti.com.
| ID | Head Line | Module |
| <a href= | Invalid comment in the linker command files | Build |
| <a href= | Debug unlock certificate generation script does not generate DER certificate blob | Build |
| <a href= | LPDDR: DDR PLL reset code issue | DDR |
| <a href= | DebugP_assert: change so that it does not lock up the entire core | DPL |
| <a href= | ClockP_usleep() getting into infinite loop due to timer wraparound | DPL |
| <a href= | OLDI Single Link Common Mode VOCM Voltage Drop with MCU+SDK | Display |
| <a href= | Wrong comments on HwiP_inISR() API | Documentation |
| <a href= | SysConfig does not generate correct FLASH section parameters. | Flash |
| <a href= | I2C Target Overrun Test Hangs Waiting for Callback | I2C |
| <a href= | I2c_transfer not returning correct status when transfer mode is set to polling | I2C |
| <a href= | I2C_transfer() return not handled properly while i2cLldHandle is NULL | I2C |
| <a href= | SysConfig does not support configuring both 10-bit own addresses for I2C target mode | I2C |
| <a href= | NACK is not returned to application when performing i2c write in polling mode | I2C |
| <a href= | I2C target mode with multiple own addresses transaction fails | I2C |
| <a href= | Linux Kernel IPC Examples are broken | IPC |
| <a href= | DMA channel teardown sequence is not proper in MCASP_disableDmaTx | MCASP |
| <a href= | [MCSPI]End of Channel Transfer status check is missing for DMA mode | MCSPI |
| <a href= | [MCSPI] Timeout mechanism missing to prevent Infinite loops in MCSPI driver | MCSPI |
| <a href= | PDMA channels are not aligned properly with the different MCSPI instants | MCSPI |
| <a href= | eMMC Init Code Missing DLL Register Settings needed for Initial Legacy SDR Mode Phase | MMCSD |
| <a href= | eMMC PHY I/O Calibration not getting executed during eMMC boot | MMCSD |
| <a href= | SDR/DDR mode are not enabled in the Sysconfig for MMCSD | MMCSD |
| <a href= | MMCSD driver does not follow the SWITCH command sequence correctly | MMCSD |
| <a href= | EXTCSD HS_TIMING register is set incorrectly at certain places in the driver | MMCSD |
| <a href= | MMCSD driver uses infinite loop instead of timeout for checking fields of PRESENTSTATE register | MMCSD |
| <a href= | Timing issues with MMCSD host controller driver | MMCSD |
| <a href= | Incorrect handling of the CAPABILITIES register in the eMMC initialization | MMCSD |
| <a href= | Random CRC errors observed for eMMC HS400 mode on random reset test | MMCSD |
| <a href= | Comment and Implementation does not match in the MMCSD_retune | MMCSD |
| <a href= | eMMC Driver Error Interrupt Flags accessed in Wrong Register | MMCSD |
| <a href= | eMMC Init Code ignores early failures and continues Execution | MMCSD |
| <a href= | eMMC Driver Error Recovery Recursion can lead to System Crashes | MMCSD |
| <a href= | MMCSD : Read fails when injecting Command time out fault | MMCSD |
| <a href= | MMCSD : Read fails when injecting Command Index fault | MMCSD |
| <a href= | MMCSD : Read times out in HS200 mode after writing in SDR50 mode | MMCSD |
| <a href= | MMCSD : Read fails when injecting Command CRC fault | MMCSD |
| <a href= | MMCSD : Read fails when passing invalid argument. | MMCSD |
| <a href= | eMMC PHY Tuning Status Result Ignored when switching to HS400 Mode | MMCSD |
| <a href= | MMCSD close() is not proper | MMCSD |
| <a href= | Simultaneous FAT transfer fails for the same instance while being accessed from two different tasks. | MMCSD |
| <a href= | MMCSD : Write fails when passing invalid argument. | MMCSD |
| <a href= | MMCSD : Read fails when injecting Command End Bit fault | MMCSD |
| <a href= | HSDDR50 mode lead to data CRC errors with correct timing values. | MMCSD |
| <a href= | MMCSD close fails after opening the same instance twice. | MMCSD |
| <a href= | MMCSD Sysconfig provides options to configure PHY type | MMCSD |
| <a href= | MMCSD error recovery sequence isn't implemented correctly | MMCSD |
| <a href= | Missing -p flag with strip command to reduce the size of *.out | Makefiles |
| <a href= | OSPI tuning algorithm finds points in noisy region on rare scenarios | OSPI |
| <a href= | OSPI_flashExecCmd has a couple of checks where the code may get stuck | OSPI |
| <a href= | Configured dummy cycles in flash driver contradicts flash data sheet | OSPI |
| <a href= | OSPI DAC Mode Configuration hardcoded and not based on flashsize | OSPI |
| <a href= | OSPI_PhyTuneGrapher missing read delay value 4 | OSPI |
| <a href= | OSPI Phy Status Check Missing | OSPI |
| <a href= | AM62P: fss flash boot size is locking the MMRs | OSPI |
| <a href= | NOR Flash Fixup missing in SBL NULL | OSPI |
| <a href= | Flash_eraseSector and Flash_norOspiEraseSector does not erases the mentioned sector. | OSPI |
| <a href= | gMemBootloaderConfig in the bootloader driver is not thread safe | SBL |
| <a href= | SBL SD is broken on AM62P | SBL |
| <a href= | Secure board configurations by default allows JTAG unlocking | SBL |
| <a href= | DMA is not enabled for SOC Memory boot media in the SysConfig | SBL |
| <a href= | gAppimage is not allocated to the intended section defined in the linker command files | SBL |
| <a href= | """sbl_uart_uniflash_stage2"" is not prebuilt" | SBL |
| <a href= | FORCE bit not book keeped properly for MCSPI DMA mode of operation | Software |
| <a href= | Improve Sysconfig tool tips for all drivers | SysConfig |
| <a href= | UDMA: HC/UHC channel allocation fails due to RM config mismatch with CSL defines | UDMA |
| <a href= | UDMA multiple channel open for the same channel and invalid instance not handling properly | UDMA |
| <a href= | VTM module sensor reset sequence modification for reliable functionality | SDL |
| <a href= | SDL DCC Seed Value Calculation Deviates from TRM Guidelines | SDL |
| <a href= | PBIST example and tests fail in UART Bootmode | SDL |
| ID | Head Line | Module |
| <a href= | MCU+ SDK LPDDR4 Driver starts DDR Training/Leveling Sequence twice | DDR |
| <a href= | MCU+ SDK Example Projects using incorrect ARMv7 MPU Attributes for Peripheral Register Region | Examples |
| <a href= | Outstanding mailbox messages prevent suspend | IPC |
| <a href= | MMCSD_enableBootPartition implements two mutually exclusive concepts as one function | MMCSD |
| <a href= | MMCSD_read & MMCSD_write function are not designed simple & readable | MMCSD |
| <a href= | MMCSD field Card Type is not ordered logically in the Sysconfig | MMCSD |
| <a href= | Incorrect calculation of rowColEnd in the ext_otp_writeMmr | OTP |
| <a href= | RTC Test application failing intermittently. | RTC |
| <a href= | SBL_SD bootloaders report incorrect boot image size | SBL |
| <a href= | MCU+ SDK CCS Project Build Generates Invalid/Redundant Boot Image Files | Build |
| <a href= | WKUP UART0 is not working in CallBack mode | UART |
| <a href= | eMMC retuning may be attempted during the initialization sequence | MMCSD |
| <a href= | ECC: Firewall related aggregators failures - ECC Aggregators SDL_SMS0_SMS_TIFS_ECC, SDL_SMS0_SMS_HSM_ECC, SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR and SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR fail because of firewall access issues faced by SDL | SDL |
| <a href= | AM62Px: ECC: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR aggregator is failing | SDL |
| <a href= | CSI RX ECC aggregators are failing on AM62P/AM62X | SDL |
| <a href= | Running MCU LBIST on SBL causes JTAG connection issues to MCU R5F | SDL |
This section lists changes which could affect user applications developed using older SDK versions. Read this carefully to see if you need to do any changes in your existing application when migrating to this SDK version relative to previous SDK version. Also refer to older SDK version release notes to see changes in earlier SDKs.
The below table captures the list of migration document sections when migrating from one version to another. The migration for a partcluar module will be applicable, if you are migrating from older version listed to newer version listed on the table below.
1.12.0