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#define	AM62LX_DEV_ADC0_ADC_CLK 0

#define	AM62LX_DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 1

#define	AM62LX_DEV_ADC0_ADC_CLK_PARENT_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK12 2

#define	AM62LX_DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT8_CLK 3

#define	AM62LX_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 4

#define	AM62LX_DEV_ADC0_SYS_CLK 5

#define	AM62LX_DEV_ADC0_VBUS_CLK 6

#define	AM62LX_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK 7

#define	AM62LX_DEV_TIMESYNC_INTROUTER0_INTR_CLK 8

#define	AM62LX_DEV_CPSW0_CPPI_CLK_CLK 9

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK 10

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 11

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 12

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 13

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_CLK_32K_RC_SEL_OUT0 14

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 15

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 16

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK 17

#define	AM62LX_DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 18

#define	AM62LX_DEV_CPSW0_GMII1_MR_CLK 19

#define	AM62LX_DEV_CPSW0_GMII1_MT_CLK 20

#define	AM62LX_DEV_CPSW0_GMII2_MR_CLK 21

#define	AM62LX_DEV_CPSW0_GMII2_MT_CLK 22

#define	AM62LX_DEV_CPSW0_GMII_RFT_CLK 23

#define	AM62LX_DEV_CPSW0_RGMII_MHZ_250_CLK 24

#define	AM62LX_DEV_CPSW0_RGMII_MHZ_50_CLK 25

#define	AM62LX_DEV_CPSW0_RGMII_MHZ_5_CLK 26

#define	AM62LX_DEV_CPSW0_RMII1_MHZ_50_CLK 27

#define	AM62LX_DEV_CPSW0_RMII2_MHZ_50_CLK 28

#define	AM62LX_DEV_CPSW0_CPTS_GENF0 29

#define	AM62LX_DEV_CPSW0_CPTS_GENF1 30

#define	AM62LX_DEV_CPSW0_MDIO_MDCLK_O 31

#define	AM62LX_DEV_CPT2_AGGR0_VCLK_CLK 32

#define	AM62LX_DEV_CPT2_AGGR1_VCLK_CLK 33

#define	AM62LX_DEV_WKUP_CPT2_AGGR0_VCLK_CLK 34

#define	AM62LX_DEV_STM0_ATB_CLK 35

#define	AM62LX_DEV_STM0_CORE_CLK 36

#define	AM62LX_DEV_STM0_VBUSP_CLK 37

#define	AM62LX_DEV_DEBUGSS_WRAP0_ATB_CLK 38

#define	AM62LX_DEV_DEBUGSS_WRAP0_CORE_CLK 39

#define	AM62LX_DEV_DEBUGSS_WRAP0_JTAG_TCK 40

#define	AM62LX_DEV_DEBUGSS_WRAP0_P1500_WRCK 41

#define	AM62LX_DEV_DEBUGSS_WRAP0_TREXPT_CLK 42

#define	AM62LX_DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK 43

#define	AM62LX_DEV_DMASS0_BCDMA_0_CLK 44

#define	AM62LX_DEV_DMASS0_PKTDMA_0_CLK 45

#define	AM62LX_DEV_TIMER0_TIMER_HCLK_CLK 46

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK 47

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 48

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 49

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 50

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 51

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 52

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 53

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 54

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 55

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 56

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT1_CLK 57

#define	AM62LX_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 58

#define	AM62LX_DEV_TIMER0_TIMER_PWM 59

#define	AM62LX_DEV_TIMER1_TIMER_HCLK_CLK 60

#define	AM62LX_DEV_TIMER1_TIMER_TCLK_CLK 61

#define	AM62LX_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT1 62

#define	AM62LX_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM 63

#define	AM62LX_DEV_TIMER1_TIMER_PWM 64

#define	AM62LX_DEV_TIMER2_TIMER_HCLK_CLK 65

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK 66

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 67

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 68

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 69

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 70

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 71

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 72

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 73

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 74

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 75

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT1_CLK 76

#define	AM62LX_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 77

#define	AM62LX_DEV_TIMER2_TIMER_PWM 78

#define	AM62LX_DEV_TIMER3_TIMER_HCLK_CLK 79

#define	AM62LX_DEV_TIMER3_TIMER_TCLK_CLK 80

#define	AM62LX_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMERCLKN_SEL_OUT3 81

#define	AM62LX_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM 82

#define	AM62LX_DEV_TIMER3_TIMER_PWM 83

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_HCLK_CLK 84

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK 85

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 86

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 87

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 88

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 89

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 90

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CLK_32K_RC_SEL_OUT0 91

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 92

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 93

#define	AM62LX_DEV_WKUP_TIMER0_TIMER_PWM 94

#define	AM62LX_DEV_WKUP_TIMER1_TIMER_HCLK_CLK 95

#define	AM62LX_DEV_WKUP_TIMER1_TIMER_TCLK_CLK 96

#define	AM62LX_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_WKUP_TIMERCLKN_SEL_OUT1 97

#define	AM62LX_DEV_WKUP_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_WKUP_0_TIMER_PWM 98

#define	AM62LX_DEV_ECAP0_VBUS_CLK 99

#define	AM62LX_DEV_ECAP1_VBUS_CLK 100

#define	AM62LX_DEV_ECAP2_VBUS_CLK 101

#define	AM62LX_DEV_ELM0_VBUSP_CLK 102

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_IO_CLK_I 103

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT 104

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLK_OUT 105

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_VBUS_CLK 106

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_XIN_CLK 107

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 108

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT9_CLK 109

#define	AM62LX_DEV_MMCSD1_EMMCSDSS_IO_CLK_O 110

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_IO_CLK_I 111

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLKLB_OUT 112

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC2_CLK_OUT 113

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_VBUS_CLK 114

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_XIN_CLK 115

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 116

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT9_CLK 117

#define	AM62LX_DEV_MMCSD2_EMMCSDSS_IO_CLK_O 118

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_IO_CLK_I 119

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLKLB_OUT 120

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC0_CLK_OUT 121

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_VBUS_CLK 122

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_XIN_CLK 123

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK 124

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT9_CLK 125

#define	AM62LX_DEV_MMCSD0_EMMCSDSS_IO_CLK_O 126

#define	AM62LX_DEV_EQEP0_VBUS_CLK 127

#define	AM62LX_DEV_EQEP1_VBUS_CLK 128

#define	AM62LX_DEV_EQEP2_VBUS_CLK 129

#define	AM62LX_DEV_FSS0_OSPI0_DQS_CLK 130

#define	AM62LX_DEV_FSS0_OSPI0_ICLK_CLK 131

#define	AM62LX_DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT 132

#define	AM62LX_DEV_FSS0_OSPI0_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT 133

#define	AM62LX_DEV_FSS0_OSPI0_RCLK_CLK 134

#define	AM62LX_DEV_FSS0_OSPI0_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK 135

#define	AM62LX_DEV_FSS0_OSPI0_RCLK_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT4_CLK 136

#define	AM62LX_DEV_FSS0_VBUS_CLK 137

#define	AM62LX_DEV_FSS0_OSPI0_OCLK_CLK 138

#define	AM62LX_DEV_GICSS0_VCLK_CLK 139

#define	AM62LX_DEV_GPIO0_MMR_CLK 140

#define	AM62LX_DEV_GPIO2_MMR_CLK 141

#define	AM62LX_DEV_WKUP_GPIO0_MMR_CLK 142

#define	AM62LX_DEV_WKUP_GPIO0_MMR_CLK_PARENT_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK4 143

#define	AM62LX_DEV_WKUP_GPIO0_MMR_CLK_PARENT_RTCSS_WKUP_0_OSC_32K_CLK 144

#define	AM62LX_DEV_WKUP_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 145

#define	AM62LX_DEV_WKUP_GPIO0_MMR_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 146

#define	AM62LX_DEV_GPMC0_FUNC_CLK 147

#define	AM62LX_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK 148

#define	AM62LX_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT3_CLK 149

#define	AM62LX_DEV_GPMC0_PI_GPMC_RET_CLK 150

#define	AM62LX_DEV_GPMC0_VBUSM_CLK 151

#define	AM62LX_DEV_GPMC0_PO_GPMC_DEV_CLK 152

#define	AM62LX_DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK 153

#define	AM62LX_DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK 154

#define	AM62LX_DEV_DSS_DSI0_DPI_0_CLK 155

#define	AM62LX_DEV_DSS_DSI0_PLL_CTRL_CLK 156

#define	AM62LX_DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK 157

#define	AM62LX_DEV_DSS_DSI0_SYS_CLK 158

#define	AM62LX_DEV_DSS0_DPI_0_IN_CLK 159

#define	AM62LX_DEV_DSS0_DPI_0_IN_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 160

#define	AM62LX_DEV_DSS0_DPI_0_IN_CLK_PARENT_BOARD_0_VOUT0_EXTPCLKIN_OUT 161

#define	AM62LX_DEV_DSS0_DSS_FUNC_CLK 162

#define	AM62LX_DEV_DSS0_DPI_0_OUT_CLK 163

#define	AM62LX_DEV_EPWM0_VBUSP_CLK 164

#define	AM62LX_DEV_EPWM1_VBUSP_CLK 165

#define	AM62LX_DEV_EPWM2_VBUSP_CLK 166

#define	AM62LX_DEV_LED0_VBUS_CLK 167

#define	AM62LX_DEV_PBIST0_CLK8_CLK 168

#define	AM62LX_DEV_PBIST0_TCLK_CLK 169

#define	AM62LX_DEV_WKUP_PBIST0_CLK8_CLK 170

#define	AM62LX_DEV_WKUP_VTM0_FIX_REF2_CLK 171

#define	AM62LX_DEV_WKUP_VTM0_FIX_REF_CLK 172

#define	AM62LX_DEV_WKUP_VTM0_VBUSP_CLK 173

#define	AM62LX_DEV_MCAN0_MCANSS_CCLK_CLK 174

#define	AM62LX_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 175

#define	AM62LX_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 176

#define	AM62LX_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 177

#define	AM62LX_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 178

#define	AM62LX_DEV_MCAN0_MCANSS_HCLK_CLK 179

#define	AM62LX_DEV_MCAN1_MCANSS_CCLK_CLK 180

#define	AM62LX_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 181

#define	AM62LX_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 182

#define	AM62LX_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 183

#define	AM62LX_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 184

#define	AM62LX_DEV_MCAN1_MCANSS_HCLK_CLK 185

#define	AM62LX_DEV_MCAN2_MCANSS_CCLK_CLK 186

#define	AM62LX_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK 187

#define	AM62LX_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 188

#define	AM62LX_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 189

#define	AM62LX_DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 190

#define	AM62LX_DEV_MCAN2_MCANSS_HCLK_CLK 191

#define	AM62LX_DEV_MCASP0_AUX_CLK 192

#define	AM62LX_DEV_MCASP0_AUX_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 193

#define	AM62LX_DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT1_CLK 194

#define	AM62LX_DEV_MCASP0_MCASP_ACLKR_PIN 195

#define	AM62LX_DEV_MCASP0_MCASP_ACLKX_PIN 196

#define	AM62LX_DEV_MCASP0_MCASP_AFSR_PIN 197

#define	AM62LX_DEV_MCASP0_MCASP_AFSX_PIN 198

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_PIN 199

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 200

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 201

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 202

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 203

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_PIN 204

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_EXT_REFCLK1_OUT 205

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLK 206

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT 207

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT 208

#define	AM62LX_DEV_MCASP0_VBUSP_CLK 209

#define	AM62LX_DEV_MCASP0_MCASP_ACLKR_POUT 210

#define	AM62LX_DEV_MCASP0_MCASP_ACLKX_POUT 211

#define	AM62LX_DEV_MCASP0_MCASP_AFSR_POUT 212

#define	AM62LX_DEV_MCASP0_MCASP_AFSX_POUT 213

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKR_POUT 214

#define	AM62LX_DEV_MCASP0_MCASP_AHCLKX_POUT 215

#define	AM62LX_DEV_MCASP1_AUX_CLK 216

#define	AM62LX_DEV_MCASP1_MCASP_ACLKR_PIN 217

#define	AM62LX_DEV_MCASP1_MCASP_ACLKX_PIN 218

#define	AM62LX_DEV_MCASP1_MCASP_AFSR_PIN 219

#define	AM62LX_DEV_MCASP1_MCASP_AFSX_PIN 220

#define	AM62LX_DEV_MCASP1_MCASP_AHCLKR_PIN 221

#define	AM62LX_DEV_MCASP1_MCASP_AHCLKX_PIN 222

#define	AM62LX_DEV_MCASP1_VBUSP_CLK 223

#define	AM62LX_DEV_MCASP1_MCASP_ACLKR_POUT 224

#define	AM62LX_DEV_MCASP1_MCASP_ACLKX_POUT 225

#define	AM62LX_DEV_MCASP1_MCASP_AFSR_POUT 226

#define	AM62LX_DEV_MCASP1_MCASP_AFSX_POUT 227

#define	AM62LX_DEV_MCASP1_MCASP_AHCLKR_POUT 228

#define	AM62LX_DEV_MCASP1_MCASP_AHCLKX_POUT 229

#define	AM62LX_DEV_MCASP2_AUX_CLK 230

#define	AM62LX_DEV_MCASP2_MCASP_ACLKR_PIN 231

#define	AM62LX_DEV_MCASP2_MCASP_ACLKX_PIN 232

#define	AM62LX_DEV_MCASP2_MCASP_AFSR_PIN 233

#define	AM62LX_DEV_MCASP2_MCASP_AFSX_PIN 234

#define	AM62LX_DEV_MCASP2_MCASP_AHCLKR_PIN 235

#define	AM62LX_DEV_MCASP2_MCASP_AHCLKX_PIN 236

#define	AM62LX_DEV_MCASP2_VBUSP_CLK 237

#define	AM62LX_DEV_MCASP2_MCASP_ACLKR_POUT 238

#define	AM62LX_DEV_MCASP2_MCASP_ACLKX_POUT 239

#define	AM62LX_DEV_MCASP2_MCASP_AFSR_POUT 240

#define	AM62LX_DEV_MCASP2_MCASP_AFSX_POUT 241

#define	AM62LX_DEV_MCASP2_MCASP_AHCLKR_POUT 242

#define	AM62LX_DEV_MCASP2_MCASP_AHCLKX_POUT 243

#define	AM62LX_DEV_I2C0_CLK 244

#define	AM62LX_DEV_I2C0_PISCL 245

#define	AM62LX_DEV_I2C0_PISYS_CLK 246

#define	AM62LX_DEV_I2C0_PORSCL 247

#define	AM62LX_DEV_I2C1_CLK 248

#define	AM62LX_DEV_I2C1_PISCL 249

#define	AM62LX_DEV_I2C1_PISYS_CLK 250

#define	AM62LX_DEV_I2C1_PORSCL 251

#define	AM62LX_DEV_I2C2_CLK 252

#define	AM62LX_DEV_I2C2_PISCL 253

#define	AM62LX_DEV_I2C2_PISYS_CLK 254

#define	AM62LX_DEV_I2C2_PORSCL 255

#define	AM62LX_DEV_I2C3_CLK 256

#define	AM62LX_DEV_I2C3_PISCL 257

#define	AM62LX_DEV_I2C3_PISYS_CLK 258

#define	AM62LX_DEV_I2C3_PORSCL 259

#define	AM62LX_DEV_WKUP_I2C0_CLK 260

#define	AM62LX_DEV_WKUP_I2C0_PISCL 261

#define	AM62LX_DEV_WKUP_I2C0_PISYS_CLK 262

#define	AM62LX_DEV_WKUP_I2C0_PORSCL 263

#define	AM62LX_DEV_WKUP_GTC0_GTC_CLK 264

#define	AM62LX_DEV_WKUP_GTC0_GTC_CLK_PARENT_WKUP_GTCCLK_SEL_OUT0 265

#define	AM62LX_DEV_WKUP_GTC0_GTC_CLK_PARENT_CLK_32K_RC_SEL_OUT0 266

#define	AM62LX_DEV_WKUP_GTC0_VBUSP_CLK 267

#define	AM62LX_DEV_WKUP_RTCSS0_ANA_OSC32K_CLK 268

#define	AM62LX_DEV_WKUP_RTCSS0_AUX_32K_CLK 269

#define	AM62LX_DEV_WKUP_RTCSS0_JTAG_WRCK 270

#define	AM62LX_DEV_WKUP_RTCSS0_VCLK_CLK 271

#define	AM62LX_DEV_WKUP_RTCSS0_OSC_32K_CLK 272

#define	AM62LX_DEV_RTI0_RTI_CLK 273

#define	AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 274

#define	AM62LX_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 275

#define	AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 276

#define	AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 277

#define	AM62LX_DEV_RTI0_VBUSP_CLK 278

#define	AM62LX_DEV_RTI1_RTI_CLK 279

#define	AM62LX_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 280

#define	AM62LX_DEV_RTI1_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0 281

#define	AM62LX_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 282

#define	AM62LX_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 283

#define	AM62LX_DEV_RTI1_VBUSP_CLK 284

#define	AM62LX_DEV_DEBUGSS0_CFG_CLK 285

#define	AM62LX_DEV_DEBUGSS0_DBG_CLK 286

#define	AM62LX_DEV_DEBUGSS0_SYS_CLK 287

#define	AM62LX_DEV_MSRAM_96K0_VCLK_CLK 288

#define	AM62LX_DEV_WKUP_PSRAM_64K0_CLK_CLK 289

#define	AM62LX_DEV_ROM0_CLK_CLK 290

#define	AM62LX_DEV_PSC0_CLK 291

#define	AM62LX_DEV_PSC0_SLOW_CLK 292

#define	AM62LX_DEV_WKUP_DEEPSLEEP_SOURCES0_CLK_12M_RC_CLK 293

#define	AM62LX_DEV_COMPUTE_CLUSTER0_ARM_COREPACK_0_COREPAC_ARM_CLK_CLK 294

#define	AM62LX_DEV_COMPUTE_CLUSTER0_ARM_COREPACK_0_PLL_CTRL_CLK 295

#define	AM62LX_DEV_COMPUTE_CLUSTER0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 296

#define	AM62LX_DEV_WKUP_DFTSS0_PLL_CLK 297

#define	AM62LX_DEV_WKUP_DFTSS0_VBUSP_CLK_CLK 298

#define	AM62LX_DEV_MCSPI0_CLKSPIREF_CLK 299

#define	AM62LX_DEV_MCSPI0_VBUSP_CLK 300

#define	AM62LX_DEV_MCSPI0_IO_CLKSPIO_CLK 301

#define	AM62LX_DEV_MCSPI1_CLKSPIREF_CLK 302

#define	AM62LX_DEV_MCSPI1_VBUSP_CLK 303

#define	AM62LX_DEV_MCSPI1_IO_CLKSPIO_CLK 304

#define	AM62LX_DEV_MCSPI2_CLKSPIREF_CLK 305

#define	AM62LX_DEV_MCSPI2_VBUSP_CLK 306

#define	AM62LX_DEV_MCSPI2_IO_CLKSPIO_CLK 307

#define	AM62LX_DEV_MCSPI3_CLKSPIREF_CLK 308

#define	AM62LX_DEV_MCSPI3_VBUSP_CLK 309

#define	AM62LX_DEV_MCSPI3_IO_CLKSPIO_CLK 310

#define	AM62LX_DEV_TRNG_DRBG_EIP76D_WRAP0_VCLK_CLK 311

#define	AM62LX_DEV_UART1_FCLK_CLK 312

#define	AM62LX_DEV_UART1_VBUSP_CLK 313

#define	AM62LX_DEV_UART2_FCLK_CLK 314

#define	AM62LX_DEV_UART2_VBUSP_CLK 315

#define	AM62LX_DEV_UART3_FCLK_CLK 316

#define	AM62LX_DEV_UART3_VBUSP_CLK 317

#define	AM62LX_DEV_UART4_FCLK_CLK 318

#define	AM62LX_DEV_UART4_VBUSP_CLK 319

#define	AM62LX_DEV_UART5_FCLK_CLK 320

#define	AM62LX_DEV_UART5_VBUSP_CLK 321

#define	AM62LX_DEV_UART6_FCLK_CLK 322

#define	AM62LX_DEV_UART6_VBUSP_CLK 323

#define	AM62LX_DEV_WKUP_UART0_FCLK_CLK 324

#define	AM62LX_DEV_WKUP_UART0_VBUSP_CLK 325

#define	AM62LX_DEV_USB0_BUS_CLK 326

#define	AM62LX_DEV_USB0_CFG_CLK 327

#define	AM62LX_DEV_USB0_USB2_APB_PCLK_CLK 328

#define	AM62LX_DEV_USB0_USB2_REFCLOCK_CLK 329

#define	AM62LX_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 330

#define	AM62LX_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK4 331

#define	AM62LX_DEV_USB0_USB2_TAP_TCK 332

#define	AM62LX_DEV_USB1_BUS_CLK 333

#define	AM62LX_DEV_USB1_CFG_CLK 334

#define	AM62LX_DEV_USB1_USB2_APB_PCLK_CLK 335

#define	AM62LX_DEV_USB1_USB2_REFCLOCK_CLK 336

#define	AM62LX_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 337

#define	AM62LX_DEV_USB1_USB2_REFCLOCK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK4 338

#define	AM62LX_DEV_USB1_USB2_TAP_TCK 339

#define	AM62LX_DEV_DPHY_TX0_CLK 340

#define	AM62LX_DEV_DPHY_TX0_DPHY_REF_CLK 341

#define	AM62LX_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 342

#define	AM62LX_DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK 343

#define	AM62LX_DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK 344

#define	AM62LX_DEV_DPHY_TX0_IP2_PPI_M_TXCLKESC_CLK 345

#define	AM62LX_DEV_DPHY_TX0_IP3_PPI_M_TXCLKESC_CLK 346

#define	AM62LX_DEV_DPHY_TX0_IP4_PPI_M_TXCLKESC_CLK 347

#define	AM62LX_DEV_DPHY_TX0_PSM_CLK 348

#define	AM62LX_DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK 349

#define	AM62LX_DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK 350

#define	AM62LX_DEV_COMPUTE_CLUSTER0_CLKDIV_0_FUNC_CLKIN_CLK 351

#define	AM62LX_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVH_CLK4_CLK_CLK 352

#define	AM62LX_DEV_COMPUTE_CLUSTER0_CLKDIV_0_DIVP_CLK1_CLK_CLK 353

#define	AM62LX_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVH_CLK4_CLK_CLK 354

#define	AM62LX_DEV_COMPUTE_CLUSTER0_PBIST_0_DIVP_CLK1_CLK_CLK 355

#define	AM62LX_DEV_COMPUTE_CLUSTER0_A53_0_A53_CORE0_ARM_CLK_CLK 356

#define	AM62LX_DEV_COMPUTE_CLUSTER0_A53_1_A53_CORE1_ARM_CLK_CLK 357

#define	AM62LX_DEV_UART0_FCLK_CLK 358

#define	AM62LX_DEV_UART0_VBUSP_CLK 359

#define	AM62LX_DEV_BOARD0_AUDIO_EXT_REFCLK0_IN 360

#define	AM62LX_DEV_BOARD0_AUDIO_EXT_REFCLK1_IN 361

#define	AM62LX_DEV_BOARD0_CLKOUT0_IN 362

#define	AM62LX_DEV_BOARD0_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK5 363

#define	AM62LX_DEV_BOARD0_CLKOUT0_IN_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK10 364

#define	AM62LX_DEV_BOARD0_GPMC0_CLKLB_IN 365

#define	AM62LX_DEV_BOARD0_GPMC0_CLK_IN 366

#define	AM62LX_DEV_BOARD0_GPMC0_FCLK_MUX_IN 367

#define	AM62LX_DEV_BOARD0_I2C0_SCL_IN 368

#define	AM62LX_DEV_BOARD0_I2C1_SCL_IN 369

#define	AM62LX_DEV_BOARD0_I2C2_SCL_IN 370

#define	AM62LX_DEV_BOARD0_I2C3_SCL_IN 371

#define	AM62LX_DEV_BOARD0_MCASP0_ACLKR_IN 372

#define	AM62LX_DEV_BOARD0_MCASP0_ACLKX_IN 373

#define	AM62LX_DEV_BOARD0_MCASP0_AFSR_IN 374

#define	AM62LX_DEV_BOARD0_MCASP0_AFSX_IN 375

#define	AM62LX_DEV_BOARD0_MCASP1_ACLKR_IN 376

#define	AM62LX_DEV_BOARD0_MCASP1_ACLKX_IN 377

#define	AM62LX_DEV_BOARD0_MCASP1_AFSR_IN 378

#define	AM62LX_DEV_BOARD0_MCASP1_AFSX_IN 379

#define	AM62LX_DEV_BOARD0_MCASP2_ACLKR_IN 380

#define	AM62LX_DEV_BOARD0_MCASP2_ACLKX_IN 381

#define	AM62LX_DEV_BOARD0_MCASP2_AFSR_IN 382

#define	AM62LX_DEV_BOARD0_MCASP2_AFSX_IN 383

#define	AM62LX_DEV_BOARD0_MDIO0_MDC_IN 384

#define	AM62LX_DEV_BOARD0_MMC0_CLKLB_IN 385

#define	AM62LX_DEV_BOARD0_MMC0_CLK_IN 386

#define	AM62LX_DEV_BOARD0_MMC1_CLKLB_IN 387

#define	AM62LX_DEV_BOARD0_MMC1_CLK_IN 388

#define	AM62LX_DEV_BOARD0_MMC2_CLKLB_IN 389

#define	AM62LX_DEV_BOARD0_MMC2_CLK_IN 390

#define	AM62LX_DEV_BOARD0_OBSCLK0_IN 391

#define	AM62LX_DEV_BOARD0_OBSCLK1_IN 392

#define	AM62LX_DEV_BOARD0_OSPI0_CLK_IN 393

#define	AM62LX_DEV_BOARD0_OSPI0_LBCLKO_IN 394

#define	AM62LX_DEV_BOARD0_SPI0_CLK_IN 395

#define	AM62LX_DEV_BOARD0_SPI1_CLK_IN 396

#define	AM62LX_DEV_BOARD0_SPI2_CLK_IN 397

#define	AM62LX_DEV_BOARD0_SPI3_CLK_IN 398

#define	AM62LX_DEV_BOARD0_TIMER_IO0_IN 399

#define	AM62LX_DEV_BOARD0_TIMER_IO1_IN 400

#define	AM62LX_DEV_BOARD0_TIMER_IO2_IN 401

#define	AM62LX_DEV_BOARD0_TIMER_IO3_IN 402

#define	AM62LX_DEV_BOARD0_TRC_CLK_IN 403

#define	AM62LX_DEV_BOARD0_WKUP_CLKOUT0_IN 404

#define	AM62LX_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_WKUP_CLKOUT_SEL_OUT0 405

#define	AM62LX_DEV_BOARD0_WKUP_CLKOUT0_IN_PARENT_GLUELOGIC_HFOSC0_CLK 406

#define	AM62LX_DEV_BOARD0_WKUP_OBSCLK0_IN 407

#define	AM62LX_DEV_BOARD0_WKUP_OBSCLK0_IN_PARENT_WKUP_OBSCLK_MUX_SEL_OUT0 408

#define	AM62LX_DEV_BOARD0_WKUP_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLK 409

#define	AM62LX_DEV_BOARD0_WKUP_SYSCLKOUT0_IN 410

#define	AM62LX_DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT 411

#define	AM62LX_DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT 412

#define	AM62LX_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT 413

#define	AM62LX_DEV_BOARD0_EXT_REFCLK1_OUT 414

#define	AM62LX_DEV_BOARD0_GPMC0_CLKLB_OUT 415

#define	AM62LX_DEV_BOARD0_I2C0_SCL_OUT 416

#define	AM62LX_DEV_BOARD0_I2C1_SCL_OUT 417

#define	AM62LX_DEV_BOARD0_I2C2_SCL_OUT 418

#define	AM62LX_DEV_BOARD0_I2C3_SCL_OUT 419

#define	AM62LX_DEV_BOARD0_MCASP0_ACLKR_OUT 420

#define	AM62LX_DEV_BOARD0_MCASP0_ACLKX_OUT 421

#define	AM62LX_DEV_BOARD0_MCASP0_AFSR_OUT 422

#define	AM62LX_DEV_BOARD0_MCASP0_AFSX_OUT 423

#define	AM62LX_DEV_BOARD0_MCASP1_ACLKR_OUT 424

#define	AM62LX_DEV_BOARD0_MCASP1_ACLKX_OUT 425

#define	AM62LX_DEV_BOARD0_MCASP1_AFSR_OUT 426

#define	AM62LX_DEV_BOARD0_MCASP1_AFSX_OUT 427

#define	AM62LX_DEV_BOARD0_MCASP2_ACLKR_OUT 428

#define	AM62LX_DEV_BOARD0_MCASP2_ACLKX_OUT 429

#define	AM62LX_DEV_BOARD0_MCASP2_AFSR_OUT 430

#define	AM62LX_DEV_BOARD0_MCASP2_AFSX_OUT 431

#define	AM62LX_DEV_BOARD0_MMC0_CLKLB_OUT 432

#define	AM62LX_DEV_BOARD0_MMC0_CLK_OUT 433

#define	AM62LX_DEV_BOARD0_MMC1_CLKLB_OUT 434

#define	AM62LX_DEV_BOARD0_MMC1_CLK_OUT 435

#define	AM62LX_DEV_BOARD0_MMC2_CLKLB_OUT 436

#define	AM62LX_DEV_BOARD0_MMC2_CLK_OUT 437

#define	AM62LX_DEV_BOARD0_OSPI0_DQS_OUT 438

#define	AM62LX_DEV_BOARD0_OSPI0_LBCLKO_OUT 439

#define	AM62LX_DEV_BOARD0_RMII1_REF_CLK_OUT 440

#define	AM62LX_DEV_BOARD0_RMII2_REF_CLK_OUT 441

#define	AM62LX_DEV_BOARD0_TCK_OUT 442

#define	AM62LX_DEV_BOARD0_VOUT0_EXTPCLKIN_OUT 443

#define	AM62LX_DEV_BOARD0_WKUP_EXT_REFCLK0_OUT 444

#define	AM62LX_DEV_BOARD0_WKUP_I2C0_SCL_OUT 445

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK 446

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 447

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK 448

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT 449

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_WKUP_EXT_REFCLK0_OUT 450

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT 451

#define	AM62LX_DEV_WKUP_GTCCLK_SEL_DEV_VD_CLK_PARENT_SAM62_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 452

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK 453

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 454

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT8_CLK 455

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT0_CLK 456

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT4_CLK 457

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT0_CLK_DUP0 458

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 459

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 460

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_WKUP_32KHZ_GEN_0_HSDIVOUT0_CLK8 461

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_WKUP_0_HSDIVOUT0_CLK 462

#define	AM62LX_DEV_WKUP_OBSCLK_MUX_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 463

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK 464

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_RTCSS_WKUP_0_OSC_32K_CLK 465

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT7_CLK 466

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_WKUP_0_HSDIVOUT0_CLK2 467

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_POSTDIV4_16FF_WKUP_0_HSDIVOUT8_CLK 468

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_CLK_32K_RC_SEL_OUT0 469

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 470

#define	AM62LX_DEV_WKUP_CLKOUT_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 471

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK 472

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK 473

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF1 474

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_17_HSDIVOUT0_CLK 475

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 476

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_SAM62L_A53_256KB_WRAP_MAIN_0_ARM_COREPACK_0_A53_DIVH_CLK4_OBSCLK_OUT_CLK 477

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK 478

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT 479

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_WKUP_32KHZ_GEN_0_HSDIVOUT0_CLK8 480

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_HSDIV4_16FFT_WKUP_0_HSDIVOUT0_CLK 481

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLK 482

#define	AM62LX_DEV_OBSCLK0_MUX_SEL_DEV_VD_CLK_PARENT_CPSW_3GUSS_AM62L_MAIN_0_CPTS_GENF0 483

#define	AM62LX_DEV_CLK_32K_RC_SEL_DEV_VD_CLK 484

#define	AM62LX_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 485

#define	AM62LX_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_HSDIV0_16FFT_WKUP_32KHZ_GEN_0_HSDIVOUT0_CLK8 486

#define	AM62LX_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3_DUP0 487

#define	AM62LX_DEV_CLK_32K_RC_SEL_DEV_VD_CLK_PARENT_RTCSS_WKUP_0_OSC_32K_CLK 488

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