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Macros | |
#define | MCAN_MSG_RAM_MAX_WORD_COUNT (4352U) |
#define | CSL_EPWM_PER_CNT (9U) |
Number of ePWM instances. More... | |
Core ID's of core or CPUs present on this SOC | |
#define | CSL_CORE_ID_A53SS0_0 (0U) |
#define | CSL_CORE_ID_A53SS0_1 (1U) |
#define | CSL_CORE_ID_MAX (2U) |
#define | CSL_CORE_ID_INVALID (0xFFU) |
R5 Cluster Group IDs | |
#define | CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U) |
R5 Cluster Group ID0. More... | |
#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U) |
#define CSL_CORE_ID_A53SS0_0 (0U) |
#define CSL_CORE_ID_A53SS0_1 (1U) |
#define CSL_CORE_ID_MAX (2U) |
#define CSL_CORE_ID_INVALID (0xFFU) |
#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U) |
R5 Cluster Group ID0.
#define CSL_EPWM_PER_CNT (9U) |
Number of ePWM instances.