AM62L FreeRTOS SDK  11.00.00
cslr_dss.h
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31  *
32  * Name : cslr_dss.h
33  * VPVERSION : 3.0.365 - 2024.01.05.15.15.16
34  * VPREV : 1.1.1.0
35 */
36 #ifndef CSLR_DSS_H_
37 #define CSLR_DSS_H_
38 
39 #ifdef __cplusplus
40 extern "C"
41 {
42 #endif
43 #include <drivers/hw_include/cslr.h>
44 #include <stdint.h>
45 
46 /**************************************************************************
47 * Hardware Region : COMMON Registers
48 **************************************************************************/
49 
50 
51 /**************************************************************************
52 * Register Overlay Structure
53 **************************************************************************/
54 
55 typedef struct {
56  volatile uint8_t Resv_4[4];
57  volatile uint32_t DSS_REVISION; /* DSS_REVISION */
58  volatile uint32_t DSS_SYSCONFIG; /* DSS_SYSCONFIG */
59  volatile uint8_t Resv_32[20];
60  volatile uint32_t DSS_SYSSTATUS; /* DSS_SYSSTATUS */
61  volatile uint32_t DISPC_IRQ_EOI; /* DISPC_IRQ_EOI */
62  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
63  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
64  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
65  volatile uint8_t Resv_64[12];
66  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
67  volatile uint32_t RESERVED_0; /* RESERVED_0 */
68  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
69  volatile uint8_t Resv_88[12];
70  volatile uint32_t RESERVERD_1; /* RESERVED_1 */
71  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
72  volatile uint8_t Resv_112[16];
73  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
74  volatile uint8_t Resv_124[8];
75  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
76  volatile uint8_t Resv_144[16];
77  volatile uint32_t DISPC_GLOBAL_MFLAG_ATTRIBUTE; /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
78  volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE; /* DISPC_GLOBAL_OUTPUT_ENABLE */
79  volatile uint32_t DISPC_GLOBAL_BUFFER; /* DISPC_GLOBAL_BUFFER */
80  volatile uint32_t DSS_CBA_CFG; /* DSS_CBA_CFG */
81  volatile uint32_t DISPC_DBG_CONTROL; /* DISPC_DBG_CONTROL */
82  volatile uint32_t DISPC_DBG_STATUS; /* DISPC_DBG_STATUS */
83  volatile uint32_t DISPC_CLKGATING_DISABLE; /* DISPC_CLKGATING_DISABLE */
84  volatile uint32_t DISPC_SECURE_DISABLE; /* DISPC_SECURE_DISABLE */
86 
87 
88 /**************************************************************************
89 * Register Macros
90 **************************************************************************/
91 
92 #define CSL_DSS_COMMON_DSS_REVISION (0x00000004U)
93 #define CSL_DSS_COMMON_DSS_SYSCONFIG (0x00000008U)
94 #define CSL_DSS_COMMON_DSS_SYSSTATUS (0x00000020U)
95 #define CSL_DSS_COMMON_DISPC_IRQ_EOI (0x00000024U)
96 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW (0x00000028U)
97 #define CSL_DSS_COMMON_DISPC_IRQSTATUS (0x0000002CU)
98 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET (0x00000030U)
99 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR (0x00000040U)
100 #define CSL_DSS_COMMON_RESERVED_0 (0x00000044U)
101 #define CSL_DSS_COMMON_VID_IRQENABLE_1 (0x00000048U)
102 #define CSL_DSS_COMMON_RESERVERD_1 (0x00000058U)
103 #define CSL_DSS_COMMON_VID_IRQSTATUS_1 (0x0000005CU)
104 #define CSL_DSS_COMMON_VP_IRQENABLE_0 (0x00000070U)
105 #define CSL_DSS_COMMON_VP_IRQSTATUS_0 (0x0000007CU)
106 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE (0x00000090U)
107 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE (0x00000094U)
108 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER (0x00000098U)
109 #define CSL_DSS_COMMON_DSS_CBA_CFG (0x0000009CU)
110 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL (0x000000A0U)
111 #define CSL_DSS_COMMON_DISPC_DBG_STATUS (0x000000A4U)
112 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE (0x000000A8U)
113 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE (0x000000ACU)
114 
115 /**************************************************************************
116 * Field Definition Macros
117 **************************************************************************/
118 
119 
120 /* DSS_REVISION */
121 
122 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_MASK (0x0000003FU)
123 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_SHIFT (0x00000000U)
124 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_MAX (0x0000003FU)
125 
126 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_MASK (0x000000C0U)
127 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_SHIFT (0x00000006U)
128 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_MAX (0x00000003U)
129 
130 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_MASK (0x00000700U)
131 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_SHIFT (0x00000008U)
132 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_MAX (0x00000007U)
133 
134 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_MASK (0x0000F800U)
135 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_SHIFT (0x0000000BU)
136 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_MAX (0x0000001FU)
137 
138 #define CSL_DSS_COMMON_DSS_REVISION_MODID_MASK (0xFFFF0000U)
139 #define CSL_DSS_COMMON_DSS_REVISION_MODID_SHIFT (0x00000010U)
140 #define CSL_DSS_COMMON_DSS_REVISION_MODID_MAX (0x0000FFFFU)
141 
142 
143 /* DSS_SYSCONFIG */
144 
145 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_MASK (0x00000001U)
146 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_SHIFT (0x00000000U)
147 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_MAX (0x00000001U)
148 
149 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKFREE (0x0U)
150 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKGATED (0x1U)
151 
152 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_MASK (0x00000002U)
153 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_SHIFT (0x00000001U)
154 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_MAX (0x00000001U)
155 
156 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_MASK (0x00000004U)
157 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_SHIFT (0x00000002U)
158 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_MAX (0x00000001U)
159 
160 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_MASK (0x00000018U)
161 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_SHIFT (0x00000003U)
162 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_MAX (0x00000003U)
163 
164 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_MASK (0x00000020U)
165 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_SHIFT (0x00000005U)
166 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_MAX (0x00000001U)
167 
168 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_MASK (0x000000C0U)
169 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_SHIFT (0x00000006U)
170 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_MAX (0x00000003U)
171 
172 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_MASK (0x00003F00U)
173 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_SHIFT (0x00000008U)
174 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_MAX (0x0000003FU)
175 
176 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_MASK (0xFFFFC000U)
177 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_SHIFT (0x0000000EU)
178 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_MAX (0x0003FFFFU)
179 
180 
181 /* DSS_SYSSTATUS */
182 
183 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MASK (0x00000001U)
184 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_SHIFT (0x00000000U)
185 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MAX (0x00000001U)
186 
187 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTONGOING (0x0U)
188 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTCOMP (0x1U)
189 
190 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MASK (0x00000006U)
191 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_SHIFT (0x00000001U)
192 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MAX (0x00000003U)
193 
194 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTONGOING (0x0U)
195 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTCOMP (0x1U)
196 
197 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_MASK (0x00000010U)
198 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_SHIFT (0x00000004U)
199 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_MAX (0x00000001U)
200 
201 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_MASK (0x00000020U)
202 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_SHIFT (0x00000005U)
203 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_MAX (0x00000001U)
204 
205 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_VAL_RSTONGOING (0x0U)
206 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_VAL_RSTCOMP (0x1U)
207 
208 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_MASK (0x00000100U)
209 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_SHIFT (0x00000008U)
210 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_MAX (0x00000001U)
211 
212 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MASK (0x00000200U)
213 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_SHIFT (0x00000009U)
214 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MAX (0x00000001U)
215 
216 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_NOTIDLE (0x0U)
217 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_IDLE (0x1U)
218 
219 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_MASK (0xFFFFFC00U)
220 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_SHIFT (0x0000000AU)
221 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_MAX (0x003FFFFFU)
222 
223 
224 /* DISPC_IRQ_EOI */
225 
226 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_MASK (0x00000001U)
227 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_SHIFT (0x00000000U)
228 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_MAX (0x00000001U)
229 
230 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_VAL_NOACTION (0x0U)
231 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_VAL_EOI (0x1U)
232 
233 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_MASK (0xFFFFFFFEU)
234 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_SHIFT (0x00000001U)
235 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_MAX (0x7FFFFFFFU)
236 
237 
238 /* DISPC_IRQSTATUS_RAW */
239 
240 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x00000003U)
241 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
242 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x00000003U)
243 
244 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
245 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
246 
247 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x00000030U)
248 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
249 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x00000003U)
250 
251 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
252 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
253 
254 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFF8000U)
255 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x0000000FU)
256 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x0001FFFFU)
257 
258 
259 /* DISPC_IRQSTATUS */
260 
261 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_MASK (0x00000003U)
262 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
263 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_MAX (0x00000003U)
264 
265 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
266 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
267 
268 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_MASK (0x00000030U)
269 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
270 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_MAX (0x00000003U)
271 
272 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
273 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
274 
275 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFF8000U)
276 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_SHIFT (0x0000000FU)
277 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_MAX (0x0001FFFFU)
278 
279 
280 /* DISPC_IRQENABLE_SET */
281 
282 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x00000003U)
283 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
284 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x00000003U)
285 
286 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
287 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
288 
289 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x00000030U)
290 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
291 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x00000003U)
292 
293 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
294 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
295 
296 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFF8000U)
297 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x0000000FU)
298 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_MAX (0x0001FFFFU)
299 
300 
301 /* DISPC_IRQENABLE_CLR */
302 
303 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x00000003U)
304 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
305 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x00000003U)
306 
307 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
308 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
309 
310 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x00000030U)
311 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
312 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x00000003U)
313 
314 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
315 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
316 
317 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFF8000U)
318 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x0000000FU)
319 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x0001FFFFU)
320 
321 
322 /* RESERVED_0 */
323 
324 #define CSL_DSS_COMMON_RESERVED_0_RSVD_0_MASK (0x00000001U)
325 #define CSL_DSS_COMMON_RESERVED_0_RSVD_0_SHIFT (0x00000000U)
326 #define CSL_DSS_COMMON_RESERVED_0_RSVD_0_MAX (0x00000001U)
327 
328 #define CSL_DSS_COMMON_RESERVED_0_RSVD_1_MASK (0x00000002U)
329 #define CSL_DSS_COMMON_RESERVED_0_RSVD_1_SHIFT (0x00000001U)
330 #define CSL_DSS_COMMON_RESERVED_0_RSVD_1_MAX (0x00000001U)
331 
332 #define CSL_DSS_COMMON_RESERVED_0_RSVD_2_MASK (0x00000004U)
333 #define CSL_DSS_COMMON_RESERVED_0_RSVD_2_SHIFT (0x00000002U)
334 #define CSL_DSS_COMMON_RESERVED_0_RSVD_2_MAX (0x00000001U)
335 
336 #define CSL_DSS_COMMON_RESERVED_0_RSVD_3_MASK (0xFFFFFFF8U)
337 #define CSL_DSS_COMMON_RESERVED_0_RSVD_3_SHIFT (0x00000003U)
338 #define CSL_DSS_COMMON_RESERVED_0_RSVD_3_MAX (0x1FFFFFFFU)
339 
340 
341 /* VID_IRQENABLE_1 */
342 
343 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
344 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
345 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
346 
347 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
348 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
349 
350 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
351 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
352 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
353 
354 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
355 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
356 
357 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
358 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
359 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
360 
361 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
362 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
363 
364 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFF8U)
365 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000003U)
366 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_MAX (0x1FFFFFFFU)
367 
368 
369 /* RESERVERD_1 */
370 
371 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_0_MASK (0x00000001U)
372 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_0_SHIFT (0x00000000U)
373 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_0_MAX (0x00000001U)
374 
375 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_1_MASK (0x00000002U)
376 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_1_SHIFT (0x00000001U)
377 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_1_MAX (0x00000001U)
378 
379 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_2_MASK (0x00000004U)
380 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_2_SHIFT (0x00000002U)
381 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_2_MAX (0x00000001U)
382 
383 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_3_MASK (0xFFFFFFF8U)
384 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_3_SHIFT (0x00000003U)
385 #define CSL_DSS_COMMON_RESERVERD_1_RSVD_3_MAX (0x1FFFFFFFU)
386 
387 
388 /* VID_IRQSTATUS_1 */
389 
390 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
391 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
392 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
393 
394 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
395 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
396 
397 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
398 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
399 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
400 
401 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
402 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
403 
404 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
405 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
406 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
407 
408 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
409 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
410 
411 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFF8U)
412 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000003U)
413 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_MAX (0x1FFFFFFFU)
414 
415 
416 /* VP_IRQENABLE_0 */
417 
418 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
419 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
420 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
421 
422 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
423 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
424 
425 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
426 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
427 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
428 
429 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
430 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
431 
432 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
433 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
434 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
435 
436 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
437 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
438 
439 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
440 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
441 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
442 
443 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
444 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
445 
446 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
447 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
448 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
449 
450 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
451 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
452 
453 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
454 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
455 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
456 
457 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
458 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
459 
460 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
461 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
462 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
463 
464 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
465 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
466 
467 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
468 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
469 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
470 
471 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
472 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
473 
474 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
475 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
476 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
477 
478 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
479 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
480 
481 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
482 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
483 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
484 
485 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
486 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
487 
488 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_MASK (0xFFFFE000U)
489 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_SHIFT (0x0000000DU)
490 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_MAX (0x0007FFFFU)
491 
492 
493 /* VP_IRQSTATUS_0 */
494 
495 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
496 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
497 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
498 
499 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
500 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
501 
502 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
503 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
504 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
505 
506 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
507 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
508 
509 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
510 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
511 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
512 
513 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
514 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
515 
516 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
517 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
518 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
519 
520 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
521 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
522 
523 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
524 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
525 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
526 
527 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
528 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
529 
530 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
531 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
532 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
533 
534 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
535 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
536 
537 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
538 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
539 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
540 
541 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
542 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
543 
544 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
545 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
546 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
547 
548 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
549 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
550 
551 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
552 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
553 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
554 
555 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
556 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
557 
558 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
559 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
560 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
561 
562 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
563 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
564 
565 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFFE000U)
566 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_SHIFT (0x0000000DU)
567 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_MAX (0x0007FFFFU)
568 
569 
570 /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
571 
572 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK (0x00000003U)
573 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_SHIFT (0x00000000U)
574 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MAX (0x00000003U)
575 
576 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGDIS (0x0U)
577 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGFORCE (0x1U)
578 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGEN (0x2U)
579 
580 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MASK (0x0000003CU)
581 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_SHIFT (0x00000002U)
582 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MAX (0x0000000FU)
583 
584 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK (0x00000040U)
585 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_SHIFT (0x00000006U)
586 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MAX (0x00000001U)
587 
588 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGNORMALSTARTMODE (0x0U)
589 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGFORCESTARTMODE (0x1U)
590 
591 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MASK (0x00000180U)
592 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_SHIFT (0x00000007U)
593 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MAX (0x00000003U)
594 
595 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MASK (0xFFFFFE00U)
596 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_SHIFT (0x00000009U)
597 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MAX (0x007FFFFFU)
598 
599 
600 /* DISPC_GLOBAL_OUTPUT_ENABLE */
601 
602 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MASK (0x00000007U)
603 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_SHIFT (0x00000000U)
604 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MAX (0x00000007U)
605 
606 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_DISABLE (0x0U)
607 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_ENABLE (0x1U)
608 
609 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_MASK (0x00000008U)
610 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_SHIFT (0x00000003U)
611 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_MAX (0x00000001U)
612 
613 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MASK (0x0000FFF0U)
614 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_SHIFT (0x00000004U)
615 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MAX (0x00000FFFU)
616 
617 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MASK (0x00070000U)
618 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_SHIFT (0x00000010U)
619 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MAX (0x00000007U)
620 
621 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_HFUISR (0x0U)
622 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_UFPSR (0x1U)
623 
624 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_MASK (0x00080000U)
625 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_SHIFT (0x00000013U)
626 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_MAX (0x00000001U)
627 
628 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MASK (0xFFF00000U)
629 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_SHIFT (0x00000014U)
630 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MAX (0x00000FFFU)
631 
632 
633 /* DISPC_GLOBAL_BUFFER */
634 
635 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_MASK (0x00000007U)
636 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_SHIFT (0x00000000U)
637 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_MAX (0x00000007U)
638 
639 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MASK (0x00000038U)
640 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_SHIFT (0x00000003U)
641 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MAX (0x00000007U)
642 
643 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_MASK (0x000001C0U)
644 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_SHIFT (0x00000006U)
645 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_MAX (0x00000007U)
646 
647 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_MASK (0x00000E00U)
648 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_SHIFT (0x00000009U)
649 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_MAX (0x00000007U)
650 
651 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_MASK (0x00007000U)
652 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_SHIFT (0x0000000CU)
653 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_MAX (0x00000007U)
654 
655 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_MASK (0x7FFF8000U)
656 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_SHIFT (0x0000000FU)
657 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_MAX (0x0000FFFFU)
658 
659 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MASK (0x80000000U)
660 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_SHIFT (0x0000001FU)
661 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MAX (0x00000001U)
662 
663 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_INDIVIDUALPIPE (0x0U)
664 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_ALLPIPES (0x1U)
665 
666 
667 /* DSS_CBA_CFG */
668 
669 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_MASK (0x00000007U)
670 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_SHIFT (0x00000000U)
671 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_MAX (0x00000007U)
672 
673 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_MASK (0x00000038U)
674 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_SHIFT (0x00000003U)
675 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_MAX (0x00000007U)
676 
677 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_MASK (0x000001C0U)
678 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_SHIFT (0x00000006U)
679 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_MAX (0x00000007U)
680 
681 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_MASK (0xFFFFFE00U)
682 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_SHIFT (0x00000009U)
683 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_MAX (0x007FFFFFU)
684 
685 
686 /* DISPC_DBG_CONTROL */
687 
688 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_MASK (0x00000001U)
689 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_SHIFT (0x00000000U)
690 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_MAX (0x00000001U)
691 
692 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_VAL_DBGDIS (0x0U)
693 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_VAL_DBGEN (0x1U)
694 
695 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_MASK (0x000001FEU)
696 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_SHIFT (0x00000001U)
697 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_MAX (0x000000FFU)
698 
699 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDSEL (0x0U)
700 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDL1SEL (0x8U)
701 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR1SEL (0x11U)
702 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR2SEL (0x12U)
703 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP1SEL (0x13U)
704 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP2SEL (0x15U)
705 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_MISCSEL (0x17U)
706 
707 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_MASK (0xFFFFFE00U)
708 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_SHIFT (0x00000009U)
709 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_MAX (0x007FFFFFU)
710 
711 
712 /* DISPC_DBG_STATUS */
713 
714 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_MASK (0xFFFFFFFFU)
715 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_SHIFT (0x00000000U)
716 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_MAX (0xFFFFFFFFU)
717 
718 
719 /* DISPC_CLKGATING_DISABLE */
720 
721 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_MASK (0x00000001U)
722 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_SHIFT (0x00000000U)
723 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_MAX (0x00000001U)
724 
725 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGEN (0x0U)
726 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGDIS (0x1U)
727 
728 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_MASK (0x00000006U)
729 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_SHIFT (0x00000001U)
730 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_MAX (0x00000003U)
731 
732 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_MASK (0x00000018U)
733 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_SHIFT (0x00000003U)
734 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_MAX (0x00000003U)
735 
736 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGEN (0x0U)
737 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGDIS (0x1U)
738 
739 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_MASK (0x00000F80U)
740 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_SHIFT (0x00000007U)
741 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_MAX (0x0000001FU)
742 
743 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_MASK (0x00001000U)
744 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_SHIFT (0x0000000CU)
745 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_MAX (0x00000001U)
746 
747 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_MASK (0x0000C000U)
748 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_SHIFT (0x0000000EU)
749 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_MAX (0x00000003U)
750 
751 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGEN (0x0U)
752 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGDIS (0x1U)
753 
754 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_MASK (0x00020000U)
755 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_SHIFT (0x00000011U)
756 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_MAX (0x00000001U)
757 
758 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP1_MASK (0x000C0000U)
759 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP1_SHIFT (0x00000012U)
760 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP1_MAX (0x00000003U)
761 
762 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP1_VAL_CLKGATINGEN (0x0U)
763 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP1_VAL_CLKGATINGDIS (0x1U)
764 
765 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_MASK (0x00200000U)
766 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_SHIFT (0x00000015U)
767 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_MAX (0x00000001U)
768 
769 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_MASK (0xFFC00000U)
770 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_SHIFT (0x00000016U)
771 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_MAX (0x000003FFU)
772 
773 
774 /* DISPC_SECURE_DISABLE */
775 
776 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_MASK (0x00000001U)
777 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_SHIFT (0x00000000U)
778 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_MAX (0x00000001U)
779 
780 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREEN (0x0U)
781 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREDIS (0x1U)
782 
783 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_MASK (0xFFFFFFFEU)
784 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_SHIFT (0x00000001U)
785 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_MAX (0x7FFFFFFFU)
786 
787 
788 /**************************************************************************
789 * Hardware Region : COMMON1 Registers
790 **************************************************************************/
791 
792 
793 /**************************************************************************
794 * Register Overlay Structure
795 **************************************************************************/
796 
797 typedef struct {
798  volatile uint8_t Resv_36[36];
799  volatile uint32_t DISPC_IRQ_EOI; /* DISPC_IRQ_EOI */
800  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
801  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
802  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
803  volatile uint8_t Resv_64[12];
804  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
805  volatile uint32_t RESERVED_0; /* RESERVED_0 */
806  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
807  volatile uint8_t Resv_84[8];
808  volatile uint32_t DISPC_SECURE; /* DISPC_SECURE */
809  volatile uint32_t RESERVERD_1; /* RESERVED_1 */
810  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
811  volatile uint8_t Resv_112[16];
812  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
813  volatile uint8_t Resv_124[8];
814  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
816 
817 
818 /**************************************************************************
819 * Register Macros
820 **************************************************************************/
821 
822 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI (0x00000024U)
823 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW (0x00000028U)
824 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS (0x0000002CU)
825 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET (0x00000030U)
826 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR (0x00000040U)
827 #define CSL_DSS_COMMON1_RESERVED_0 (0x00000044U)
828 #define CSL_DSS_COMMON1_VID_IRQENABLE_1 (0x00000048U)
829 #define CSL_DSS_COMMON1_DISPC_SECURE (0x00000054U)
830 #define CSL_DSS_COMMON1_RESERVERD_1 (0x00000058U)
831 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1 (0x0000005CU)
832 #define CSL_DSS_COMMON1_VP_IRQENABLE_0 (0x00000070U)
833 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0 (0x0000007CU)
834 
835 /**************************************************************************
836 * Field Definition Macros
837 **************************************************************************/
838 
839 
840 /* DISPC_IRQ_EOI */
841 
842 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_MASK (0x00000001U)
843 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_SHIFT (0x00000000U)
844 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_MAX (0x00000001U)
845 
846 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_VAL_NOACTION (0x0U)
847 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_VAL_EOI (0x1U)
848 
849 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_MASK (0xFFFFFFFEU)
850 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_SHIFT (0x00000001U)
851 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_MAX (0x7FFFFFFFU)
852 
853 
854 /* DISPC_IRQSTATUS_RAW */
855 
856 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x00000003U)
857 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
858 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x00000003U)
859 
860 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
861 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
862 
863 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x00000030U)
864 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
865 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x00000003U)
866 
867 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
868 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
869 
870 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFF8000U)
871 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x0000000FU)
872 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x0001FFFFU)
873 
874 
875 /* DISPC_IRQSTATUS */
876 
877 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_MASK (0x00000003U)
878 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
879 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_MAX (0x00000003U)
880 
881 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
882 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
883 
884 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_MASK (0x00000030U)
885 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
886 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_MAX (0x00000003U)
887 
888 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
889 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
890 
891 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFF8000U)
892 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_SHIFT (0x0000000FU)
893 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_MAX (0x0001FFFFU)
894 
895 
896 /* DISPC_IRQENABLE_SET */
897 
898 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x00000003U)
899 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
900 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x00000003U)
901 
902 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
903 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
904 
905 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x00000030U)
906 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
907 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x00000003U)
908 
909 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
910 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
911 
912 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFF8000U)
913 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x0000000FU)
914 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_MAX (0x0001FFFFU)
915 
916 
917 /* DISPC_IRQENABLE_CLR */
918 
919 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x00000003U)
920 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
921 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x00000003U)
922 
923 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
924 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
925 
926 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x00000030U)
927 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
928 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x00000003U)
929 
930 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
931 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
932 
933 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFF8000U)
934 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x0000000FU)
935 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x0001FFFFU)
936 
937 
938 /* RESERVED_0 */
939 
940 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_0_MASK (0x00000001U)
941 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_0_SHIFT (0x00000000U)
942 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_0_MAX (0x00000001U)
943 
944 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_1_MASK (0x00000002U)
945 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_1_SHIFT (0x00000001U)
946 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_1_MAX (0x00000001U)
947 
948 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_2_MASK (0x00000004U)
949 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_2_SHIFT (0x00000002U)
950 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_2_MAX (0x00000001U)
951 
952 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_3_MASK (0xFFFFFFF8U)
953 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_3_SHIFT (0x00000003U)
954 #define CSL_DSS_COMMON1_RESERVED_0_RSVD_3_MAX (0x1FFFFFFFU)
955 
956 
957 /* VID_IRQENABLE_1 */
958 
959 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
960 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
961 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
962 
963 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
964 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
965 
966 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
967 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
968 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
969 
970 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
971 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
972 
973 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
974 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
975 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
976 
977 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
978 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
979 
980 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFF8U)
981 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000003U)
982 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_MAX (0x1FFFFFFFU)
983 
984 
985 /* DISPC_SECURE */
986 
987 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_MASK (0x00000003U)
988 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_SHIFT (0x00000000U)
989 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_MAX (0x00000003U)
990 
991 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_VAL_SECUREDIS (0x0U)
992 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_VAL_SECUREEN (0x1U)
993 
994 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_MASK (0x00000004U)
995 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_SHIFT (0x00000002U)
996 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_MAX (0x00000001U)
997 
998 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_MASK (0x00000008U)
999 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_SHIFT (0x00000003U)
1000 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_MAX (0x00000001U)
1001 
1002 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_MASK (0x00000030U)
1003 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_SHIFT (0x00000004U)
1004 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_MAX (0x00000003U)
1005 
1006 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_VAL_SECUREDIS (0x0U)
1007 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_VAL_SECUREEN (0x1U)
1008 
1009 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED6_MASK (0x000000C0U)
1010 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED6_SHIFT (0x00000006U)
1011 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED6_MAX (0x00000003U)
1012 
1013 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_MASK (0x00001F00U)
1014 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_SHIFT (0x00000008U)
1015 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_MAX (0x0000001FU)
1016 
1017 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_MASK (0x00002000U)
1018 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_SHIFT (0x0000000DU)
1019 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_MAX (0x00000001U)
1020 
1021 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED7_MASK (0x00004000U)
1022 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED7_SHIFT (0x0000000EU)
1023 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED7_MAX (0x00000001U)
1024 
1025 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_MASK (0x00018000U)
1026 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_SHIFT (0x0000000FU)
1027 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_MAX (0x00000003U)
1028 
1029 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_VAL_SECUREDIS (0x0U)
1030 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_VAL_SECUREEN (0x1U)
1031 
1032 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED8_MASK (0x00020000U)
1033 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED8_SHIFT (0x00000011U)
1034 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED8_MAX (0x00000001U)
1035 
1036 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED4_MASK (0x00040000U)
1037 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED4_SHIFT (0x00000012U)
1038 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED4_MAX (0x00000001U)
1039 
1040 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_MASK (0xFFF80000U)
1041 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_SHIFT (0x00000013U)
1042 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_MAX (0x00001FFFU)
1043 
1044 
1045 /* RESERVERD_1 */
1046 
1047 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_0_MASK (0x00000001U)
1048 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_0_SHIFT (0x00000000U)
1049 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_0_MAX (0x00000001U)
1050 
1051 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_1_MASK (0x00000002U)
1052 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_1_SHIFT (0x00000001U)
1053 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_1_MAX (0x00000001U)
1054 
1055 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_2_MASK (0x00000004U)
1056 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_2_SHIFT (0x00000002U)
1057 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_2_MAX (0x00000001U)
1058 
1059 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_3_MASK (0xFFFFFFF8U)
1060 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_3_SHIFT (0x00000003U)
1061 #define CSL_DSS_COMMON1_RESERVERD_1_RSVD_3_MAX (0x1FFFFFFFU)
1062 
1063 
1064 /* VID_IRQSTATUS_1 */
1065 
1066 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
1067 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
1068 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
1069 
1070 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
1071 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
1072 
1073 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
1074 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
1075 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
1076 
1077 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
1078 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
1079 
1080 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
1081 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
1082 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
1083 
1084 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1085 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1086 
1087 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFF8U)
1088 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000003U)
1089 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_MAX (0x1FFFFFFFU)
1090 
1091 
1092 /* VP_IRQENABLE_0 */
1093 
1094 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
1095 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
1096 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
1097 
1098 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
1099 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
1100 
1101 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
1102 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
1103 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
1104 
1105 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
1106 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
1107 
1108 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
1109 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
1110 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
1111 
1112 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
1113 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
1114 
1115 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
1116 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
1117 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
1118 
1119 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
1120 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
1121 
1122 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
1123 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
1124 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
1125 
1126 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
1127 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
1128 
1129 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
1130 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
1131 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
1132 
1133 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
1134 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
1135 
1136 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
1137 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
1138 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
1139 
1140 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
1141 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
1142 
1143 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
1144 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
1145 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
1146 
1147 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1148 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1149 
1150 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
1151 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
1152 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
1153 
1154 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
1155 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
1156 
1157 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
1158 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
1159 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
1160 
1161 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
1162 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
1163 
1164 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_MASK (0xFFFFE000U)
1165 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_SHIFT (0x0000000DU)
1166 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_MAX (0x0007FFFFU)
1167 
1168 
1169 /* VP_IRQSTATUS_0 */
1170 
1171 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1172 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1173 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1174 
1175 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1176 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1177 
1178 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
1179 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
1180 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
1181 
1182 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1183 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
1184 
1185 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1186 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1187 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1188 
1189 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1190 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1191 
1192 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1193 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1194 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1195 
1196 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1197 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1198 
1199 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
1200 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1201 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
1202 
1203 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1204 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1205 
1206 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1207 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1208 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1209 
1210 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1211 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1212 
1213 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
1214 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1215 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
1216 
1217 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1218 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1219 
1220 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1221 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1222 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1223 
1224 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1225 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1226 
1227 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
1228 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
1229 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
1230 
1231 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1232 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
1233 
1234 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
1235 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
1236 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
1237 
1238 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
1239 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
1240 
1241 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFFE000U)
1242 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_SHIFT (0x0000000DU)
1243 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_MAX (0x0007FFFFU)
1244 
1245 
1246 /**************************************************************************
1247 * Hardware Region : VIDL1 Registers
1248 **************************************************************************/
1249 
1250 
1251 /**************************************************************************
1252 * Register Overlay Structure
1253 **************************************************************************/
1254 
1255 typedef struct {
1256  volatile uint8_t Resv_32[32];
1257  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
1258  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
1259  volatile uint32_t BA_0; /* BA_0 */
1260  volatile uint32_t BA_1; /* BA_1 */
1261  volatile uint32_t BA_UV_0; /* BA_UV_0 */
1262  volatile uint32_t BA_UV_1; /* BA_UV_1 */
1263  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
1264  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
1265  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
1266  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
1267  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
1268  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
1269  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
1270  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
1271  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
1272  volatile uint8_t Resv_508[416];
1273  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
1274  volatile uint8_t Resv_520[8];
1275  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
1276  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
1277  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
1278  volatile uint8_t Resv_536[4];
1279  volatile uint32_t PRELOAD; /* PRELOAD */
1280  volatile uint32_t ROW_INC; /* ROW_INC */
1281  volatile uint8_t Resv_556[12];
1282  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
1283  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
1284  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
1285  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
1286  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
1287  volatile uint8_t Resv_584[8];
1288  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
1289  volatile uint8_t Resv_608[20];
1290  volatile uint32_t CLUT_0; /* CLUT_0 */
1291  volatile uint32_t CLUT_1; /* CLUT_1 */
1292  volatile uint32_t CLUT_2; /* CLUT_2 */
1293  volatile uint32_t CLUT_3; /* CLUT_3 */
1294  volatile uint32_t CLUT_4; /* CLUT_4 */
1295  volatile uint32_t CLUT_5; /* CLUT_5 */
1296  volatile uint32_t CLUT_6; /* CLUT_6 */
1297  volatile uint32_t CLUT_7; /* CLUT_7 */
1298  volatile uint32_t CLUT_8; /* CLUT_8 */
1299  volatile uint32_t CLUT_9; /* CLUT_9 */
1300  volatile uint32_t CLUT_10; /* CLUT_10 */
1301  volatile uint32_t CLUT_11; /* CLUT_11 */
1302  volatile uint32_t CLUT_12; /* CLUT_12 */
1303  volatile uint32_t CLUT_13; /* CLUT_13 */
1304  volatile uint32_t CLUT_14; /* CLUT_14 */
1305  volatile uint32_t CLUT_15; /* CLUT_15 */
1306  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
1307  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
1308  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
1309  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
1310  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
1311  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
1312  volatile uint32_t LUMAKEY; /* LUMAKEY */
1314 
1315 
1316 /**************************************************************************
1317 * Register Macros
1318 **************************************************************************/
1319 
1320 #define CSL_DSS_VIDL1_ATTRIBUTES (0x00000020U)
1321 #define CSL_DSS_VIDL1_ATTRIBUTES2 (0x00000024U)
1322 #define CSL_DSS_VIDL1_BA_0 (0x00000028U)
1323 #define CSL_DSS_VIDL1_BA_1 (0x0000002CU)
1324 #define CSL_DSS_VIDL1_BA_UV_0 (0x00000030U)
1325 #define CSL_DSS_VIDL1_BA_UV_1 (0x00000034U)
1326 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS (0x00000038U)
1327 #define CSL_DSS_VIDL1_BUF_THRESHOLD (0x0000003CU)
1328 #define CSL_DSS_VIDL1_CSC_COEF0 (0x00000040U)
1329 #define CSL_DSS_VIDL1_CSC_COEF1 (0x00000044U)
1330 #define CSL_DSS_VIDL1_CSC_COEF2 (0x00000048U)
1331 #define CSL_DSS_VIDL1_CSC_COEF3 (0x0000004CU)
1332 #define CSL_DSS_VIDL1_CSC_COEF4 (0x00000050U)
1333 #define CSL_DSS_VIDL1_CSC_COEF5 (0x00000054U)
1334 #define CSL_DSS_VIDL1_CSC_COEF6 (0x00000058U)
1335 #define CSL_DSS_VIDL1_GLOBAL_ALPHA (0x000001FCU)
1336 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD (0x00000208U)
1337 #define CSL_DSS_VIDL1_PICTURE_SIZE (0x0000020CU)
1338 #define CSL_DSS_VIDL1_PIXEL_INC (0x00000210U)
1339 #define CSL_DSS_VIDL1_PRELOAD (0x00000218U)
1340 #define CSL_DSS_VIDL1_ROW_INC (0x0000021CU)
1341 #define CSL_DSS_VIDL1_BA_EXT_0 (0x0000022CU)
1342 #define CSL_DSS_VIDL1_BA_EXT_1 (0x00000230U)
1343 #define CSL_DSS_VIDL1_BA_UV_EXT_0 (0x00000234U)
1344 #define CSL_DSS_VIDL1_BA_UV_EXT_1 (0x00000238U)
1345 #define CSL_DSS_VIDL1_CSC_COEF7 (0x0000023CU)
1346 #define CSL_DSS_VIDL1_ROW_INC_UV (0x00000248U)
1347 #define CSL_DSS_VIDL1_CLUT_0 (0x00000260U)
1348 #define CSL_DSS_VIDL1_CLUT_1 (0x00000264U)
1349 #define CSL_DSS_VIDL1_CLUT_2 (0x00000268U)
1350 #define CSL_DSS_VIDL1_CLUT_3 (0x0000026CU)
1351 #define CSL_DSS_VIDL1_CLUT_4 (0x00000270U)
1352 #define CSL_DSS_VIDL1_CLUT_5 (0x00000274U)
1353 #define CSL_DSS_VIDL1_CLUT_6 (0x00000278U)
1354 #define CSL_DSS_VIDL1_CLUT_7 (0x0000027CU)
1355 #define CSL_DSS_VIDL1_CLUT_8 (0x00000280U)
1356 #define CSL_DSS_VIDL1_CLUT_9 (0x00000284U)
1357 #define CSL_DSS_VIDL1_CLUT_10 (0x00000288U)
1358 #define CSL_DSS_VIDL1_CLUT_11 (0x0000028CU)
1359 #define CSL_DSS_VIDL1_CLUT_12 (0x00000290U)
1360 #define CSL_DSS_VIDL1_CLUT_13 (0x00000294U)
1361 #define CSL_DSS_VIDL1_CLUT_14 (0x00000298U)
1362 #define CSL_DSS_VIDL1_CLUT_15 (0x0000029CU)
1363 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES (0x000002A0U)
1364 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE (0x000002A4U)
1365 #define CSL_DSS_VIDL1_SAFETY_POSITION (0x000002A8U)
1366 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE (0x000002ACU)
1367 #define CSL_DSS_VIDL1_SAFETY_SIZE (0x000002B0U)
1368 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED (0x000002B4U)
1369 #define CSL_DSS_VIDL1_LUMAKEY (0x000002B8U)
1370 
1371 /**************************************************************************
1372 * Field Definition Macros
1373 **************************************************************************/
1374 
1375 
1376 /* ATTRIBUTES */
1377 
1378 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
1379 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
1380 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
1381 
1382 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
1383 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
1384 
1385 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
1386 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
1387 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
1388 
1389 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
1390 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
1391 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
1392 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
1393 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
1394 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
1395 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
1396 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
1397 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
1398 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
1399 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
1400 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
1401 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
1402 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
1403 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
1404 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
1405 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
1406 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
1407 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
1408 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
1409 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
1410 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
1411 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
1412 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
1413 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
1414 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
1415 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
1416 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
1417 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
1418 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
1419 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
1420 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
1421 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
1422 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
1423 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
1424 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
1425 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
1426 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
1427 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
1428 
1429 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MASK (0x00000180U)
1430 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_SHIFT (0x00000007U)
1431 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MAX (0x00000003U)
1432 
1433 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
1434 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
1435 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
1436 
1437 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
1438 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
1439 
1440 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
1441 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
1442 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
1443 
1444 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
1445 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
1446 
1447 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
1448 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
1449 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
1450 
1451 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
1452 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
1453 
1454 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MASK (0x00001000U)
1455 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
1456 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MAX (0x00000001U)
1457 
1458 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
1459 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
1460 
1461 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_MASK (0x00002000U)
1462 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_SHIFT (0x0000000DU)
1463 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
1464 
1465 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
1466 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
1467 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
1468 
1469 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
1470 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
1471 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
1472 
1473 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
1474 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
1475 
1476 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
1477 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
1478 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
1479 
1480 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
1481 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
1482 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
1483 
1484 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
1485 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
1486 
1487 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
1488 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
1489 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
1490 
1491 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MASK (0x00200000U)
1492 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_SHIFT (0x00000015U)
1493 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MAX (0x00000001U)
1494 
1495 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
1496 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
1497 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
1498 
1499 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
1500 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
1501 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
1502 
1503 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
1504 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
1505 
1506 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
1507 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
1508 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
1509 
1510 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
1511 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
1512 
1513 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
1514 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
1515 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
1516 
1517 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
1518 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
1519 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
1520 
1521 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
1522 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
1523 
1524 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_MASK (0x20000000U)
1525 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_SHIFT (0x0000001DU)
1526 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_MAX (0x00000001U)
1527 
1528 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
1529 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
1530 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
1531 
1532 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
1533 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
1534 
1535 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
1536 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
1537 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
1538 
1539 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
1540 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
1541 
1542 
1543 /* ATTRIBUTES2 */
1544 
1545 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
1546 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
1547 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
1548 
1549 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
1550 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
1551 
1552 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
1553 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
1554 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
1555 
1556 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
1557 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
1558 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
1559 
1560 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
1561 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
1562 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
1563 
1564 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
1565 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
1566 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
1567 
1568 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
1569 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
1570 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
1571 
1572 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
1573 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
1574 
1575 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
1576 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
1577 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
1578 
1579 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
1580 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
1581 
1582 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_MASK (0x03FFF800U)
1583 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_SHIFT (0x0000000BU)
1584 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_MAX (0x00007FFFU)
1585 
1586 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
1587 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
1588 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
1589 
1590 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
1591 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
1592 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
1593 
1594 
1595 /* BA_0 */
1596 
1597 #define CSL_DSS_VIDL1_BA_0_BA_MASK (0xFFFFFFFFU)
1598 #define CSL_DSS_VIDL1_BA_0_BA_SHIFT (0x00000000U)
1599 #define CSL_DSS_VIDL1_BA_0_BA_MAX (0xFFFFFFFFU)
1600 
1601 
1602 /* BA_1 */
1603 
1604 #define CSL_DSS_VIDL1_BA_1_BA_MASK (0xFFFFFFFFU)
1605 #define CSL_DSS_VIDL1_BA_1_BA_SHIFT (0x00000000U)
1606 #define CSL_DSS_VIDL1_BA_1_BA_MAX (0xFFFFFFFFU)
1607 
1608 
1609 /* BA_UV_0 */
1610 
1611 #define CSL_DSS_VIDL1_BA_UV_0_BA_MASK (0xFFFFFFFFU)
1612 #define CSL_DSS_VIDL1_BA_UV_0_BA_SHIFT (0x00000000U)
1613 #define CSL_DSS_VIDL1_BA_UV_0_BA_MAX (0xFFFFFFFFU)
1614 
1615 
1616 /* BA_UV_1 */
1617 
1618 #define CSL_DSS_VIDL1_BA_UV_1_BA_MASK (0xFFFFFFFFU)
1619 #define CSL_DSS_VIDL1_BA_UV_1_BA_SHIFT (0x00000000U)
1620 #define CSL_DSS_VIDL1_BA_UV_1_BA_MAX (0xFFFFFFFFU)
1621 
1622 
1623 /* BUF_SIZE_STATUS */
1624 
1625 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
1626 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
1627 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
1628 
1629 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
1630 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
1631 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
1632 
1633 
1634 /* BUF_THRESHOLD */
1635 
1636 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
1637 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
1638 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
1639 
1640 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
1641 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
1642 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
1643 
1644 
1645 /* CSC_COEF0 */
1646 
1647 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MASK (0x000007FFU)
1648 #define CSL_DSS_VIDL1_CSC_COEF0_C00_SHIFT (0x00000000U)
1649 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MAX (0x000007FFU)
1650 
1651 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
1652 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
1653 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
1654 
1655 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MASK (0x07FF0000U)
1656 #define CSL_DSS_VIDL1_CSC_COEF0_C01_SHIFT (0x00000010U)
1657 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MAX (0x000007FFU)
1658 
1659 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
1660 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
1661 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
1662 
1663 
1664 /* CSC_COEF1 */
1665 
1666 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MASK (0x000007FFU)
1667 #define CSL_DSS_VIDL1_CSC_COEF1_C02_SHIFT (0x00000000U)
1668 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MAX (0x000007FFU)
1669 
1670 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
1671 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
1672 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
1673 
1674 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MASK (0x07FF0000U)
1675 #define CSL_DSS_VIDL1_CSC_COEF1_C10_SHIFT (0x00000010U)
1676 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MAX (0x000007FFU)
1677 
1678 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
1679 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
1680 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
1681 
1682 
1683 /* CSC_COEF2 */
1684 
1685 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MASK (0x000007FFU)
1686 #define CSL_DSS_VIDL1_CSC_COEF2_C11_SHIFT (0x00000000U)
1687 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MAX (0x000007FFU)
1688 
1689 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
1690 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
1691 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
1692 
1693 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MASK (0x07FF0000U)
1694 #define CSL_DSS_VIDL1_CSC_COEF2_C12_SHIFT (0x00000010U)
1695 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MAX (0x000007FFU)
1696 
1697 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
1698 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
1699 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
1700 
1701 
1702 /* CSC_COEF3 */
1703 
1704 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MASK (0x000007FFU)
1705 #define CSL_DSS_VIDL1_CSC_COEF3_C20_SHIFT (0x00000000U)
1706 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MAX (0x000007FFU)
1707 
1708 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
1709 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
1710 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
1711 
1712 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MASK (0x07FF0000U)
1713 #define CSL_DSS_VIDL1_CSC_COEF3_C21_SHIFT (0x00000010U)
1714 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MAX (0x000007FFU)
1715 
1716 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
1717 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
1718 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
1719 
1720 
1721 /* CSC_COEF4 */
1722 
1723 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MASK (0x000007FFU)
1724 #define CSL_DSS_VIDL1_CSC_COEF4_C22_SHIFT (0x00000000U)
1725 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MAX (0x000007FFU)
1726 
1727 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
1728 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
1729 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
1730 
1731 
1732 /* CSC_COEF5 */
1733 
1734 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MASK (0x00000007U)
1735 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
1736 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MAX (0x00000007U)
1737 
1738 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
1739 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
1740 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
1741 
1742 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
1743 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
1744 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
1745 
1746 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
1747 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
1748 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
1749 
1750 
1751 /* CSC_COEF6 */
1752 
1753 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MASK (0x00000007U)
1754 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
1755 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MAX (0x00000007U)
1756 
1757 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
1758 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
1759 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
1760 
1761 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
1762 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
1763 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
1764 
1765 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
1766 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
1767 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
1768 
1769 
1770 /* GLOBAL_ALPHA */
1771 
1772 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
1773 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
1774 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
1775 
1776 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
1777 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
1778 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
1779 
1780 
1781 /* MFLAG_THRESHOLD */
1782 
1783 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
1784 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
1785 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
1786 
1787 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
1788 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
1789 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
1790 
1791 
1792 /* PICTURE_SIZE */
1793 
1794 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MASK (0x00000FFFU)
1795 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
1796 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MAX (0x00000FFFU)
1797 
1798 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_MASK (0x0000F000U)
1799 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_SHIFT (0x0000000CU)
1800 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_MAX (0x0000000FU)
1801 
1802 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MASK (0x0FFF0000U)
1803 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
1804 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MAX (0x00000FFFU)
1805 
1806 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_MASK (0xF0000000U)
1807 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_SHIFT (0x0000001CU)
1808 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_MAX (0x0000000FU)
1809 
1810 
1811 /* PIXEL_INC */
1812 
1813 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
1814 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
1815 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
1816 
1817 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
1818 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
1819 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
1820 
1821 
1822 /* PRELOAD */
1823 
1824 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MASK (0x00000FFFU)
1825 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_SHIFT (0x00000000U)
1826 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MAX (0x00000FFFU)
1827 
1828 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
1829 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
1830 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
1831 
1832 
1833 /* ROW_INC */
1834 
1835 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
1836 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_SHIFT (0x00000000U)
1837 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
1838 
1839 
1840 /* BA_EXT_0 */
1841 
1842 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
1843 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
1844 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
1845 
1846 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
1847 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
1848 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
1849 
1850 
1851 /* BA_EXT_1 */
1852 
1853 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
1854 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
1855 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
1856 
1857 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
1858 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
1859 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
1860 
1861 
1862 /* BA_UV_EXT_0 */
1863 
1864 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
1865 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
1866 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
1867 
1868 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
1869 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
1870 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
1871 
1872 
1873 /* BA_UV_EXT_1 */
1874 
1875 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
1876 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
1877 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
1878 
1879 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
1880 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
1881 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
1882 
1883 
1884 /* CSC_COEF7 */
1885 
1886 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MASK (0x00000007U)
1887 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
1888 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MAX (0x00000007U)
1889 
1890 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
1891 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
1892 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
1893 
1894 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
1895 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
1896 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
1897 
1898 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
1899 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
1900 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
1901 
1902 
1903 /* ROW_INC_UV */
1904 
1905 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
1906 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
1907 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
1908 
1909 
1910 /* CLUT_0 */
1911 
1912 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MASK (0x000000FFU)
1913 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_SHIFT (0x00000000U)
1914 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MAX (0x000000FFU)
1915 
1916 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MASK (0x0000FF00U)
1917 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_SHIFT (0x00000008U)
1918 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MAX (0x000000FFU)
1919 
1920 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MASK (0x00FF0000U)
1921 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_SHIFT (0x00000010U)
1922 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MAX (0x000000FFU)
1923 
1924 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MASK (0xFF000000U)
1925 #define CSL_DSS_VIDL1_CLUT_0_INDEX_SHIFT (0x00000018U)
1926 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MAX (0x000000FFU)
1927 
1928 
1929 /* CLUT_1 */
1930 
1931 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MASK (0x000000FFU)
1932 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_SHIFT (0x00000000U)
1933 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MAX (0x000000FFU)
1934 
1935 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MASK (0x0000FF00U)
1936 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_SHIFT (0x00000008U)
1937 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MAX (0x000000FFU)
1938 
1939 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MASK (0x00FF0000U)
1940 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_SHIFT (0x00000010U)
1941 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MAX (0x000000FFU)
1942 
1943 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MASK (0xFF000000U)
1944 #define CSL_DSS_VIDL1_CLUT_1_INDEX_SHIFT (0x00000018U)
1945 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MAX (0x000000FFU)
1946 
1947 
1948 /* CLUT_2 */
1949 
1950 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MASK (0x000000FFU)
1951 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_SHIFT (0x00000000U)
1952 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MAX (0x000000FFU)
1953 
1954 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MASK (0x0000FF00U)
1955 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_SHIFT (0x00000008U)
1956 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MAX (0x000000FFU)
1957 
1958 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MASK (0x00FF0000U)
1959 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_SHIFT (0x00000010U)
1960 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MAX (0x000000FFU)
1961 
1962 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MASK (0xFF000000U)
1963 #define CSL_DSS_VIDL1_CLUT_2_INDEX_SHIFT (0x00000018U)
1964 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MAX (0x000000FFU)
1965 
1966 
1967 /* CLUT_3 */
1968 
1969 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MASK (0x000000FFU)
1970 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_SHIFT (0x00000000U)
1971 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MAX (0x000000FFU)
1972 
1973 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MASK (0x0000FF00U)
1974 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_SHIFT (0x00000008U)
1975 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MAX (0x000000FFU)
1976 
1977 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MASK (0x00FF0000U)
1978 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_SHIFT (0x00000010U)
1979 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MAX (0x000000FFU)
1980 
1981 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MASK (0xFF000000U)
1982 #define CSL_DSS_VIDL1_CLUT_3_INDEX_SHIFT (0x00000018U)
1983 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MAX (0x000000FFU)
1984 
1985 
1986 /* CLUT_4 */
1987 
1988 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MASK (0x000000FFU)
1989 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_SHIFT (0x00000000U)
1990 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MAX (0x000000FFU)
1991 
1992 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MASK (0x0000FF00U)
1993 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_SHIFT (0x00000008U)
1994 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MAX (0x000000FFU)
1995 
1996 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MASK (0x00FF0000U)
1997 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_SHIFT (0x00000010U)
1998 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MAX (0x000000FFU)
1999 
2000 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MASK (0xFF000000U)
2001 #define CSL_DSS_VIDL1_CLUT_4_INDEX_SHIFT (0x00000018U)
2002 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MAX (0x000000FFU)
2003 
2004 
2005 /* CLUT_5 */
2006 
2007 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MASK (0x000000FFU)
2008 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_SHIFT (0x00000000U)
2009 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MAX (0x000000FFU)
2010 
2011 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MASK (0x0000FF00U)
2012 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_SHIFT (0x00000008U)
2013 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MAX (0x000000FFU)
2014 
2015 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MASK (0x00FF0000U)
2016 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_SHIFT (0x00000010U)
2017 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MAX (0x000000FFU)
2018 
2019 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MASK (0xFF000000U)
2020 #define CSL_DSS_VIDL1_CLUT_5_INDEX_SHIFT (0x00000018U)
2021 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MAX (0x000000FFU)
2022 
2023 
2024 /* CLUT_6 */
2025 
2026 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MASK (0x000000FFU)
2027 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_SHIFT (0x00000000U)
2028 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MAX (0x000000FFU)
2029 
2030 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MASK (0x0000FF00U)
2031 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_SHIFT (0x00000008U)
2032 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MAX (0x000000FFU)
2033 
2034 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MASK (0x00FF0000U)
2035 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_SHIFT (0x00000010U)
2036 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MAX (0x000000FFU)
2037 
2038 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MASK (0xFF000000U)
2039 #define CSL_DSS_VIDL1_CLUT_6_INDEX_SHIFT (0x00000018U)
2040 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MAX (0x000000FFU)
2041 
2042 
2043 /* CLUT_7 */
2044 
2045 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MASK (0x000000FFU)
2046 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_SHIFT (0x00000000U)
2047 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MAX (0x000000FFU)
2048 
2049 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MASK (0x0000FF00U)
2050 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_SHIFT (0x00000008U)
2051 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MAX (0x000000FFU)
2052 
2053 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MASK (0x00FF0000U)
2054 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_SHIFT (0x00000010U)
2055 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MAX (0x000000FFU)
2056 
2057 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MASK (0xFF000000U)
2058 #define CSL_DSS_VIDL1_CLUT_7_INDEX_SHIFT (0x00000018U)
2059 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MAX (0x000000FFU)
2060 
2061 
2062 /* CLUT_8 */
2063 
2064 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MASK (0x000000FFU)
2065 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_SHIFT (0x00000000U)
2066 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MAX (0x000000FFU)
2067 
2068 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MASK (0x0000FF00U)
2069 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_SHIFT (0x00000008U)
2070 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MAX (0x000000FFU)
2071 
2072 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MASK (0x00FF0000U)
2073 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_SHIFT (0x00000010U)
2074 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MAX (0x000000FFU)
2075 
2076 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MASK (0xFF000000U)
2077 #define CSL_DSS_VIDL1_CLUT_8_INDEX_SHIFT (0x00000018U)
2078 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MAX (0x000000FFU)
2079 
2080 
2081 /* CLUT_9 */
2082 
2083 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MASK (0x000000FFU)
2084 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_SHIFT (0x00000000U)
2085 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MAX (0x000000FFU)
2086 
2087 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MASK (0x0000FF00U)
2088 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_SHIFT (0x00000008U)
2089 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MAX (0x000000FFU)
2090 
2091 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MASK (0x00FF0000U)
2092 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_SHIFT (0x00000010U)
2093 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MAX (0x000000FFU)
2094 
2095 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MASK (0xFF000000U)
2096 #define CSL_DSS_VIDL1_CLUT_9_INDEX_SHIFT (0x00000018U)
2097 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MAX (0x000000FFU)
2098 
2099 
2100 /* CLUT_10 */
2101 
2102 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MASK (0x000000FFU)
2103 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_SHIFT (0x00000000U)
2104 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MAX (0x000000FFU)
2105 
2106 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MASK (0x0000FF00U)
2107 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_SHIFT (0x00000008U)
2108 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MAX (0x000000FFU)
2109 
2110 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MASK (0x00FF0000U)
2111 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_SHIFT (0x00000010U)
2112 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MAX (0x000000FFU)
2113 
2114 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MASK (0xFF000000U)
2115 #define CSL_DSS_VIDL1_CLUT_10_INDEX_SHIFT (0x00000018U)
2116 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MAX (0x000000FFU)
2117 
2118 
2119 /* CLUT_11 */
2120 
2121 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MASK (0x000000FFU)
2122 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_SHIFT (0x00000000U)
2123 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MAX (0x000000FFU)
2124 
2125 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MASK (0x0000FF00U)
2126 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_SHIFT (0x00000008U)
2127 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MAX (0x000000FFU)
2128 
2129 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MASK (0x00FF0000U)
2130 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_SHIFT (0x00000010U)
2131 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MAX (0x000000FFU)
2132 
2133 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MASK (0xFF000000U)
2134 #define CSL_DSS_VIDL1_CLUT_11_INDEX_SHIFT (0x00000018U)
2135 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MAX (0x000000FFU)
2136 
2137 
2138 /* CLUT_12 */
2139 
2140 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MASK (0x000000FFU)
2141 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_SHIFT (0x00000000U)
2142 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MAX (0x000000FFU)
2143 
2144 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MASK (0x0000FF00U)
2145 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_SHIFT (0x00000008U)
2146 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MAX (0x000000FFU)
2147 
2148 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MASK (0x00FF0000U)
2149 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_SHIFT (0x00000010U)
2150 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MAX (0x000000FFU)
2151 
2152 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MASK (0xFF000000U)
2153 #define CSL_DSS_VIDL1_CLUT_12_INDEX_SHIFT (0x00000018U)
2154 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MAX (0x000000FFU)
2155 
2156 
2157 /* CLUT_13 */
2158 
2159 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MASK (0x000000FFU)
2160 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_SHIFT (0x00000000U)
2161 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MAX (0x000000FFU)
2162 
2163 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MASK (0x0000FF00U)
2164 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_SHIFT (0x00000008U)
2165 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MAX (0x000000FFU)
2166 
2167 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MASK (0x00FF0000U)
2168 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_SHIFT (0x00000010U)
2169 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MAX (0x000000FFU)
2170 
2171 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MASK (0xFF000000U)
2172 #define CSL_DSS_VIDL1_CLUT_13_INDEX_SHIFT (0x00000018U)
2173 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MAX (0x000000FFU)
2174 
2175 
2176 /* CLUT_14 */
2177 
2178 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MASK (0x000000FFU)
2179 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_SHIFT (0x00000000U)
2180 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MAX (0x000000FFU)
2181 
2182 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MASK (0x0000FF00U)
2183 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_SHIFT (0x00000008U)
2184 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MAX (0x000000FFU)
2185 
2186 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MASK (0x00FF0000U)
2187 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_SHIFT (0x00000010U)
2188 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MAX (0x000000FFU)
2189 
2190 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MASK (0xFF000000U)
2191 #define CSL_DSS_VIDL1_CLUT_14_INDEX_SHIFT (0x00000018U)
2192 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MAX (0x000000FFU)
2193 
2194 
2195 /* CLUT_15 */
2196 
2197 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MASK (0x000000FFU)
2198 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_SHIFT (0x00000000U)
2199 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MAX (0x000000FFU)
2200 
2201 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MASK (0x0000FF00U)
2202 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_SHIFT (0x00000008U)
2203 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MAX (0x000000FFU)
2204 
2205 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MASK (0x00FF0000U)
2206 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_SHIFT (0x00000010U)
2207 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MAX (0x000000FFU)
2208 
2209 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MASK (0xFF000000U)
2210 #define CSL_DSS_VIDL1_CLUT_15_INDEX_SHIFT (0x00000018U)
2211 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MAX (0x000000FFU)
2212 
2213 
2214 /* SAFETY_ATTRIBUTES */
2215 
2216 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
2217 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
2218 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
2219 
2220 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
2221 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
2222 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
2223 
2224 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
2225 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
2226 
2227 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
2228 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
2229 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
2230 
2231 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
2232 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
2233 
2234 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
2235 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
2236 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
2237 
2238 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
2239 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
2240 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
2241 
2242 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
2243 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
2244 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
2245 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
2246 
2247 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
2248 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
2249 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
2250 
2251 
2252 /* SAFETY_CAPT_SIGNATURE */
2253 
2254 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
2255 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
2256 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
2257 
2258 
2259 /* SAFETY_POSITION */
2260 
2261 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
2262 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
2263 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
2264 
2265 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
2266 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
2267 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
2268 
2269 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
2270 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
2271 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
2272 
2273 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
2274 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
2275 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
2276 
2277 
2278 /* SAFETY_REF_SIGNATURE */
2279 
2280 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
2281 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
2282 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
2283 
2284 
2285 /* SAFETY_SIZE */
2286 
2287 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
2288 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
2289 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
2290 
2291 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
2292 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
2293 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
2294 
2295 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
2296 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
2297 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
2298 
2299 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
2300 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
2301 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
2302 
2303 
2304 /* SAFETY_LFSR_SEED */
2305 
2306 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
2307 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
2308 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
2309 
2310 
2311 /* LUMAKEY */
2312 
2313 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MASK (0xF0000000U)
2314 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
2315 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MAX (0x0000000FU)
2316 
2317 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
2318 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
2319 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
2320 
2321 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MASK (0x0000F000U)
2322 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
2323 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MAX (0x0000000FU)
2324 
2325 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
2326 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
2327 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
2328 
2329 
2330 /**************************************************************************
2331 * Hardware Region : OVR1 Registers
2332 **************************************************************************/
2333 
2334 
2335 /**************************************************************************
2336 * Register Overlay Structure
2337 **************************************************************************/
2338 
2339 typedef struct {
2340  volatile uint32_t CONFIG; /* CONFIG */
2341  volatile uint8_t Resv_8[4];
2342  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
2343  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
2344  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
2345  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
2346  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
2347  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
2348  volatile uint32_t ATTRIBUTES_0; /* ATTRIBUTES_0 */
2349  volatile uint32_t RESERVED_1; /* RESERVED */
2350  volatile uint32_t RESERVED_2; /* RESERVED */
2351  volatile uint32_t RESERVED_3; /* RESERVED */
2353 
2354 
2355 /**************************************************************************
2356 * Register Macros
2357 **************************************************************************/
2358 
2359 #define CSL_DSS_OVR1_CONFIG (0x00000000U)
2360 #define CSL_DSS_OVR1_DEFAULT_COLOR (0x00000008U)
2361 #define CSL_DSS_OVR1_DEFAULT_COLOR2 (0x0000000CU)
2362 #define CSL_DSS_OVR1_TRANS_COLOR_MAX (0x00000010U)
2363 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2 (0x00000014U)
2364 #define CSL_DSS_OVR1_TRANS_COLOR_MIN (0x00000018U)
2365 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2 (0x0000001CU)
2366 #define CSL_DSS_OVR1_ATTRIBUTES_0 (0x00000020U)
2367 #define CSL_DSS_OVR1_RESERVED_1 (0x00000024U)
2368 #define CSL_DSS_OVR1_RESERVED_2 (0x00000028U)
2369 #define CSL_DSS_OVR1_RESERVED_3 (0x0000002CU)
2370 
2371 /**************************************************************************
2372 * Field Definition Macros
2373 **************************************************************************/
2374 
2375 
2376 /* CONFIG */
2377 
2378 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MASK (0x00000001U)
2379 #define CSL_DSS_OVR1_CONFIG_RESERVED6_SHIFT (0x00000000U)
2380 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MAX (0x00000001U)
2381 
2382 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MASK (0x00000002U)
2383 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_SHIFT (0x00000001U)
2384 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MAX (0x00000001U)
2385 
2386 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
2387 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
2388 
2389 #define CSL_DSS_OVR1_CONFIG_RESERVED_MASK (0x000003FCU)
2390 #define CSL_DSS_OVR1_CONFIG_RESERVED_SHIFT (0x00000002U)
2391 #define CSL_DSS_OVR1_CONFIG_RESERVED_MAX (0x000000FFU)
2392 
2393 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
2394 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
2395 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
2396 
2397 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
2398 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
2399 
2400 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
2401 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
2402 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
2403 
2404 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
2405 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
2406 
2407 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MASK (0x00001000U)
2408 #define CSL_DSS_OVR1_CONFIG_RESERVED2_SHIFT (0x0000000CU)
2409 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MAX (0x00000001U)
2410 
2411 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MASK (0x00002000U)
2412 #define CSL_DSS_OVR1_CONFIG_RESERVED3_SHIFT (0x0000000DU)
2413 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MAX (0x00000001U)
2414 
2415 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MASK (0xFFFFC000U)
2416 #define CSL_DSS_OVR1_CONFIG_RESERVED1_SHIFT (0x0000000EU)
2417 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MAX (0x0003FFFFU)
2418 
2419 
2420 /* DEFAULT_COLOR */
2421 
2422 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
2423 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
2424 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
2425 
2426 
2427 /* DEFAULT_COLOR2 */
2428 
2429 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
2430 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
2431 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
2432 
2433 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
2434 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
2435 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
2436 
2437 
2438 /* TRANS_COLOR_MAX */
2439 
2440 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
2441 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
2442 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
2443 
2444 
2445 /* TRANS_COLOR_MAX2 */
2446 
2447 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
2448 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
2449 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
2450 
2451 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
2452 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
2453 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
2454 
2455 
2456 /* TRANS_COLOR_MIN */
2457 
2458 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
2459 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
2460 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
2461 
2462 
2463 /* TRANS_COLOR_MIN2 */
2464 
2465 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
2466 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
2467 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
2468 
2469 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
2470 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
2471 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
2472 
2473 
2474 /* ATTRIBUTES_0 */
2475 
2476 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSX_MASK (0x0003FFC0U)
2477 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSX_SHIFT (0x00000006U)
2478 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSX_MAX (0x00000FFFU)
2479 
2480 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED_MASK (0x00040000U)
2481 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED_SHIFT (0x00000012U)
2482 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED_MAX (0x00000001U)
2483 
2484 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSY_MASK (0x7FF80000U)
2485 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSY_SHIFT (0x00000013U)
2486 #define CSL_DSS_OVR1_ATTRIBUTES_0_POSY_MAX (0x00000FFFU)
2487 
2488 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED1_MASK (0x80000000U)
2489 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED1_SHIFT (0x0000001FU)
2490 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED1_MAX (0x00000001U)
2491 
2492 #define CSL_DSS_OVR1_ATTRIBUTES_0_ENABLE_MASK (0x00000001U)
2493 #define CSL_DSS_OVR1_ATTRIBUTES_0_ENABLE_SHIFT (0x00000000U)
2494 #define CSL_DSS_OVR1_ATTRIBUTES_0_ENABLE_MAX (0x00000001U)
2495 
2496 #define CSL_DSS_OVR1_ATTRIBUTES_0_CHANNELIN_MASK (0x0000001EU)
2497 #define CSL_DSS_OVR1_ATTRIBUTES_0_CHANNELIN_SHIFT (0x00000001U)
2498 #define CSL_DSS_OVR1_ATTRIBUTES_0_CHANNELIN_MAX (0x0000000FU)
2499 
2500 #define CSL_DSS_OVR1_ATTRIBUTES_0_CHANNELIN_VAL_VIDL1 (0x1U)
2501 
2502 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED2_MASK (0x00000020U)
2503 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED2_SHIFT (0x00000005U)
2504 #define CSL_DSS_OVR1_ATTRIBUTES_0_RESERVED2_MAX (0x00000001U)
2505 
2506 
2507 /* RESERVED_1 */
2508 
2509 #define CSL_DSS_OVR1_RESERVED_1_RSVD_0_MASK (0x0003FFC0U)
2510 #define CSL_DSS_OVR1_RESERVED_1_RSVD_0_SHIFT (0x00000006U)
2511 #define CSL_DSS_OVR1_RESERVED_1_RSVD_0_MAX (0x00000FFFU)
2512 
2513 #define CSL_DSS_OVR1_RESERVED_1_RSVD_1_MASK (0x00040000U)
2514 #define CSL_DSS_OVR1_RESERVED_1_RSVD_1_SHIFT (0x00000012U)
2515 #define CSL_DSS_OVR1_RESERVED_1_RSVD_1_MAX (0x00000001U)
2516 
2517 #define CSL_DSS_OVR1_RESERVED_1_RSVD_2_MASK (0x7FF80000U)
2518 #define CSL_DSS_OVR1_RESERVED_1_RSVD_2_SHIFT (0x00000013U)
2519 #define CSL_DSS_OVR1_RESERVED_1_RSVD_2_MAX (0x00000FFFU)
2520 
2521 #define CSL_DSS_OVR1_RESERVED_1_RSVD_3_MASK (0x80000000U)
2522 #define CSL_DSS_OVR1_RESERVED_1_RSVD_3_SHIFT (0x0000001FU)
2523 #define CSL_DSS_OVR1_RESERVED_1_RSVD_3_MAX (0x00000001U)
2524 
2525 #define CSL_DSS_OVR1_RESERVED_1_RSVD_4_MASK (0x00000001U)
2526 #define CSL_DSS_OVR1_RESERVED_1_RSVD_4_SHIFT (0x00000000U)
2527 #define CSL_DSS_OVR1_RESERVED_1_RSVD_4_MAX (0x00000001U)
2528 
2529 #define CSL_DSS_OVR1_RESERVED_1_RSVD_5_MASK (0x0000001EU)
2530 #define CSL_DSS_OVR1_RESERVED_1_RSVD_5_SHIFT (0x00000001U)
2531 #define CSL_DSS_OVR1_RESERVED_1_RSVD_5_MAX (0x0000000FU)
2532 
2533 #define CSL_DSS_OVR1_RESERVED_1_RSVD_6_MASK (0x00000020U)
2534 #define CSL_DSS_OVR1_RESERVED_1_RSVD_6_SHIFT (0x00000005U)
2535 #define CSL_DSS_OVR1_RESERVED_1_RSVD_6_MAX (0x00000001U)
2536 
2537 
2538 /* RESERVED_2 */
2539 
2540 #define CSL_DSS_OVR1_RESERVED_2_RSVD_0_MASK (0x0003FFC0U)
2541 #define CSL_DSS_OVR1_RESERVED_2_RSVD_0_SHIFT (0x00000006U)
2542 #define CSL_DSS_OVR1_RESERVED_2_RSVD_0_MAX (0x00000FFFU)
2543 
2544 #define CSL_DSS_OVR1_RESERVED_2_RSVD_1_MASK (0x00040000U)
2545 #define CSL_DSS_OVR1_RESERVED_2_RSVD_1_SHIFT (0x00000012U)
2546 #define CSL_DSS_OVR1_RESERVED_2_RSVD_1_MAX (0x00000001U)
2547 
2548 #define CSL_DSS_OVR1_RESERVED_2_RSVD_2_MASK (0x7FF80000U)
2549 #define CSL_DSS_OVR1_RESERVED_2_RSVD_2_SHIFT (0x00000013U)
2550 #define CSL_DSS_OVR1_RESERVED_2_RSVD_2_MAX (0x00000FFFU)
2551 
2552 #define CSL_DSS_OVR1_RESERVED_2_RSVD_3_MASK (0x80000000U)
2553 #define CSL_DSS_OVR1_RESERVED_2_RSVD_3_SHIFT (0x0000001FU)
2554 #define CSL_DSS_OVR1_RESERVED_2_RSVD_3_MAX (0x00000001U)
2555 
2556 #define CSL_DSS_OVR1_RESERVED_2_RSVD_4_MASK (0x00000001U)
2557 #define CSL_DSS_OVR1_RESERVED_2_RSVD_4_SHIFT (0x00000000U)
2558 #define CSL_DSS_OVR1_RESERVED_2_RSVD_4_MAX (0x00000001U)
2559 
2560 #define CSL_DSS_OVR1_RESERVED_2_RSVD_5_MASK (0x0000001EU)
2561 #define CSL_DSS_OVR1_RESERVED_2_RSVD_5_SHIFT (0x00000001U)
2562 #define CSL_DSS_OVR1_RESERVED_2_RSVD_5_MAX (0x0000000FU)
2563 
2564 #define CSL_DSS_OVR1_RESERVED_2_RSVD_6_MASK (0x00000020U)
2565 #define CSL_DSS_OVR1_RESERVED_2_RSVD_6_SHIFT (0x00000005U)
2566 #define CSL_DSS_OVR1_RESERVED_2_RSVD_6_MAX (0x00000001U)
2567 
2568 
2569 /* RESERVED_3 */
2570 
2571 #define CSL_DSS_OVR1_RESERVED_3_RSVD_0_MASK (0x0003FFC0U)
2572 #define CSL_DSS_OVR1_RESERVED_3_RSVD_0_SHIFT (0x00000006U)
2573 #define CSL_DSS_OVR1_RESERVED_3_RSVD_0_MAX (0x00000FFFU)
2574 
2575 #define CSL_DSS_OVR1_RESERVED_3_RSVD_1_MASK (0x00040000U)
2576 #define CSL_DSS_OVR1_RESERVED_3_RSVD_1_SHIFT (0x00000012U)
2577 #define CSL_DSS_OVR1_RESERVED_3_RSVD_1_MAX (0x00000001U)
2578 
2579 #define CSL_DSS_OVR1_RESERVED_3_RSVD_2_MASK (0x7FF80000U)
2580 #define CSL_DSS_OVR1_RESERVED_3_RSVD_2_SHIFT (0x00000013U)
2581 #define CSL_DSS_OVR1_RESERVED_3_RSVD_2_MAX (0x00000FFFU)
2582 
2583 #define CSL_DSS_OVR1_RESERVED_3_RSVD_3_MASK (0x80000000U)
2584 #define CSL_DSS_OVR1_RESERVED_3_RSVD_3_SHIFT (0x0000001FU)
2585 #define CSL_DSS_OVR1_RESERVED_3_RSVD_3_MAX (0x00000001U)
2586 
2587 #define CSL_DSS_OVR1_RESERVED_3_RSVD_4_MASK (0x00000001U)
2588 #define CSL_DSS_OVR1_RESERVED_3_RSVD_4_SHIFT (0x00000000U)
2589 #define CSL_DSS_OVR1_RESERVED_3_RSVD_4_MAX (0x00000001U)
2590 
2591 #define CSL_DSS_OVR1_RESERVED_3_RSVD_5_MASK (0x0000001EU)
2592 #define CSL_DSS_OVR1_RESERVED_3_RSVD_5_SHIFT (0x00000001U)
2593 #define CSL_DSS_OVR1_RESERVED_3_RSVD_5_MAX (0x0000000FU)
2594 
2595 #define CSL_DSS_OVR1_RESERVED_3_RSVD_6_MASK (0x00000020U)
2596 #define CSL_DSS_OVR1_RESERVED_3_RSVD_6_SHIFT (0x00000005U)
2597 #define CSL_DSS_OVR1_RESERVED_3_RSVD_6_MAX (0x00000001U)
2598 
2599 
2600 /**************************************************************************
2601 * Hardware Region : VP1 Registers
2602 **************************************************************************/
2603 
2604 
2605 /**************************************************************************
2606 * Register Overlay Structure
2607 **************************************************************************/
2608 
2609 typedef struct {
2610  volatile uint32_t CONFIG; /* CONFIG */
2611  volatile uint32_t CONTROL; /* CONTROL */
2612  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
2613  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
2614  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
2615  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
2616  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
2617  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
2618  volatile uint8_t Resv_68[36];
2619  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
2620  volatile uint8_t Resv_76[4];
2621  volatile uint32_t POL_FREQ; /* POL_FREQ */
2622  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
2623  volatile uint32_t TIMING_H; /* TIMING_H */
2624  volatile uint32_t TIMING_V; /* TIMING_V */
2625  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
2626  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
2627  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
2628  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
2629  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
2630  volatile uint32_t SAFETY_ATTRIBUTES[4U]; /* SAFETY_ATTRIBUTES 0..3 */
2631  volatile uint8_t Resv_144[16];
2632  volatile uint32_t SAFETY_CAPT_SIGNATURE[4U]; /* SAFETY_CAPT_SIGNATURE 0..3 */
2633  volatile uint8_t Resv_176[16];
2634  volatile uint32_t SAFETY_POSITION[4U]; /* SAFETY_POSITION 0..3 */
2635  volatile uint8_t Resv_208[16];
2636  volatile uint32_t SAFETY_REF_SIGNATURE[4U]; /* SAFETY_REF_SIGNATURE 0..3 */
2637  volatile uint8_t Resv_240[16];
2638  volatile uint32_t SAFETY_SIZE[4U]; /* SAFETY_SIZE 0..3 */
2639  volatile uint8_t Resv_272[16];
2640  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
2641  volatile uint8_t Resv_288[12];
2642  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
2643  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
2644  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
2645  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
2646  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
2647  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
2648  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
2649  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
2650  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
2651  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
2652  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
2653  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
2654  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
2655  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
2656  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
2657  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
2658  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
2659  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
2660  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
2661 } CSL_dss_vp1Regs;
2662 
2663 
2664 /**************************************************************************
2665 * Register Macros
2666 **************************************************************************/
2667 
2668 #define CSL_DSS_VP1_CONFIG (0x00000000U)
2669 #define CSL_DSS_VP1_CONTROL (0x00000004U)
2670 #define CSL_DSS_VP1_CSC_COEF0 (0x00000008U)
2671 #define CSL_DSS_VP1_CSC_COEF1 (0x0000000CU)
2672 #define CSL_DSS_VP1_CSC_COEF2 (0x00000010U)
2673 #define CSL_DSS_VP1_DATA_CYCLE_0 (0x00000014U)
2674 #define CSL_DSS_VP1_DATA_CYCLE_1 (0x00000018U)
2675 #define CSL_DSS_VP1_DATA_CYCLE_2 (0x0000001CU)
2676 #define CSL_DSS_VP1_LINE_NUMBER (0x00000044U)
2677 #define CSL_DSS_VP1_POL_FREQ (0x0000004CU)
2678 #define CSL_DSS_VP1_SIZE_SCREEN (0x00000050U)
2679 #define CSL_DSS_VP1_TIMING_H (0x00000054U)
2680 #define CSL_DSS_VP1_TIMING_V (0x00000058U)
2681 #define CSL_DSS_VP1_CSC_COEF3 (0x0000005CU)
2682 #define CSL_DSS_VP1_CSC_COEF4 (0x00000060U)
2683 #define CSL_DSS_VP1_CSC_COEF5 (0x00000064U)
2684 #define CSL_DSS_VP1_CSC_COEF6 (0x00000068U)
2685 #define CSL_DSS_VP1_CSC_COEF7 (0x0000006CU)
2686 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
2687 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
2688 #define CSL_DSS_VP1_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
2689 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
2690 #define CSL_DSS_VP1_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
2691 #define CSL_DSS_VP1_SAFETY_LFSR_SEED (0x00000110U)
2692 #define CSL_DSS_VP1_GAMMA_TABLE_0 (0x00000120U)
2693 #define CSL_DSS_VP1_GAMMA_TABLE_1 (0x00000124U)
2694 #define CSL_DSS_VP1_GAMMA_TABLE_2 (0x00000128U)
2695 #define CSL_DSS_VP1_GAMMA_TABLE_3 (0x0000012CU)
2696 #define CSL_DSS_VP1_GAMMA_TABLE_4 (0x00000130U)
2697 #define CSL_DSS_VP1_GAMMA_TABLE_5 (0x00000134U)
2698 #define CSL_DSS_VP1_GAMMA_TABLE_6 (0x00000138U)
2699 #define CSL_DSS_VP1_GAMMA_TABLE_7 (0x0000013CU)
2700 #define CSL_DSS_VP1_GAMMA_TABLE_8 (0x00000140U)
2701 #define CSL_DSS_VP1_GAMMA_TABLE_9 (0x00000144U)
2702 #define CSL_DSS_VP1_GAMMA_TABLE_10 (0x00000148U)
2703 #define CSL_DSS_VP1_GAMMA_TABLE_11 (0x0000014CU)
2704 #define CSL_DSS_VP1_GAMMA_TABLE_12 (0x00000150U)
2705 #define CSL_DSS_VP1_GAMMA_TABLE_13 (0x00000154U)
2706 #define CSL_DSS_VP1_GAMMA_TABLE_14 (0x00000158U)
2707 #define CSL_DSS_VP1_GAMMA_TABLE_15 (0x0000015CU)
2708 #define CSL_DSS_VP1_DSS_OLDI_CFG (0x00000160U)
2709 #define CSL_DSS_VP1_DSS_OLDI_STATUS (0x00000164U)
2710 #define CSL_DSS_VP1_DSS_OLDI_LB (0x00000168U)
2711 
2712 /**************************************************************************
2713 * Field Definition Macros
2714 **************************************************************************/
2715 
2716 
2717 /* CONFIG */
2718 
2719 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MASK (0x00000001U)
2720 #define CSL_DSS_VP1_CONFIG_PIXELGATED_SHIFT (0x00000000U)
2721 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MAX (0x00000001U)
2722 
2723 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
2724 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
2725 
2726 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
2727 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
2728 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
2729 
2730 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
2731 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
2732 
2733 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MASK (0x00000004U)
2734 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
2735 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MAX (0x00000001U)
2736 
2737 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
2738 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
2739 
2740 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MASK (0x00000008U)
2741 #define CSL_DSS_VP1_CONFIG_HDMIMODE_SHIFT (0x00000003U)
2742 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MAX (0x00000001U)
2743 
2744 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
2745 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
2746 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
2747 
2748 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
2749 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
2750 
2751 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
2752 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
2753 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
2754 
2755 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
2756 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
2757 
2758 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MASK (0x00000040U)
2759 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
2760 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MAX (0x00000001U)
2761 
2762 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
2763 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
2764 
2765 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MASK (0x00000080U)
2766 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
2767 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MAX (0x00000001U)
2768 
2769 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
2770 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
2771 
2772 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
2773 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
2774 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
2775 
2776 #define CSL_DSS_VP1_CONFIG_RESERVED1_MASK (0x00007E00U)
2777 #define CSL_DSS_VP1_CONFIG_RESERVED1_SHIFT (0x00000009U)
2778 #define CSL_DSS_VP1_CONFIG_RESERVED1_MAX (0x0000003FU)
2779 
2780 #define CSL_DSS_VP1_CONFIG_CPR_MASK (0x00008000U)
2781 #define CSL_DSS_VP1_CONFIG_CPR_SHIFT (0x0000000FU)
2782 #define CSL_DSS_VP1_CONFIG_CPR_MAX (0x00000001U)
2783 
2784 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
2785 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
2786 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
2787 
2788 #define CSL_DSS_VP1_CONFIG_RESERVED2_MASK (0x000E0000U)
2789 #define CSL_DSS_VP1_CONFIG_RESERVED2_SHIFT (0x00000011U)
2790 #define CSL_DSS_VP1_CONFIG_RESERVED2_MAX (0x00000007U)
2791 
2792 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MASK (0x00100000U)
2793 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
2794 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MAX (0x00000001U)
2795 
2796 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
2797 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
2798 
2799 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MASK (0x00200000U)
2800 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
2801 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MAX (0x00000001U)
2802 
2803 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
2804 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
2805 
2806 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
2807 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
2808 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
2809 
2810 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
2811 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
2812 
2813 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MASK (0x00800000U)
2814 #define CSL_DSS_VP1_CONFIG_FIDFIRST_SHIFT (0x00000017U)
2815 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MAX (0x00000001U)
2816 
2817 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
2818 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD (0x1U)
2819 
2820 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
2821 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
2822 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
2823 
2824 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
2825 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
2826 
2827 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MASK (0x02000000U)
2828 #define CSL_DSS_VP1_CONFIG_FULLRANGE_SHIFT (0x00000019U)
2829 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MAX (0x00000001U)
2830 
2831 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
2832 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
2833 
2834 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MASK (0x04000000U)
2835 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
2836 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MAX (0x00000001U)
2837 
2838 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
2839 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
2840 
2841 #define CSL_DSS_VP1_CONFIG_RESERVED3_MASK (0xF8000000U)
2842 #define CSL_DSS_VP1_CONFIG_RESERVED3_SHIFT (0x0000001BU)
2843 #define CSL_DSS_VP1_CONFIG_RESERVED3_MAX (0x0000001FU)
2844 
2845 
2846 /* CONTROL */
2847 
2848 #define CSL_DSS_VP1_CONTROL_ENABLE_MASK (0x00000001U)
2849 #define CSL_DSS_VP1_CONTROL_ENABLE_SHIFT (0x00000000U)
2850 #define CSL_DSS_VP1_CONTROL_ENABLE_MAX (0x00000001U)
2851 
2852 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
2853 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
2854 
2855 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
2856 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
2857 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
2858 
2859 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
2860 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
2861 
2862 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MASK (0x00000004U)
2863 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
2864 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MAX (0x00000001U)
2865 
2866 #define CSL_DSS_VP1_CONTROL_STN_MASK (0x00000008U)
2867 #define CSL_DSS_VP1_CONTROL_STN_SHIFT (0x00000003U)
2868 #define CSL_DSS_VP1_CONTROL_STN_MAX (0x00000001U)
2869 
2870 #define CSL_DSS_VP1_CONTROL_M8B_MASK (0x00000010U)
2871 #define CSL_DSS_VP1_CONTROL_M8B_SHIFT (0x00000004U)
2872 #define CSL_DSS_VP1_CONTROL_M8B_MAX (0x00000001U)
2873 
2874 #define CSL_DSS_VP1_CONTROL_GOBIT_MASK (0x00000020U)
2875 #define CSL_DSS_VP1_CONTROL_GOBIT_SHIFT (0x00000005U)
2876 #define CSL_DSS_VP1_CONTROL_GOBIT_MAX (0x00000001U)
2877 
2878 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_HFUISR (0x0U)
2879 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_UFPSR (0x1U)
2880 
2881 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MASK (0x00000040U)
2882 #define CSL_DSS_VP1_CONTROL_DPIENABLE_SHIFT (0x00000006U)
2883 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MAX (0x00000001U)
2884 
2885 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
2886 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
2887 
2888 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MASK (0x00000080U)
2889 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
2890 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MAX (0x00000001U)
2891 
2892 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
2893 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
2894 
2895 #define CSL_DSS_VP1_CONTROL_DATALINES_MASK (0x00000700U)
2896 #define CSL_DSS_VP1_CONTROL_DATALINES_SHIFT (0x00000008U)
2897 #define CSL_DSS_VP1_CONTROL_DATALINES_MAX (0x00000007U)
2898 
2899 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
2900 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
2901 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
2902 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
2903 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
2904 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
2905 
2906 #define CSL_DSS_VP1_CONTROL_STALLMODE_MASK (0x00000800U)
2907 #define CSL_DSS_VP1_CONTROL_STALLMODE_SHIFT (0x0000000BU)
2908 #define CSL_DSS_VP1_CONTROL_STALLMODE_MAX (0x00000001U)
2909 
2910 #define CSL_DSS_VP1_CONTROL_RESERVED6_MASK (0x00001000U)
2911 #define CSL_DSS_VP1_CONTROL_RESERVED6_SHIFT (0x0000000CU)
2912 #define CSL_DSS_VP1_CONTROL_RESERVED6_MAX (0x00000001U)
2913 
2914 #define CSL_DSS_VP1_CONTROL_RESERVED3_MASK (0x00002000U)
2915 #define CSL_DSS_VP1_CONTROL_RESERVED3_SHIFT (0x0000000DU)
2916 #define CSL_DSS_VP1_CONTROL_RESERVED3_MAX (0x00000001U)
2917 
2918 #define CSL_DSS_VP1_CONTROL_HT_MASK (0x0001C000U)
2919 #define CSL_DSS_VP1_CONTROL_HT_SHIFT (0x0000000EU)
2920 #define CSL_DSS_VP1_CONTROL_HT_MAX (0x00000007U)
2921 
2922 #define CSL_DSS_VP1_CONTROL_RESERVED1_MASK (0x000E0000U)
2923 #define CSL_DSS_VP1_CONTROL_RESERVED1_SHIFT (0x00000011U)
2924 #define CSL_DSS_VP1_CONTROL_RESERVED1_MAX (0x00000007U)
2925 
2926 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MASK (0x00100000U)
2927 #define CSL_DSS_VP1_CONTROL_TDMENABLE_SHIFT (0x00000014U)
2928 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MAX (0x00000001U)
2929 
2930 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
2931 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
2932 
2933 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
2934 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
2935 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
2936 
2937 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
2938 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
2939 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
2940 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
2941 
2942 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
2943 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
2944 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
2945 
2946 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
2947 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
2948 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
2949 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
2950 
2951 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
2952 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
2953 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
2954 
2955 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
2956 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
2957 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
2958 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
2959 
2960 #define CSL_DSS_VP1_CONTROL_RESERVED_MASK (0x38000000U)
2961 #define CSL_DSS_VP1_CONTROL_RESERVED_SHIFT (0x0000001BU)
2962 #define CSL_DSS_VP1_CONTROL_RESERVED_MAX (0x00000007U)
2963 
2964 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
2965 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
2966 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
2967 
2968 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
2969 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
2970 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
2971 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
2972 
2973 
2974 /* CSC_COEF0 */
2975 
2976 #define CSL_DSS_VP1_CSC_COEF0_C00_MASK (0x000007FFU)
2977 #define CSL_DSS_VP1_CSC_COEF0_C00_SHIFT (0x00000000U)
2978 #define CSL_DSS_VP1_CSC_COEF0_C00_MAX (0x000007FFU)
2979 
2980 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
2981 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
2982 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
2983 
2984 #define CSL_DSS_VP1_CSC_COEF0_C01_MASK (0x07FF0000U)
2985 #define CSL_DSS_VP1_CSC_COEF0_C01_SHIFT (0x00000010U)
2986 #define CSL_DSS_VP1_CSC_COEF0_C01_MAX (0x000007FFU)
2987 
2988 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
2989 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
2990 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
2991 
2992 
2993 /* CSC_COEF1 */
2994 
2995 #define CSL_DSS_VP1_CSC_COEF1_C02_MASK (0x000007FFU)
2996 #define CSL_DSS_VP1_CSC_COEF1_C02_SHIFT (0x00000000U)
2997 #define CSL_DSS_VP1_CSC_COEF1_C02_MAX (0x000007FFU)
2998 
2999 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
3000 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
3001 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
3002 
3003 #define CSL_DSS_VP1_CSC_COEF1_C10_MASK (0x07FF0000U)
3004 #define CSL_DSS_VP1_CSC_COEF1_C10_SHIFT (0x00000010U)
3005 #define CSL_DSS_VP1_CSC_COEF1_C10_MAX (0x000007FFU)
3006 
3007 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
3008 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
3009 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
3010 
3011 
3012 /* CSC_COEF2 */
3013 
3014 #define CSL_DSS_VP1_CSC_COEF2_C11_MASK (0x000007FFU)
3015 #define CSL_DSS_VP1_CSC_COEF2_C11_SHIFT (0x00000000U)
3016 #define CSL_DSS_VP1_CSC_COEF2_C11_MAX (0x000007FFU)
3017 
3018 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
3019 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
3020 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
3021 
3022 #define CSL_DSS_VP1_CSC_COEF2_C12_MASK (0x07FF0000U)
3023 #define CSL_DSS_VP1_CSC_COEF2_C12_SHIFT (0x00000010U)
3024 #define CSL_DSS_VP1_CSC_COEF2_C12_MAX (0x000007FFU)
3025 
3026 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
3027 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
3028 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
3029 
3030 
3031 /* DATA_CYCLE_0 */
3032 
3033 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
3034 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
3035 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
3036 
3037 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
3038 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
3039 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
3040 
3041 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
3042 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
3043 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
3044 
3045 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
3046 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
3047 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
3048 
3049 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
3050 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
3051 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
3052 
3053 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
3054 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
3055 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
3056 
3057 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
3058 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
3059 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
3060 
3061 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
3062 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
3063 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
3064 
3065 
3066 /* DATA_CYCLE_1 */
3067 
3068 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
3069 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
3070 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
3071 
3072 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
3073 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
3074 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
3075 
3076 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
3077 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
3078 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
3079 
3080 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
3081 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
3082 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
3083 
3084 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
3085 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
3086 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
3087 
3088 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
3089 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
3090 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
3091 
3092 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
3093 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
3094 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
3095 
3096 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
3097 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
3098 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
3099 
3100 
3101 /* DATA_CYCLE_2 */
3102 
3103 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
3104 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
3105 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
3106 
3107 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
3108 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
3109 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
3110 
3111 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
3112 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
3113 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
3114 
3115 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
3116 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
3117 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
3118 
3119 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
3120 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
3121 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
3122 
3123 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
3124 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
3125 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
3126 
3127 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
3128 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
3129 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
3130 
3131 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
3132 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
3133 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
3134 
3135 
3136 /* LINE_NUMBER */
3137 
3138 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MASK (0x00000FFFU)
3139 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
3140 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MAX (0x00000FFFU)
3141 
3142 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MASK (0xFFFFF000U)
3143 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_SHIFT (0x0000000CU)
3144 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MAX (0x000FFFFFU)
3145 
3146 
3147 /* POL_FREQ */
3148 
3149 #define CSL_DSS_VP1_POL_FREQ_ACB_MASK (0x000000FFU)
3150 #define CSL_DSS_VP1_POL_FREQ_ACB_SHIFT (0x00000000U)
3151 #define CSL_DSS_VP1_POL_FREQ_ACB_MAX (0x000000FFU)
3152 
3153 #define CSL_DSS_VP1_POL_FREQ_ACBI_MASK (0x00000F00U)
3154 #define CSL_DSS_VP1_POL_FREQ_ACBI_SHIFT (0x00000008U)
3155 #define CSL_DSS_VP1_POL_FREQ_ACBI_MAX (0x0000000FU)
3156 
3157 #define CSL_DSS_VP1_POL_FREQ_IVS_MASK (0x00001000U)
3158 #define CSL_DSS_VP1_POL_FREQ_IVS_SHIFT (0x0000000CU)
3159 #define CSL_DSS_VP1_POL_FREQ_IVS_MAX (0x00000001U)
3160 
3161 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
3162 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
3163 
3164 #define CSL_DSS_VP1_POL_FREQ_IHS_MASK (0x00002000U)
3165 #define CSL_DSS_VP1_POL_FREQ_IHS_SHIFT (0x0000000DU)
3166 #define CSL_DSS_VP1_POL_FREQ_IHS_MAX (0x00000001U)
3167 
3168 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
3169 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
3170 
3171 #define CSL_DSS_VP1_POL_FREQ_IPC_MASK (0x00004000U)
3172 #define CSL_DSS_VP1_POL_FREQ_IPC_SHIFT (0x0000000EU)
3173 #define CSL_DSS_VP1_POL_FREQ_IPC_MAX (0x00000001U)
3174 
3175 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DRPCK (0x0U)
3176 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DFPCK (0x1U)
3177 
3178 #define CSL_DSS_VP1_POL_FREQ_IEO_MASK (0x00008000U)
3179 #define CSL_DSS_VP1_POL_FREQ_IEO_SHIFT (0x0000000FU)
3180 #define CSL_DSS_VP1_POL_FREQ_IEO_MAX (0x00000001U)
3181 
3182 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
3183 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
3184 
3185 #define CSL_DSS_VP1_POL_FREQ_RF_MASK (0x00010000U)
3186 #define CSL_DSS_VP1_POL_FREQ_RF_SHIFT (0x00000010U)
3187 #define CSL_DSS_VP1_POL_FREQ_RF_MAX (0x00000001U)
3188 
3189 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
3190 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
3191 
3192 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MASK (0x00020000U)
3193 #define CSL_DSS_VP1_POL_FREQ_ONOFF_SHIFT (0x00000011U)
3194 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MAX (0x00000001U)
3195 
3196 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
3197 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
3198 
3199 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MASK (0x00040000U)
3200 #define CSL_DSS_VP1_POL_FREQ_ALIGN_SHIFT (0x00000012U)
3201 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MAX (0x00000001U)
3202 
3203 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
3204 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
3205 
3206 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MASK (0xFFF80000U)
3207 #define CSL_DSS_VP1_POL_FREQ_RESERVED_SHIFT (0x00000013U)
3208 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MAX (0x00001FFFU)
3209 
3210 
3211 /* SIZE_SCREEN */
3212 
3213 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MASK (0x00000FFFU)
3214 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
3215 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MAX (0x00000FFFU)
3216 
3217 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_MASK (0x00003000U)
3218 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_SHIFT (0x0000000CU)
3219 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_MAX (0x00000003U)
3220 
3221 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
3222 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
3223 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
3224 
3225 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
3226 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
3227 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
3228 
3229 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MASK (0x0FFF0000U)
3230 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
3231 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MAX (0x00000FFFU)
3232 
3233 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_MASK (0xF0000000U)
3234 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_SHIFT (0x0000001CU)
3235 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_MAX (0x0000000FU)
3236 
3237 
3238 /* TIMING_H */
3239 
3240 #define CSL_DSS_VP1_TIMING_H_HSW_MASK (0x000000FFU)
3241 #define CSL_DSS_VP1_TIMING_H_HSW_SHIFT (0x00000000U)
3242 #define CSL_DSS_VP1_TIMING_H_HSW_MAX (0x000000FFU)
3243 
3244 #define CSL_DSS_VP1_TIMING_H_HFP_MASK (0x000FFF00U)
3245 #define CSL_DSS_VP1_TIMING_H_HFP_SHIFT (0x00000008U)
3246 #define CSL_DSS_VP1_TIMING_H_HFP_MAX (0x00000FFFU)
3247 
3248 #define CSL_DSS_VP1_TIMING_H_HBP_MASK (0xFFF00000U)
3249 #define CSL_DSS_VP1_TIMING_H_HBP_SHIFT (0x00000014U)
3250 #define CSL_DSS_VP1_TIMING_H_HBP_MAX (0x00000FFFU)
3251 
3252 
3253 /* TIMING_V */
3254 
3255 #define CSL_DSS_VP1_TIMING_V_VSW_MASK (0x000000FFU)
3256 #define CSL_DSS_VP1_TIMING_V_VSW_SHIFT (0x00000000U)
3257 #define CSL_DSS_VP1_TIMING_V_VSW_MAX (0x000000FFU)
3258 
3259 #define CSL_DSS_VP1_TIMING_V_VFP_MASK (0x000FFF00U)
3260 #define CSL_DSS_VP1_TIMING_V_VFP_SHIFT (0x00000008U)
3261 #define CSL_DSS_VP1_TIMING_V_VFP_MAX (0x00000FFFU)
3262 
3263 #define CSL_DSS_VP1_TIMING_V_VBP_MASK (0xFFF00000U)
3264 #define CSL_DSS_VP1_TIMING_V_VBP_SHIFT (0x00000014U)
3265 #define CSL_DSS_VP1_TIMING_V_VBP_MAX (0x00000FFFU)
3266 
3267 
3268 /* CSC_COEF3 */
3269 
3270 #define CSL_DSS_VP1_CSC_COEF3_C20_MASK (0x000007FFU)
3271 #define CSL_DSS_VP1_CSC_COEF3_C20_SHIFT (0x00000000U)
3272 #define CSL_DSS_VP1_CSC_COEF3_C20_MAX (0x000007FFU)
3273 
3274 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
3275 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
3276 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
3277 
3278 #define CSL_DSS_VP1_CSC_COEF3_C21_MASK (0x07FF0000U)
3279 #define CSL_DSS_VP1_CSC_COEF3_C21_SHIFT (0x00000010U)
3280 #define CSL_DSS_VP1_CSC_COEF3_C21_MAX (0x000007FFU)
3281 
3282 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
3283 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
3284 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
3285 
3286 
3287 /* CSC_COEF4 */
3288 
3289 #define CSL_DSS_VP1_CSC_COEF4_C22_MASK (0x000007FFU)
3290 #define CSL_DSS_VP1_CSC_COEF4_C22_SHIFT (0x00000000U)
3291 #define CSL_DSS_VP1_CSC_COEF4_C22_MAX (0x000007FFU)
3292 
3293 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
3294 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
3295 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
3296 
3297 
3298 /* CSC_COEF5 */
3299 
3300 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MASK (0x00000007U)
3301 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
3302 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MAX (0x00000007U)
3303 
3304 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
3305 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
3306 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
3307 
3308 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
3309 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
3310 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
3311 
3312 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
3313 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
3314 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
3315 
3316 
3317 /* CSC_COEF6 */
3318 
3319 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MASK (0x00000007U)
3320 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
3321 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MAX (0x00000007U)
3322 
3323 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
3324 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
3325 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
3326 
3327 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
3328 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
3329 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
3330 
3331 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
3332 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
3333 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
3334 
3335 
3336 /* CSC_COEF7 */
3337 
3338 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MASK (0x00000007U)
3339 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
3340 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MAX (0x00000007U)
3341 
3342 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
3343 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
3344 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
3345 
3346 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
3347 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
3348 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
3349 
3350 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
3351 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
3352 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
3353 
3354 /* SAFETY_ATTRIBUTES */
3355 
3356 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
3357 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
3358 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
3359 
3360 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
3361 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
3362 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
3363 
3364 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
3365 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
3366 
3367 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
3368 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
3369 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
3370 
3371 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
3372 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
3373 
3374 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
3375 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
3376 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
3377 
3378 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
3379 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
3380 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
3381 
3382 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
3383 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
3384 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
3385 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
3386 
3387 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
3388 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
3389 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
3390 
3391 /* SAFETY_CAPT_SIGNATURE */
3392 
3393 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
3394 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
3395 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
3396 
3397 /* SAFETY_POSITION */
3398 
3399 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
3400 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
3401 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
3402 
3403 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
3404 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
3405 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
3406 
3407 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
3408 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
3409 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
3410 
3411 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
3412 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
3413 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
3414 
3415 /* SAFETY_REF_SIGNATURE */
3416 
3417 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
3418 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
3419 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
3420 
3421 /* SAFETY_SIZE */
3422 
3423 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
3424 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
3425 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
3426 
3427 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
3428 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
3429 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
3430 
3431 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
3432 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
3433 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
3434 
3435 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
3436 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
3437 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
3438 
3439 /* SAFETY_LFSR_SEED */
3440 
3441 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
3442 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
3443 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
3444 
3445 
3446 /* GAMMA_TABLE_0 */
3447 
3448 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MASK (0x000000FFU)
3449 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
3450 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MAX (0x000000FFU)
3451 
3452 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MASK (0x0000FF00U)
3453 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_SHIFT (0x00000008U)
3454 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MAX (0x000000FFU)
3455 
3456 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MASK (0x00FF0000U)
3457 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000010U)
3458 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MAX (0x000000FFU)
3459 
3460 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MASK (0xFF000000U)
3461 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_SHIFT (0x00000018U)
3462 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MAX (0x000000FFU)
3463 
3464 
3465 /* GAMMA_TABLE_1 */
3466 
3467 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MASK (0x000000FFU)
3468 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
3469 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MAX (0x000000FFU)
3470 
3471 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MASK (0x0000FF00U)
3472 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_SHIFT (0x00000008U)
3473 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MAX (0x000000FFU)
3474 
3475 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MASK (0x00FF0000U)
3476 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000010U)
3477 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MAX (0x000000FFU)
3478 
3479 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MASK (0xFF000000U)
3480 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_SHIFT (0x00000018U)
3481 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MAX (0x000000FFU)
3482 
3483 
3484 /* GAMMA_TABLE_2 */
3485 
3486 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MASK (0x000000FFU)
3487 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
3488 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MAX (0x000000FFU)
3489 
3490 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MASK (0x0000FF00U)
3491 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_SHIFT (0x00000008U)
3492 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MAX (0x000000FFU)
3493 
3494 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MASK (0x00FF0000U)
3495 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000010U)
3496 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MAX (0x000000FFU)
3497 
3498 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MASK (0xFF000000U)
3499 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_SHIFT (0x00000018U)
3500 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MAX (0x000000FFU)
3501 
3502 
3503 /* GAMMA_TABLE_3 */
3504 
3505 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MASK (0x000000FFU)
3506 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
3507 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MAX (0x000000FFU)
3508 
3509 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MASK (0x0000FF00U)
3510 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_SHIFT (0x00000008U)
3511 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MAX (0x000000FFU)
3512 
3513 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MASK (0x00FF0000U)
3514 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000010U)
3515 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MAX (0x000000FFU)
3516 
3517 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MASK (0xFF000000U)
3518 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_SHIFT (0x00000018U)
3519 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MAX (0x000000FFU)
3520 
3521 
3522 /* GAMMA_TABLE_4 */
3523 
3524 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MASK (0x000000FFU)
3525 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
3526 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MAX (0x000000FFU)
3527 
3528 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MASK (0x0000FF00U)
3529 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_SHIFT (0x00000008U)
3530 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MAX (0x000000FFU)
3531 
3532 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MASK (0x00FF0000U)
3533 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000010U)
3534 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MAX (0x000000FFU)
3535 
3536 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MASK (0xFF000000U)
3537 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_SHIFT (0x00000018U)
3538 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MAX (0x000000FFU)
3539 
3540 
3541 /* GAMMA_TABLE_5 */
3542 
3543 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MASK (0x000000FFU)
3544 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
3545 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MAX (0x000000FFU)
3546 
3547 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MASK (0x0000FF00U)
3548 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_SHIFT (0x00000008U)
3549 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MAX (0x000000FFU)
3550 
3551 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MASK (0x00FF0000U)
3552 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000010U)
3553 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MAX (0x000000FFU)
3554 
3555 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MASK (0xFF000000U)
3556 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_SHIFT (0x00000018U)
3557 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MAX (0x000000FFU)
3558 
3559 
3560 /* GAMMA_TABLE_6 */
3561 
3562 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MASK (0x000000FFU)
3563 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
3564 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MAX (0x000000FFU)
3565 
3566 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MASK (0x0000FF00U)
3567 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_SHIFT (0x00000008U)
3568 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MAX (0x000000FFU)
3569 
3570 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MASK (0x00FF0000U)
3571 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000010U)
3572 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MAX (0x000000FFU)
3573 
3574 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MASK (0xFF000000U)
3575 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_SHIFT (0x00000018U)
3576 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MAX (0x000000FFU)
3577 
3578 
3579 /* GAMMA_TABLE_7 */
3580 
3581 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MASK (0x000000FFU)
3582 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
3583 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MAX (0x000000FFU)
3584 
3585 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MASK (0x0000FF00U)
3586 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_SHIFT (0x00000008U)
3587 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MAX (0x000000FFU)
3588 
3589 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MASK (0x00FF0000U)
3590 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000010U)
3591 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MAX (0x000000FFU)
3592 
3593 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MASK (0xFF000000U)
3594 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_SHIFT (0x00000018U)
3595 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MAX (0x000000FFU)
3596 
3597 
3598 /* GAMMA_TABLE_8 */
3599 
3600 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MASK (0x000000FFU)
3601 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
3602 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MAX (0x000000FFU)
3603 
3604 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MASK (0x0000FF00U)
3605 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_SHIFT (0x00000008U)
3606 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MAX (0x000000FFU)
3607 
3608 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MASK (0x00FF0000U)
3609 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000010U)
3610 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MAX (0x000000FFU)
3611 
3612 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MASK (0xFF000000U)
3613 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_SHIFT (0x00000018U)
3614 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MAX (0x000000FFU)
3615 
3616 
3617 /* GAMMA_TABLE_9 */
3618 
3619 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MASK (0x000000FFU)
3620 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
3621 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MAX (0x000000FFU)
3622 
3623 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MASK (0x0000FF00U)
3624 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_SHIFT (0x00000008U)
3625 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MAX (0x000000FFU)
3626 
3627 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MASK (0x00FF0000U)
3628 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000010U)
3629 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MAX (0x000000FFU)
3630 
3631 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MASK (0xFF000000U)
3632 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_SHIFT (0x00000018U)
3633 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MAX (0x000000FFU)
3634 
3635 
3636 /* GAMMA_TABLE_10 */
3637 
3638 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MASK (0x000000FFU)
3639 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
3640 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MAX (0x000000FFU)
3641 
3642 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MASK (0x0000FF00U)
3643 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_SHIFT (0x00000008U)
3644 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MAX (0x000000FFU)
3645 
3646 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MASK (0x00FF0000U)
3647 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000010U)
3648 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MAX (0x000000FFU)
3649 
3650 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MASK (0xFF000000U)
3651 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_SHIFT (0x00000018U)
3652 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MAX (0x000000FFU)
3653 
3654 
3655 /* GAMMA_TABLE_11 */
3656 
3657 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MASK (0x000000FFU)
3658 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
3659 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MAX (0x000000FFU)
3660 
3661 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MASK (0x0000FF00U)
3662 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_SHIFT (0x00000008U)
3663 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MAX (0x000000FFU)
3664 
3665 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MASK (0x00FF0000U)
3666 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000010U)
3667 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MAX (0x000000FFU)
3668 
3669 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MASK (0xFF000000U)
3670 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_SHIFT (0x00000018U)
3671 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MAX (0x000000FFU)
3672 
3673 
3674 /* GAMMA_TABLE_12 */
3675 
3676 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MASK (0x000000FFU)
3677 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
3678 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MAX (0x000000FFU)
3679 
3680 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MASK (0x0000FF00U)
3681 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_SHIFT (0x00000008U)
3682 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MAX (0x000000FFU)
3683 
3684 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MASK (0x00FF0000U)
3685 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000010U)
3686 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MAX (0x000000FFU)
3687 
3688 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MASK (0xFF000000U)
3689 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_SHIFT (0x00000018U)
3690 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MAX (0x000000FFU)
3691 
3692 
3693 /* GAMMA_TABLE_13 */
3694 
3695 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MASK (0x000000FFU)
3696 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
3697 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MAX (0x000000FFU)
3698 
3699 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MASK (0x0000FF00U)
3700 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_SHIFT (0x00000008U)
3701 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MAX (0x000000FFU)
3702 
3703 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MASK (0x00FF0000U)
3704 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000010U)
3705 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MAX (0x000000FFU)
3706 
3707 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MASK (0xFF000000U)
3708 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_SHIFT (0x00000018U)
3709 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MAX (0x000000FFU)
3710 
3711 
3712 /* GAMMA_TABLE_14 */
3713 
3714 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MASK (0x000000FFU)
3715 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
3716 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MAX (0x000000FFU)
3717 
3718 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MASK (0x0000FF00U)
3719 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_SHIFT (0x00000008U)
3720 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MAX (0x000000FFU)
3721 
3722 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MASK (0x00FF0000U)
3723 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000010U)
3724 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MAX (0x000000FFU)
3725 
3726 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MASK (0xFF000000U)
3727 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_SHIFT (0x00000018U)
3728 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MAX (0x000000FFU)
3729 
3730 
3731 /* GAMMA_TABLE_15 */
3732 
3733 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MASK (0x000000FFU)
3734 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
3735 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MAX (0x000000FFU)
3736 
3737 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MASK (0x0000FF00U)
3738 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_SHIFT (0x00000008U)
3739 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MAX (0x000000FFU)
3740 
3741 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MASK (0x00FF0000U)
3742 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000010U)
3743 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MAX (0x000000FFU)
3744 
3745 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MASK (0xFF000000U)
3746 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_SHIFT (0x00000018U)
3747 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MAX (0x000000FFU)
3748 
3749 
3750 /* DSS_OLDI_CFG */
3751 
3752 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_MASK (0x00000001U)
3753 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_SHIFT (0x00000000U)
3754 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_MAX (0x00000001U)
3755 
3756 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_VAL_DISABLED (0x0U)
3757 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_VAL_ENABLED (0x1U)
3758 
3759 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_MASK (0x0000000EU)
3760 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_SHIFT (0x00000001U)
3761 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_MAX (0x00000007U)
3762 
3763 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A (0x0U)
3764 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B (0x1U)
3765 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C (0x2U)
3766 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D (0x4U)
3767 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E (0x5U)
3768 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F (0x6U)
3769 
3770 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_MASK (0x00000010U)
3771 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_SHIFT (0x00000004U)
3772 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_MAX (0x00000001U)
3773 
3774 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_VAL_CHANNEL0 (0x0U)
3775 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_VAL_CHANNEL1 (0x1U)
3776 
3777 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_MASK (0x00000020U)
3778 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_SHIFT (0x00000005U)
3779 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_MAX (0x00000001U)
3780 
3781 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_VAL_SINGLE (0x0U)
3782 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_VAL_DUPLICATE (0x1U)
3783 
3784 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_MASK (0x00000040U)
3785 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_SHIFT (0x00000006U)
3786 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_MAX (0x00000001U)
3787 
3788 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_VAL_MASTER (0x0U)
3789 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_VAL_SLAVE (0x1U)
3790 
3791 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_MASK (0x00000080U)
3792 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_SHIFT (0x00000007U)
3793 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_MAX (0x00000001U)
3794 
3795 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_VAL_HIGH (0x0U)
3796 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_VAL_LOW (0x1U)
3797 
3798 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_MASK (0x00000100U)
3799 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_SHIFT (0x00000008U)
3800 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_MAX (0x00000001U)
3801 
3802 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B (0x0U)
3803 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B (0x1U)
3804 
3805 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_MASK (0x00000200U)
3806 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_SHIFT (0x00000009U)
3807 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_MAX (0x00000001U)
3808 
3809 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_VAL_DISABLE (0x0U)
3810 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_VAL_ENABLE (0x1U)
3811 
3812 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_MASK (0x00000400U)
3813 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_SHIFT (0x0000000AU)
3814 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_MAX (0x00000001U)
3815 
3816 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_MASK (0x00000800U)
3817 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_SHIFT (0x0000000BU)
3818 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_MAX (0x00000001U)
3819 
3820 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE (0x0U)
3821 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE (0x1U)
3822 
3823 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_MASK (0x00001000U)
3824 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_SHIFT (0x0000000CU)
3825 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_MAX (0x00000001U)
3826 
3827 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_VAL_ASSERT (0x0U)
3828 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_VAL_DEASSERT (0x1U)
3829 
3830 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_MASK (0x00002000U)
3831 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_SHIFT (0x0000000DU)
3832 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_MAX (0x00000001U)
3833 
3834 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
3835 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
3836 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
3837 
3838 
3839 /* DSS_OLDI_STATUS */
3840 
3841 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_MASK (0x0000003FU)
3842 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_SHIFT (0x00000000U)
3843 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_MAX (0x0000003FU)
3844 
3845 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_MASK (0x000000C0U)
3846 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_SHIFT (0x00000006U)
3847 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_MAX (0x00000003U)
3848 
3849 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_MASK (0x00000700U)
3850 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_SHIFT (0x00000008U)
3851 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_MAX (0x00000007U)
3852 
3853 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_MASK (0x0000F800U)
3854 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_SHIFT (0x0000000BU)
3855 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_MAX (0x0000001FU)
3856 
3857 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_MASK (0xFFFF0000U)
3858 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_SHIFT (0x00000010U)
3859 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_MAX (0x0000FFFFU)
3860 
3861 
3862 /* DSS_OLDI_LB */
3863 
3864 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_MASK (0x000003FFU)
3865 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_SHIFT (0x00000000U)
3866 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_MAX (0x000003FFU)
3867 
3868 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFC00U)
3869 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_SHIFT (0x0000000AU)
3870 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MAX (0x003FFFFFU)
3871 
3872 
3873 #ifdef __cplusplus
3874 }
3875 #endif
3876 #endif
CSL_dss_vidl1Regs::BA_EXT_0
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:1282
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Definition: cslr_dss.h:812
CSL_dss_vp1Regs::GAMMA_TABLE_3
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CSL_dss_vp1Regs::CONTROL
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CSL_dss_vidl1Regs::CLUT_0
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CSL_dss_vidl1Regs::ATTRIBUTES2
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:1258
CSL_dss_ovr1Regs::TRANS_COLOR_MIN
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:2346
CSL_dss_vp1Regs::GAMMA_TABLE_4
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:2646
CSL_dss_vidl1Regs::GLOBAL_ALPHA
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:1273
CSL_dss_commonRegs::RESERVED_0
volatile uint32_t RESERVED_0
Definition: cslr_dss.h:67
CSL_dss_ovr1Regs::TRANS_COLOR_MIN2
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:2347
CSL_dss_commonRegs::DISPC_DBG_STATUS
volatile uint32_t DISPC_DBG_STATUS
Definition: cslr_dss.h:82
CSL_dss_vidl1Regs::CLUT_12
volatile uint32_t CLUT_12
Definition: cslr_dss.h:1302
CSL_dss_vidl1Regs::CSC_COEF0
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:1265
CSL_dss_commonRegs::DISPC_GLOBAL_OUTPUT_ENABLE
volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE
Definition: cslr_dss.h:78
CSL_dss_ovr1Regs::RESERVED_1
volatile uint32_t RESERVED_1
Definition: cslr_dss.h:2349
CSL_dss_commonRegs::DISPC_IRQSTATUS
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:63
CSL_dss_commonRegs::DISPC_IRQ_EOI
volatile uint32_t DISPC_IRQ_EOI
Definition: cslr_dss.h:61
CSL_dss_vidl1Regs::CLUT_13
volatile uint32_t CLUT_13
Definition: cslr_dss.h:1303
CSL_dss_vp1Regs::CSC_COEF0
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:2612
CSL_dss_vidl1Regs::SAFETY_REF_SIGNATURE
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:1309
CSL_dss_vidl1Regs::CLUT_7
volatile uint32_t CLUT_7
Definition: cslr_dss.h:1297
CSL_dss_vidl1Regs::BA_UV_1
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:1262
CSL_dss_vidl1Regs::SAFETY_CAPT_SIGNATURE
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:1307
CSL_dss_common1Regs::DISPC_IRQSTATUS
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:801
CSL_dss_vp1Regs::GAMMA_TABLE_13
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:2655
CSL_dss_vidl1Regs::BA_0
volatile uint32_t BA_0
Definition: cslr_dss.h:1259
CSL_dss_commonRegs::VP_IRQENABLE_0
volatile uint32_t VP_IRQENABLE_0
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CSL_dss_vidl1Regs::CLUT_3
volatile uint32_t CLUT_3
Definition: cslr_dss.h:1293
CSL_dss_vp1Regs::DSS_OLDI_CFG
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:2658
CSL_dss_vidl1Regs::CSC_COEF3
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:1268
CSL_dss_vp1Regs::GAMMA_TABLE_6
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:2648
CSL_dss_vp1Regs::DSS_OLDI_STATUS
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:2659
CSL_dss_vp1Regs::CSC_COEF2
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:2614
CSL_dss_commonRegs::VID_IRQSTATUS_1
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Definition: cslr_dss.h:71
CSL_dss_vidl1Regs::CLUT_11
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Definition: cslr_dss.h:1301
CSL_dss_vp1Regs::GAMMA_TABLE_15
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Definition: cslr_dss.h:2657
CSL_dss_ovr1Regs::TRANS_COLOR_MAX
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:2344
CSL_dss_vp1Regs::DATA_CYCLE_1
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:2616
CSL_dss_vp1Regs::CSC_COEF1
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:2613
CSL_dss_vp1Regs::SIZE_SCREEN
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Definition: cslr_dss.h:2622
CSL_dss_vp1Regs::TIMING_V
volatile uint32_t TIMING_V
Definition: cslr_dss.h:2624
CSL_dss_vidl1Regs::BUF_SIZE_STATUS
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:1263
CSL_dss_ovr1Regs::RESERVED_3
volatile uint32_t RESERVED_3
Definition: cslr_dss.h:2351
CSL_dss_vp1Regs::GAMMA_TABLE_2
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:2644
CSL_dss_vidl1Regs::CSC_COEF1
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:1266
CSL_dss_vidl1Regs::LUMAKEY
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Definition: cslr_dss.h:1312
CSL_dss_vidl1Regs::BA_1
volatile uint32_t BA_1
Definition: cslr_dss.h:1260
CSL_dss_common1Regs::RESERVED_0
volatile uint32_t RESERVED_0
Definition: cslr_dss.h:805
CSL_dss_ovr1Regs::ATTRIBUTES_0
volatile uint32_t ATTRIBUTES_0
Definition: cslr_dss.h:2348
CSL_dss_commonRegs::DISPC_DBG_CONTROL
volatile uint32_t DISPC_DBG_CONTROL
Definition: cslr_dss.h:81
CSL_dss_commonRegs::RESERVERD_1
volatile uint32_t RESERVERD_1
Definition: cslr_dss.h:70
CSL_dss_vidl1Regs::CLUT_15
volatile uint32_t CLUT_15
Definition: cslr_dss.h:1305
CSL_dss_vp1Regs::CSC_COEF5
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:2627
CSL_dss_vidl1Regs::CSC_COEF6
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:1271
CSL_dss_common1Regs
Definition: cslr_dss.h:797
CSL_dss_vidl1Regs::PIXEL_INC
volatile uint32_t PIXEL_INC
Definition: cslr_dss.h:1277
CSL_dss_common1Regs::DISPC_SECURE
volatile uint32_t DISPC_SECURE
Definition: cslr_dss.h:808
CSL_dss_vidl1Regs::CLUT_14
volatile uint32_t CLUT_14
Definition: cslr_dss.h:1304
CSL_dss_vidl1Regs::BA_UV_0
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:1261
CSL_dss_vp1Regs::GAMMA_TABLE_11
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:2653
CSL_dss_commonRegs::DSS_REVISION
volatile uint32_t DSS_REVISION
Definition: cslr_dss.h:57
CSL_dss_vidl1Regs::PICTURE_SIZE
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:1276
CSL_dss_vidl1Regs::ROW_INC_UV
volatile uint32_t ROW_INC_UV
Definition: cslr_dss.h:1288
CSL_dss_vp1Regs::GAMMA_TABLE_7
volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:2649
CSL_dss_vp1Regs::GAMMA_TABLE_5
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:2647
CSL_dss_vp1Regs::CSC_COEF6
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:2628
CSL_dss_commonRegs::DISPC_IRQENABLE_CLR
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:66
CSL_dss_vidl1Regs::CSC_COEF2
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:1267
CSL_dss_vidl1Regs::SAFETY_POSITION
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:1308
CSL_dss_common1Regs::DISPC_IRQENABLE_SET
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:802
CSL_dss_vidl1Regs::CLUT_10
volatile uint32_t CLUT_10
Definition: cslr_dss.h:1300
CSL_dss_vp1Regs::GAMMA_TABLE_1
volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:2643
CSL_dss_vp1Regs::CSC_COEF3
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:2625
CSL_dss_vidl1Regs::BA_UV_EXT_0
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:1284
CSL_dss_commonRegs::DISPC_GLOBAL_MFLAG_ATTRIBUTE
volatile uint32_t DISPC_GLOBAL_MFLAG_ATTRIBUTE
Definition: cslr_dss.h:77
CSL_dss_vidl1Regs::CLUT_6
volatile uint32_t CLUT_6
Definition: cslr_dss.h:1296
CSL_dss_vidl1Regs::CSC_COEF7
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:1286
CSL_dss_commonRegs::DSS_SYSCONFIG
volatile uint32_t DSS_SYSCONFIG
Definition: cslr_dss.h:58
CSL_dss_commonRegs::DISPC_CLKGATING_DISABLE
volatile uint32_t DISPC_CLKGATING_DISABLE
Definition: cslr_dss.h:83
CSL_dss_commonRegs::DSS_SYSSTATUS
volatile uint32_t DSS_SYSSTATUS
Definition: cslr_dss.h:60
CSL_dss_vp1Regs::SAFETY_LFSR_SEED
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:2640
CSL_dss_vidl1Regs::CLUT_1
volatile uint32_t CLUT_1
Definition: cslr_dss.h:1291
CSL_dss_vp1Regs::CSC_COEF4
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:2626
CSL_dss_vp1Regs::GAMMA_TABLE_9
volatile uint32_t GAMMA_TABLE_9
Definition: cslr_dss.h:2651
CSL_dss_vidl1Regs::MFLAG_THRESHOLD
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:1275
CSL_dss_ovr1Regs::CONFIG
volatile uint32_t CONFIG
Definition: cslr_dss.h:2340
CSL_dss_vidl1Regs::SAFETY_SIZE
volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:1310
CSL_dss_vidl1Regs::CSC_COEF4
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:1269
CSL_dss_vidl1Regs::BUF_THRESHOLD
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:1264
CSL_dss_ovr1Regs::DEFAULT_COLOR
volatile uint32_t DEFAULT_COLOR
Definition: cslr_dss.h:2342
CSL_dss_common1Regs::DISPC_IRQ_EOI
volatile uint32_t DISPC_IRQ_EOI
Definition: cslr_dss.h:799
CSL_dss_vidl1Regs::CSC_COEF5
volatile uint32_t CSC_COEF5
Definition: cslr_dss.h:1270
CSL_dss_vidl1Regs::CLUT_4
volatile uint32_t CLUT_4
Definition: cslr_dss.h:1294
CSL_dss_vp1Regs::GAMMA_TABLE_14
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:2656
CSL_dss_vp1Regs::GAMMA_TABLE_8
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:2650
CSL_dss_ovr1Regs::TRANS_COLOR_MAX2
volatile uint32_t TRANS_COLOR_MAX2
Definition: cslr_dss.h:2345
CSL_dss_vp1Regs::GAMMA_TABLE_12
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:2654
CSL_dss_vidl1Regs::CLUT_5
volatile uint32_t CLUT_5
Definition: cslr_dss.h:1295
CSL_dss_common1Regs::RESERVERD_1
volatile uint32_t RESERVERD_1
Definition: cslr_dss.h:809