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AM62D FreeRTOS SDK
11.02.00
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AM62D FreeRTOS SDK
11.02.00
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This file contains the type definitions and helper macros for the generic_phy Ethernet PHY.
Go to the source code of this file.
Macros | |
| #define | PHY_BMCR (0x00U) |
| Basic Mode Control Register (BMCR) More... | |
| #define | PHY_BMSR (0x01U) |
| Basic Mode Status Register (BMSR) More... | |
| #define | PHY_PHYIDR1 (0x02U) |
| PHY Identifier Register #1 (PHYIDR1) More... | |
| #define | PHY_PHYIDR2 (0x03U) |
| PHY Identifier Register #2 (PHYIDR2) More... | |
| #define | PHY_ANAR (0x04U) |
| Auto-Negotiation Advertisement Register (ANAR) More... | |
| #define | PHY_ANLPAR (0x05U) |
| Auto-Negotiation Link Partner Abilitiy Register (ANLPAR) More... | |
| #define | PHY_ANER (0x06U) |
| Auto-Negotiation Expansion Register (ANER) More... | |
| #define | PHY_ANNPTR (0x07U) |
| Auto-Negotiation NP TX Register (ANNPTR) More... | |
| #define | PHY_ANNPRR (0x08U) |
| Auto-Neg NP RX Register (ANNPRR) More... | |
| #define | PHY_GIGCR (0x09U) |
| 1000BASE-T Control Register (GIGCR) More... | |
| #define | PHY_GIGSR (0x0AU) |
| 1000BASE-T Status Register (GIGSR) More... | |
| #define | PHY_MMD_CR (0x0DU) |
| MMD Access Control Register. More... | |
| #define | PHY_MMD_DR (0x0EU) |
| MMD Access Data Register. More... | |
| #define | PHY_GIGESR (0x0FU) |
| 1000BASE-T Extended Status Register (GIGESR) More... | |
| #define | BMCR_RESET PHY_BIT(15) |
| #define | BMCR_LOOPBACK PHY_BIT(14) |
| #define | BMCR_SPEED100 PHY_BIT(13) |
| #define | BMCR_ANEN PHY_BIT(12) |
| #define | BMCR_PWRDOWN PHY_BIT(11) |
| #define | BMCR_ISOLATE PHY_BIT(10) |
| #define | BMCR_ANRESTART PHY_BIT(9) |
| #define | BMCR_FD PHY_BIT(8) |
| #define | BMCR_SPEED1000 PHY_BIT(6) |
| #define | BMSR_100FD PHY_BIT(14) |
| #define | BMSR_100HD PHY_BIT(13) |
| #define | BMSR_10FD PHY_BIT(12) |
| #define | BMSR_10HD PHY_BIT(11) |
| #define | BMSR_GIGEXTSTS PHY_BIT(8) |
| #define | BMSR_ANCOMPLETE PHY_BIT(5) |
| #define | BMSR_ANCAPABLE PHY_BIT(3) |
| #define | BMSR_LINKSTS PHY_BIT(2) |
| #define | BMSR_EXTCAP PHY_BIT(0) |
| #define | PHYIDR1_OUI_OFFSET (6U) |
| #define | PHYIDR2_OUI_MASK (0xFC00U) |
| #define | PHYIDR2_VMDL_MASK (0x03F0U) |
| #define | PHYIDR2_VREV_MASK (0x000FU) |
| #define | PHYIDR2_OUI_OFFSET (10U) |
| #define | PHYIDR2_VMDL_OFFSET (4U) |
| #define | PHYIDR2_VREV_OFFSET (0U) |
| #define | ANAR_100FD PHY_BIT(8) |
| #define | ANAR_100HD PHY_BIT(7) |
| #define | ANAR_10FD PHY_BIT(6) |
| #define | ANAR_10HD PHY_BIT(5) |
| #define | ANAR_802P3 PHY_BIT(0) |
| #define | ANAR_100 (ANAR_100FD | ANAR_100HD) |
| #define | ANAR_10 (ANAR_10FD | ANAR_10HD) |
| #define | ANLPAR_100FD PHY_BIT(8) |
| #define | ANLPAR_100HD PHY_BIT(7) |
| #define | ANLPAR_10FD PHY_BIT(6) |
| #define | ANLPAR_10HD PHY_BIT(5) |
| #define | ANLPAR_100 (ANLPAR_100FD | ANLPAR_100HD) |
| #define | ANLPAR_10 (ANLPAR_10FD | ANLPAR_10HD) |
| #define | ANER_LPISANABLE PHY_BIT(0) |
| #define | GIGCR_MASTERCFG PHY_BIT(12) |
| #define | GIGCR_MASTEREN PHY_BIT(11) |
| #define | GIGCR_1000FD PHY_BIT(9) |
| #define | GIGCR_1000HD PHY_BIT(8) |
| #define | GIGCR_1000 (GIGCR_1000FD | GIGCR_1000HD) |
| #define | GIGSR_MASTERRES PHY_BIT(14) |
| #define | GIGSR_LOCALSTS PHY_BIT(13) |
| #define | GIGSR_LPARSTS PHY_BIT(12) |
| #define | GIGSR_1000FD PHY_BIT(11) |
| #define | GIGSR_1000HD PHY_BIT(10) |
| #define | GIGSR_1000 (GIGSR_1000FD | GIGSR_1000HD) |
| #define | MMD_CR_ADDR (0x0000U) |
| #define | MMD_CR_DATA_NOPOSTINC (0x4000U) |
| #define | MMD_CR_DATA_POSTINC_RW (0x8000U) |
| #define | MMD_CR_DATA_POSTINC_W (0xC000U) |
| #define | MMD_CR_DEVADDR (0x001FU) |
| #define | GIGESR_1000FD PHY_BIT(13) |
| #define | GIGESR_1000HD PHY_BIT(12) |
| #define | GIGESR_1000 (GIGESR_1000FD | GIGESR_1000HD) |
1.8.20