cslr_soc_defines.h File Reference

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Macros
#define	MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)
#define	CSL_EPWM_PER_CNT   (9U)
	Number of ePWM instances. More...
Core ID's of core or CPUs present on this SOC
#define	CSL_CORE_ID_MCU_R5FSS0_0   (0U)
#define	CSL_CORE_ID_R5FSS0_0   (1U)
#define	CSL_CORE_ID_A53SS0_0   (2U)
#define	CSL_CORE_ID_A53SS0_1   (3U)
#define	CSL_CORE_ID_A53SS1_0   (4U)
#define	CSL_CORE_ID_A53SS1_1   (5U)
#define	CSL_CORE_ID_HSM_M4FSS0_0   (6U)
#define	CSL_CORE_ID_C75SS0_0   (7U)
#define	CSL_CORE_ID_MAX   (8U)
#define	CSL_CORE_ID_INVALID   (0xFFFFU)
R5 Cluster Group IDs
#define	CSL_ARM_R5_CLUSTER_GROUP_ID_0   ((uint32_t) 0x00U)
	R5 Cluster Group ID0. More...
R5 Core IDs
#define	CSL_ARM_R5_CPU_ID_0   ((uint32_t) 0x00U)
	R5 Core ID0. More...

Macro Definition Documentation

MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT   (4352U)

CSL_CORE_ID_MCU_R5FSS0_0

#define CSL_CORE_ID_MCU_R5FSS0_0   (0U)

CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0   (1U)

CSL_CORE_ID_A53SS0_0

#define CSL_CORE_ID_A53SS0_0   (2U)

CSL_CORE_ID_A53SS0_1

#define CSL_CORE_ID_A53SS0_1   (3U)

CSL_CORE_ID_A53SS1_0

#define CSL_CORE_ID_A53SS1_0   (4U)

CSL_CORE_ID_A53SS1_1

#define CSL_CORE_ID_A53SS1_1   (5U)

CSL_CORE_ID_HSM_M4FSS0_0

#define CSL_CORE_ID_HSM_M4FSS0_0   (6U)

CSL_CORE_ID_C75SS0_0

#define CSL_CORE_ID_C75SS0_0   (7U)

CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX   (8U)

CSL_CORE_ID_INVALID

#define CSL_CORE_ID_INVALID   (0xFFFFU)

CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0   ((uint32_t) 0x00U)

R5 Cluster Group ID0.

CSL_ARM_R5_CPU_ID_0

#define CSL_ARM_R5_CPU_ID_0   ((uint32_t) 0x00U)

R5 Core ID0.

CSL_EPWM_PER_CNT

#define CSL_EPWM_PER_CNT   (9U)

Number of ePWM instances.