AM62Ax MCU+ SDK  10.01.00
tisci_rm_ra.h File Reference

Go to the source code of this file.

Data Structures

struct  tisci_msg_rm_ring_cfg_req
 Configures a Navigator Subsystem ring. More...
 
struct  tisci_msg_rm_ring_cfg_resp
 Response to configuring a ring. More...
 
struct  tisci_msg_rm_ring_mon_cfg_req
 Configures a Navigator Subsystem ring monitor. Configures the real-time registers of a Navigator Subsystem ring monitor. The ring monitor index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list. The channelized firewalls covering the ring monitor registers are configured to allow the host read-only access. More...
 
struct  tisci_msg_rm_ring_mon_cfg_resp
 Response to configuring a ring monitor. More...
 

Macros

#define TISCI_MSG_VALUE_RM_RING_ADDR_LO_VALID   (1u << 0u)
 This file contains: More...
 
#define TISCI_MSG_VALUE_RM_RING_ADDR_HI_VALID   (1u << 1u)
 
#define TISCI_MSG_VALUE_RM_RING_COUNT_VALID   (1u << 2u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_VALID   (1u << 3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_VALID   (1u << 4u)
 
#define TISCI_MSG_VALUE_RM_RING_ORDER_ID_VALID   (1u << 5u)
 
#define TISCI_MSG_VALUE_RM_RING_VIRTID_VALID   (1u << 6u)
 
#define TISCI_MSG_VALUE_RM_RING_ASEL_VALID   (1U << 7U)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_RING   (0x0u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_MESSAGE   (0x1u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_CREDENTIALS   (0x2u)
 
#define TISCI_MSG_VALUE_RM_RING_MODE_QM   (0x3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_4B   (0x0u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_8B   (0x1u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_16B   (0x2u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_32B   (0x3u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_64B   (0x4u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_128B   (0x5u)
 
#define TISCI_MSG_VALUE_RM_RING_SIZE_256B   (0x6u)
 
#define TISCI_MSG_VALUE_RM_MON_SOURCE_VALID   (1u << 0U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_VALID   (1u << 1U)
 
#define TISCI_MSG_VALUE_RM_MON_QUEUE_VALID   (1u << 2U)
 
#define TISCI_MSG_VALUE_RM_MON_DATA0_VAL_VALID   (1u << 3U)
 
#define TISCI_MSG_VALUE_RM_MON_DATA1_VAL_VALID   (1u << 4U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_ELEM_CNT   (0U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_HEAD_PKT_SIZE   (1U)
 
#define TISCI_MSG_VALUE_RM_MON_SRC_ACCUM_Q_SIZE   (2U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_DISABLED   (0U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_PUSH_POP   (1U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_THRESHOLD   (2U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_WATERMARK   (3U)
 
#define TISCI_MSG_VALUE_RM_MON_MODE_STARVATION   (4U)
 

Functions

struct tisci_msg_rm_ring_cfg_req __attribute__ ((__packed__))
 

Variables

struct tisci_header hdr
 
uint32_t valid_params
 
uint16_t nav_id
 
uint16_t index
 
uint32_t addr_lo
 
uint32_t addr_hi
 
uint32_t count
 
uint8_t mode
 
uint8_t size
 
uint8_t order_id
 
uint16_t virtid
 
uint8_t asel
 
uint8_t source
 
uint16_t queue
 
uint32_t data0_val
 
uint32_t data1_val
 

Variable Documentation

◆ hdr

struct tisci_header hdr

◆ valid_params

uint32_t valid_params

◆ nav_id

uint16_t nav_id

◆ index

uint16_t index

◆ addr_lo

uint32_t addr_lo

◆ addr_hi

uint32_t addr_hi

◆ count

uint32_t count

◆ mode

uint8_t mode

◆ size

uint8_t size

◆ order_id

uint8_t order_id

◆ virtid

uint16_t virtid

◆ asel

uint8_t asel

◆ source

uint8_t source

◆ queue

uint16_t queue

◆ data0_val

uint32_t data0_val

◆ data1_val

uint32_t data1_val