tisci_rm_irq.h File Reference

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Data Structures
struct	tisci_msg_rm_irq_set_req
	Configures peripherals within the interrupt subsystem according to the valid configuration provided. The following tisci_msg_rm_irq_set_req::valid_params valid bit combinations are allowed: Interrupt Router Mux Configuration - Configures an IR input to output mux connection where the IR input is the src_index and the IR output is the dst_host_irq. Both the src_id and the dst_id must be the device ID of the IR being configured. tisci_msg_rm_irq_set_req::dst_id valid bit == STRUE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_set_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_set_req::vint valid bit == SFALSE tisci_msg_rm_irq_set_req::global_event valid bit == SFALSE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == SFALSE Event to VINT Mapping Only - Configure peripheral OES register and add an event mapping to an IA VINT tisci_msg_rm_irq_set_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_set_req::ia_id valid bit == STRUE tisci_msg_rm_irq_set_req::vint valid bit == STRUE tisci_msg_rm_irq_set_req::global_event valid bit == STRUE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == STRUE OES Register Programming Only - Only programs the OES register of the source. Useful for setting UDMAP trigger events and any other events that are not translated to the interrupt domain: tisci_msg_rm_irq_set_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_set_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_set_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_set_req::vint valid bit == SFALSE tisci_msg_rm_irq_set_req::global_event valid bit == STRUE tisci_msg_rm_irq_set_req::vint_status_bit_index valid bit == SFALSE. More...
struct	tisci_msg_rm_irq_set_resp
	Response to setting a peripheral to processor interrupt. More...
struct	tisci_msg_rm_irq_release_req
	Releases interrupt peripheral resources according to the valid configuration provided. The following tisci_msg_rm_irq_release_req::valid_params valid bit combinations are allowed: Interrupt Router Mux Release - Release an IR input to output mux connection where the IR input is the src_index and the IR output is the dst_host_irq. Both the src_id and the dst_id must be the device ID of the IR being configured. tisci_msg_rm_irq_release_req::dst_id valid bit == STRUE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == STRUE tisci_msg_rm_irq_release_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_release_req::vint valid bit == SFALSE tisci_msg_rm_irq_release_req::global_event valid bit == SFALSE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == SFALSE Event to VINT Unmap Only - Clear only peripheral OES register and event to VINT status bit mapping tisci_msg_rm_irq_release_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_release_req::ia_id valid bit == STRUE tisci_msg_rm_irq_release_req::vint valid bit == STRUE tisci_msg_rm_irq_release_req::global_event valid bit == STRUE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == STRUE OES Register Programming Only - Only clears the OES register of the source. Useful for clearing UDMAP trigger events and any other events that are not translated to the interrupt domain: tisci_msg_rm_irq_release_req::dst_id valid bit == SFALSE tisci_msg_rm_irq_release_req::dst_host_irq valid bit == SFALSE tisci_msg_rm_irq_release_req::ia_id valid bit == SFALSE tisci_msg_rm_irq_release_req::vint valid bit == SFALSE tisci_msg_rm_irq_release_req::global_event valid bit == STRUE tisci_msg_rm_irq_release_req::vint_status_bit_index valid bit == SFALSE. More...
struct	tisci_msg_rm_irq_release_resp
	Response to releasing a peripheral to processor interrupt. More...

Macros
#define	TISCI_MSG_VALUE_RM_DST_ID_VALID   (1u << 0u)
	This file contains: More...
#define	TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID   (1u << 1u)
#define	TISCI_MSG_VALUE_RM_IA_ID_VALID   (1u << 2u)
#define	TISCI_MSG_VALUE_RM_VINT_VALID   (1u << 3u)
#define	TISCI_MSG_VALUE_RM_GLOBAL_EVENT_VALID   (1u << 4u)
#define	TISCI_MSG_VALUE_RM_VINT_STATUS_BIT_INDEX_VALID   (1u << 5u)

Functions
struct tisci_msg_rm_irq_set_req	__attribute__ ((__packed__))

Variables
struct tisci_header	hdr
uint32_t	valid_params
uint16_t	src_id
uint16_t	src_index
uint16_t	dst_id
uint16_t	dst_host_irq
uint16_t	ia_id
uint16_t	vint
uint16_t	global_event
uint8_t	vint_status_bit_index
uint8_t	secondary_host

Variable Documentation

hdr

struct tisci_header hdr

valid_params

uint32_t valid_params

src_id

uint16_t src_id

src_index

uint16_t src_index

dst_id

uint16_t dst_id

dst_host_irq

uint16_t dst_host_irq

ia_id

uint16_t ia_id

vint

uint16_t vint

global_event

uint16_t global_event

vint_status_bit_index

uint8_t vint_status_bit_index

secondary_host

uint8_t secondary_host