AM62Ax MCU+ SDK  10.01.00

Detailed Description

UDMA UTC channel parameters.

Data Fields

uint8_t pauseOnError
 
uint8_t addrType
 
uint8_t chanType
 
uint16_t fetchWordSize
 
uint8_t busPriority
 
uint8_t busQos
 
uint8_t busOrderId
 
uint8_t dmaPriority
 
uint8_t burstSize
 
uint8_t supressTdCqPkt
 

Field Documentation

◆ pauseOnError

uint8_t Udma_ChUtcPrms::pauseOnError

[IN] Bool: When set (UTRUE), pause channel on error

◆ addrType

uint8_t Udma_ChUtcPrms::addrType

[IN] Address type for this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype

◆ chanType

uint8_t Udma_ChUtcPrms::chanType

◆ fetchWordSize

uint16_t Udma_ChUtcPrms::fetchWordSize

[IN] Descriptor/TR Size in 32-bit words

◆ busPriority

uint8_t Udma_ChUtcPrms::busPriority

[IN] 3-bit priority value (0=highest, 7=lowest)

◆ busQos

uint8_t Udma_ChUtcPrms::busQos

[IN] 3-bit qos value (0=highest, 7=lowest)

◆ busOrderId

uint8_t Udma_ChUtcPrms::busOrderId

[IN] 4-bit orderid value

◆ dmaPriority

uint8_t Udma_ChUtcPrms::dmaPriority

[IN] This field selects which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority

◆ burstSize

uint8_t Udma_ChUtcPrms::burstSize

[IN] Specifies the nominal burst size and alignment for data transfers on this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size. Note1: This parameter should be set less than or equal to the FIFO depth parameter set i.e. fifoDepth >= burstSize

Below are the supported burst sizes for various channel types Normal Capacity Channel - 64 or 128 bytes High Capacity Channel - 64, 128 or 256 bytes Ultra High Capacity Channel - 64, 128 or 256 bytes

◆ supressTdCqPkt

uint8_t Udma_ChUtcPrms::supressTdCqPkt

[IN] Bool: Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. UFALSE = TD packet is sent UTRUE = Suppress sending TD packet TODO: Should we allocate tdCq based on this flag?