sciclient_irq_rm.c File Reference

Introduction

File containing the AM62x specific interrupt management data for RM.

Variables
static struct Sciclient_rmIaUsedMapping	rom_usage_DMASS0_INTAGGR_0 [1U]
uint8_t	vint_usage_count_DMSS_AM62_0_INTAGGR_0 [184U] = {0}
static struct Sciclient_rmIaUsedMapping	rom_usage_DMASS1_INTAGGR_0 [1U]
uint8_t	vint_usage_count_DMSS_AM62_1_INTAGGR_0 [8] = {0}
struct Sciclient_rmIaInst	gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
struct Sciclient_rmIrInst	gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_16_31
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_34_37_to_MCU_R5FSS0_CORE0_cpu0_intr_58_61
const struct Sciclient_rmIrqIf	CMP_EVENT_INTROUTER0_outp_38_41_to_HSM0_nvic_51_54
const struct Sciclient_rmIrqIf *const	tisci_if_CMP_EVENT_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CMP_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_0_15
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
const struct Sciclient_rmIrqIf	MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33
const struct Sciclient_rmIrqIf *const	tisci_if_MAIN_GPIOMUX_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MAIN_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_72_75
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf	WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf *const	tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf	TIMESYNC_EVENT_ROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf *const	tisci_if_TIMESYNC_EVENT_ROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMESYNC_EVENT_ROUTER0
const struct Sciclient_rmIrqIf	CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_24_24
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_ROUTER0_in_16_16
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_ROUTER0_in_17_17
const struct Sciclient_rmIrqIf	CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_ROUTER0_in_18_18
const struct Sciclient_rmIrqIf *const	tisci_if_CPSW0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CPSW0
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_32_71
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_209_224
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79
const struct Sciclient_rmIrqIf *const	tisci_if_DMASS0_INTAGGR_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf	TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_0_0
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER0
const struct Sciclient_rmIrqIf	TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_1_1
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER1 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER1
const struct Sciclient_rmIrqIf	TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_2_2
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER2 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER2
const struct Sciclient_rmIrqIf	TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_3_3
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER3 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER3
const struct Sciclient_rmIrqIf	WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_ROUTER0_in_11_11
const struct Sciclient_rmIrqIf *const	tisci_if_WKUP_GTC0 []
static const struct Sciclient_rmIrqNode	tisci_irq_WKUP_GTC0
const struct Sciclient_rmIrqIf	GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
const struct Sciclient_rmIrqIf	GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177
const struct Sciclient_rmIrqIf	GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO0
const struct Sciclient_rmIrqIf	GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161
const struct Sciclient_rmIrqIf	GPIO1_gpio_bank_72_76_to_MAIN_GPIOMUX_INTROUTER0_in_180_184
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO1 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO1
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf *const	tisci_if_MCU_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCU_GPIO0
const struct Sciclient_rmIrqIf	GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26
const struct Sciclient_rmIrqIf *const	tisci_if_GPMC0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPMC0
const struct Sciclient_rmIrqIf	EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_ROUTER0_in_8_8
const struct Sciclient_rmIrqIf *const	tisci_if_EPWM0 []
static const struct Sciclient_rmIrqNode	tisci_irq_EPWM0
const struct Sciclient_rmIrqIf	MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
const struct Sciclient_rmIrqIf *const	tisci_if_MCRC64_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCRC64_0
const struct Sciclient_rmIrqIf	DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
const struct Sciclient_rmIrqIf *const	tisci_if_DEBUGSS0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DEBUGSS0
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_R5FSS0_CORE0_intr_129_132
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_R5FSS0_CORE0_intr_150_150
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_R5FSS0_CORE0_intr_158_160
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160
const struct Sciclient_rmIrqIf	DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_C7X256V0_CLEC_gic_spi_205_208
const struct Sciclient_rmIrqIf *const	tisci_if_DMASS1_INTAGGR_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DMASS1_INTAGGR_0
const struct Sciclient_rmIrqNode *const	gRmIrqTree [RM_IRQ_TREE_MAX]
const uint32_t	gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])

Variable Documentation

rom_usage_DMASS0_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[1U]

static

Initial value:

= {
    {
        .event = 30U,
        .cleared = false,
    },
}

vint_usage_count_DMSS_AM62_0_INTAGGR_0

uint8_t vint_usage_count_DMSS_AM62_0_INTAGGR_0[184U] = {0}

rom_usage_DMASS1_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS1_INTAGGR_0[1U]

static

Initial value:

= {
{
    .event = 5651U,
    .cleared = false,
},
}

vint_usage_count_DMSS_AM62_1_INTAGGR_0

uint8_t vint_usage_count_DMSS_AM62_1_INTAGGR_0[8] = {0}

gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]

Initial value:

=
{
    {
        .dev_id             = TISCI_DEV_DMASS0_INTAGGR_0,
        .imap               = 0x48100000,
        .sevt_offset        = 0u,
        .n_sevt             = 1536u,
        .n_vint             = 184,
        .vint_usage_count   = &vint_usage_count_DMSS_AM62_0_INTAGGR_0[0],
        .v0_b0_evt          = 0,
        .rom_usage = &rom_usage_DMASS0_INTAGGR_0[0U],
        .n_rom_usage = 1,
    },
    {
        .dev_id             = TISCI_DEV_DMASS1_INTAGGR_0,
        .imap               = 0x4e0b0000,
        .sevt_offset        = 0u,
        .n_sevt             = 128u,
        .n_vint             = 8,
        .vint_usage_count   = &vint_usage_count_DMSS_AM62_1_INTAGGR_0[0],
        .v0_b0_evt          = 0,
        .rom_usage = &rom_usage_DMASS1_INTAGGR_0[0U],
        .n_rom_usage = 1,
    }
}

gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]

CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_16_31

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_16_31

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 16,
}

CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 48,
}

CMP_EVENT_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 0,
}

CMP_EVENT_INTROUTER0_outp_34_37_to_MCU_R5FSS0_CORE0_cpu0_intr_58_61

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_34_37_to_MCU_R5FSS0_CORE0_cpu0_intr_58_61

Initial value:

= {
    .lbase = 34,
    .len = 4,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 58,
}

CMP_EVENT_INTROUTER0_outp_38_41_to_HSM0_nvic_51_54

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_38_41_to_HSM0_nvic_51_54

Initial value:

= {
    .lbase = 38,
    .len = 4,
    .rid = TISCI_DEV_HSM0,
    .rbase = 51,
}

tisci_if_CMP_EVENT_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_CMP_EVENT_INTROUTER0[]

Initial value:

= {
    &CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63,
    &CMP_EVENT_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_16_31,
    &CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55,
    &CMP_EVENT_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7,
    &CMP_EVENT_INTROUTER0_outp_34_37_to_MCU_R5FSS0_CORE0_cpu0_intr_58_61,
    &CMP_EVENT_INTROUTER0_outp_38_41_to_HSM0_nvic_51_54,
}

tisci_irq_CMP_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .n_if = 6,
    .p_if = &tisci_if_CMP_EVENT_INTROUTER0[0],
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 32,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_0_15

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_0_15

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 0,
}

MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215

Initial value:

= {
    .lbase = 0,
    .len = 8,
    .rid = TISCI_DEV_HSM0,
    .rbase = 208,
}

MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 16,
}

MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

Initial value:

= {
    .lbase = 22,
    .len = 2,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 24,
}

MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33

Initial value:

= {
    .lbase = 34,
    .len = 2,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 32,
}

tisci_if_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_MAIN_GPIOMUX_INTROUTER0[]

Initial value:

= {
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_0_15,
    &MAIN_GPIOMUX_INTROUTER0_outp_0_7_to_HSM0_nvic_208_215,
    &MAIN_GPIOMUX_INTROUTER0_outp_24_31_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23,
    &MAIN_GPIOMUX_INTROUTER0_outp_22_23_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25,
    &MAIN_GPIOMUX_INTROUTER0_outp_34_35_to_MCU_R5FSS0_CORE0_cpu0_intr_32_33,
}

tisci_irq_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .n_if = 7,
    .p_if = &tisci_if_MAIN_GPIOMUX_INTROUTER0[0],
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 104,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 104,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_72_75

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_72_75

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 72,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107

Initial value:

= {
    .lbase = 4,
    .len = 4,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 104,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81

Initial value:

= {
    .lbase = 4,
    .len = 4,
    .rid = TISCI_DEV_HSM0,
    .rbase = 78,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 88,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 92,
}

WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99

const struct Sciclient_rmIrqIf WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 96,
}

tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0[]

Initial value:

= {
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_72_75,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_R5FSS0_CORE0_cpu0_intr_104_107,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_HSM0_nvic_78_81,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95,
    &WKUP_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99,
}

tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0,
    .n_if = 8,
    .p_if = &tisci_if_WKUP_MCU_GPIOMUX_INTROUTER0[0],
}

TIMESYNC_EVENT_ROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

Initial value:

= {
    .lbase = 0,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 8,
}

TIMESYNC_EVENT_ROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0

Initial value:

= {
    .lbase = 10,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 0,
}

TIMESYNC_EVENT_ROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1

Initial value:

= {
    .lbase = 11,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 1,
}

TIMESYNC_EVENT_ROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2

Initial value:

= {
    .lbase = 12,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 2,
}

TIMESYNC_EVENT_ROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3

Initial value:

= {
    .lbase = 13,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 3,
}

TIMESYNC_EVENT_ROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4

Initial value:

= {
    .lbase = 14,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 4,
}

TIMESYNC_EVENT_ROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5

Initial value:

= {
    .lbase = 15,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 5,
}

TIMESYNC_EVENT_ROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6

Initial value:

= {
    .lbase = 16,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 6,
}

TIMESYNC_EVENT_ROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_ROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7

Initial value:

= {
    .lbase = 17,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 7,
}

tisci_if_TIMESYNC_EVENT_ROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_EVENT_ROUTER0[]

Initial value:

= {
    &TIMESYNC_EVENT_ROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15,
    &TIMESYNC_EVENT_ROUTER0_outl_10_10_to_CPSW0_cpts_hw1_push_0_0,
    &TIMESYNC_EVENT_ROUTER0_outl_11_11_to_CPSW0_cpts_hw2_push_1_1,
    &TIMESYNC_EVENT_ROUTER0_outl_12_12_to_CPSW0_cpts_hw3_push_2_2,
    &TIMESYNC_EVENT_ROUTER0_outl_13_13_to_CPSW0_cpts_hw4_push_3_3,
    &TIMESYNC_EVENT_ROUTER0_outl_14_14_to_CPSW0_cpts_hw5_push_4_4,
    &TIMESYNC_EVENT_ROUTER0_outl_15_15_to_CPSW0_cpts_hw6_push_5_5,
    &TIMESYNC_EVENT_ROUTER0_outl_16_16_to_CPSW0_cpts_hw7_push_6_6,
    &TIMESYNC_EVENT_ROUTER0_outl_17_17_to_CPSW0_cpts_hw8_push_7_7,
}

tisci_irq_TIMESYNC_EVENT_ROUTER0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_ROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .n_if = 9,
    .p_if = &tisci_if_TIMESYNC_EVENT_ROUTER0[0],
}

CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_24_24

const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_24_24

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_CMP_EVENT_INTROUTER0,
    .rbase = 24,
}

CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_ROUTER0_in_16_16

const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_ROUTER0_in_16_16

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 16,
}

CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_ROUTER0_in_17_17

const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_ROUTER0_in_17_17

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 17,
}

CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_ROUTER0_in_18_18

const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_ROUTER0_in_18_18

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 18,
}

tisci_if_CPSW0

const struct Sciclient_rmIrqIf* const tisci_if_CPSW0[]

Initial value:

= {
    &CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_24_24,
    &CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_ROUTER0_in_16_16,
    &CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_ROUTER0_in_17_17,
    &CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_ROUTER0_in_18_18,
}

tisci_irq_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_CPSW0

static

Initial value:

= {
    .id = TISCI_DEV_CPSW0,
    .n_if = 4,
    .p_if = &tisci_if_CPSW0[0],
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

Initial value:

= {
    .lbase = 0,
    .len = 40,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_32_71

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_32_71

Initial value:

= {
    .lbase = 0,
    .len = 40,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 32,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_209_224

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_209_224

Initial value:

= {
    .lbase = 84,
    .len = 16,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 209,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15

Initial value:

= {
    .lbase = 72,
    .len = 8,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95

Initial value:

= {
    .lbase = 40,
    .len = 32,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191

Initial value:

= {
    .lbase = 136,
    .len = 16,
    .rid = TISCI_DEV_HSM0,
    .rbase = 176,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79

Initial value:

= {
    .lbase = 168,
    .len = 16,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 64,
}

tisci_if_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqIf* const tisci_if_DMASS0_INTAGGR_0[]

Initial value:

= {
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_C7X256V0_CLEC_gic_spi_32_71,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_209_224,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_136_151_to_HSM0_nvic_176_191,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_R5FSS0_CORE0_cpu0_intr_64_79,
}

tisci_irq_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0

static

Initial value:

= {
    .id = TISCI_DEV_DMASS0_INTAGGR_0,
    .n_if = 7,
    .p_if = &tisci_if_DMASS0_INTAGGR_0[0],
}

TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_0_0

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_0_0

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 0,
}

tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]

Initial value:

= {
    &TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_0_0,
}

tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMER0,
    .n_if = 1,
    .p_if = &tisci_if_TIMER0[0],
}

TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_1_1

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_1_1

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 1,
}

tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]

Initial value:

= {
    &TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_1_1,
}

tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1

static

Initial value:

= {
    .id = TISCI_DEV_TIMER1,
    .n_if = 1,
    .p_if = &tisci_if_TIMER1[0],
}

TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_2_2

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_2_2

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 2,
}

tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]

Initial value:

= {
    &TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_2_2,
}

tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2

static

Initial value:

= {
    .id = TISCI_DEV_TIMER2,
    .n_if = 1,
    .p_if = &tisci_if_TIMER2[0],
}

TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_3_3

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_3_3

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 3,
}

tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]

Initial value:

= {
    &TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_ROUTER0_in_3_3,
}

tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3

static

Initial value:

= {
    .id = TISCI_DEV_TIMER3,
    .n_if = 1,
    .p_if = &tisci_if_TIMER3[0],
}

WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_ROUTER0_in_11_11

const struct Sciclient_rmIrqIf WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_ROUTER0_in_11_11

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 11,
}

tisci_if_WKUP_GTC0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GTC0[]

Initial value:

= {
    &WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_ROUTER0_in_11_11,
}

tisci_irq_WKUP_GTC0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_GTC0

static

Initial value:

= {
    .id = TISCI_DEV_WKUP_GTC0,
    .n_if = 1,
    .p_if = &tisci_if_WKUP_GTC0[0],
}

GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

Initial value:

= {
    .lbase = 0,
    .len = 90,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177

const struct Sciclient_rmIrqIf GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177

Initial value:

= {
    .lbase = 90,
    .len = 2,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 176,
}

GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195

const struct Sciclient_rmIrqIf GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195

Initial value:

= {
    .lbase = 92,
    .len = 6,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 190,
}

tisci_if_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[]

Initial value:

= {
    &GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89,
    &GPIO0_gpio_90_91_to_MAIN_GPIOMUX_INTROUTER0_in_176_177,
    &GPIO0_gpio_bank_92_97_to_MAIN_GPIOMUX_INTROUTER0_in_190_195,
}

tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_GPIO0,
    .n_if = 3,
    .p_if = &tisci_if_GPIO0[0],
}

GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161

const struct Sciclient_rmIrqIf GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161

Initial value:

= {
    .lbase = 0,
    .len = 72,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 90,
}

GPIO1_gpio_bank_72_76_to_MAIN_GPIOMUX_INTROUTER0_in_180_184

const struct Sciclient_rmIrqIf GPIO1_gpio_bank_72_76_to_MAIN_GPIOMUX_INTROUTER0_in_180_184

Initial value:

= {
    .lbase = 72,
    .len = 5,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 180,
}

tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]

Initial value:

= {
    &GPIO1_gpio_0_71_to_MAIN_GPIOMUX_INTROUTER0_in_90_161,
    &GPIO1_gpio_bank_72_76_to_MAIN_GPIOMUX_INTROUTER0_in_180_184,
}

tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1

static

Initial value:

= {
    .id = TISCI_DEV_GPIO1,
    .n_if = 2,
    .p_if = &tisci_if_GPIO1[0],
}

MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23

Initial value:

= {
    .lbase = 0,
    .len = 24,
    .rid = TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31

Initial value:

= {
    .lbase = 24,
    .len = 2,
    .rid = TISCI_DEV_WKUP_MCU_GPIOMUX_INTROUTER0,
    .rbase = 30,
}

tisci_if_MCU_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[]

Initial value:

= {
    &MCU_GPIO0_gpio_0_23_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_0_23,
    &MCU_GPIO0_gpio_bank_24_25_to_WKUP_MCU_GPIOMUX_INTROUTER0_in_30_31,
}

tisci_irq_MCU_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_MCU_GPIO0,
    .n_if = 2,
    .p_if = &tisci_if_MCU_GPIO0[0],
}

GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26

const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 26,
}

tisci_if_GPMC0

const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[]

Initial value:

= {
    &GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_26_26,
}

tisci_irq_GPMC0

const struct Sciclient_rmIrqNode tisci_irq_GPMC0

static

Initial value:

= {
    .id = TISCI_DEV_GPMC0,
    .n_if = 1,
    .p_if = &tisci_if_GPMC0[0],
}

EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_ROUTER0_in_8_8

const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_ROUTER0_in_8_8

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_ROUTER0,
    .rbase = 8,
}

tisci_if_EPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[]

Initial value:

= {
    &EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_ROUTER0_in_8_8,
}

tisci_irq_EPWM0

const struct Sciclient_rmIrqNode tisci_irq_EPWM0

static

Initial value:

= {
    .id = TISCI_DEV_EPWM0,
    .n_if = 1,
    .p_if = &tisci_if_EPWM0[0],
}

MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31

const struct Sciclient_rmIrqIf MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 28,
}

tisci_if_MCRC64_0

const struct Sciclient_rmIrqIf* const tisci_if_MCRC64_0[]

Initial value:

= {
    &MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31,
}

tisci_irq_MCRC64_0

const struct Sciclient_rmIrqNode tisci_irq_MCRC64_0

static

Initial value:

= {
    .id = TISCI_DEV_MCRC64_0,
    .n_if = 1,
    .p_if = &tisci_if_MCRC64_0[0],
}

DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27

const struct Sciclient_rmIrqIf DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 27,
}

tisci_if_DEBUGSS0

const struct Sciclient_rmIrqIf* const tisci_if_DEBUGSS0[]

Initial value:

= {
    &DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27,
}

tisci_irq_DEBUGSS0

const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0

static

Initial value:

= {
    .id = TISCI_DEV_DEBUGSS0,
    .n_if = 1,
    .p_if = &tisci_if_DEBUGSS0[0],
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244

Initial value:

= {
    .lbase = 0,
    .len = 8,
    .rid = TISCI_DEV_GICSS0,
    .rbase = 237,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_R5FSS0_CORE0_intr_129_132

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_R5FSS0_CORE0_intr_129_132

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 129,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_R5FSS0_CORE0_intr_150_150

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_R5FSS0_CORE0_intr_150_150

Initial value:

= {
    .lbase = 4,
    .len = 1,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 150,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_R5FSS0_CORE0_intr_158_160

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_R5FSS0_CORE0_intr_158_160

Initial value:

= {
    .lbase = 5,
    .len = 3,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 158,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 129,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150

Initial value:

= {
    .lbase = 4,
    .len = 1,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 150,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160

Initial value:

= {
    .lbase = 5,
    .len = 3,
    .rid = TISCI_DEV_MCU_R5FSS0_CORE0,
    .rbase = 158,
}

DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_C7X256V0_CLEC_gic_spi_205_208

const struct Sciclient_rmIrqIf DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_C7X256V0_CLEC_gic_spi_205_208

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 205,
}

tisci_if_DMASS1_INTAGGR_0

const struct Sciclient_rmIrqIf* const tisci_if_DMASS1_INTAGGR_0[]

Initial value:

= {
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_0_7_to_GICSS0_spi_237_244,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_R5FSS0_CORE0_intr_129_132,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_R5FSS0_CORE0_intr_150_150,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_R5FSS0_CORE0_intr_158_160,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_MCU_R5FSS0_CORE0_cpu0_intr_129_132,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_4_4_to_MCU_R5FSS0_CORE0_cpu0_intr_150_150,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_5_7_to_MCU_R5FSS0_CORE0_cpu0_intr_158_160,
    &DMASS1_INTAGGR_0_intaggr_vintr_pend_0_3_to_C7X256V0_CLEC_gic_spi_205_208,
}

tisci_irq_DMASS1_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS1_INTAGGR_0

static

Initial value:

= {
    .id = TISCI_DEV_DMASS1_INTAGGR_0,
    .n_if = 8,
    .p_if = &tisci_if_DMASS1_INTAGGR_0[0],
}

gRmIrqTree

const struct Sciclient_rmIrqNode* const gRmIrqTree[RM_IRQ_TREE_MAX]

Initial value:

= {
    &tisci_irq_CMP_EVENT_INTROUTER0,
    &tisci_irq_MAIN_GPIOMUX_INTROUTER0,
    &tisci_irq_WKUP_MCU_GPIOMUX_INTROUTER0,
    &tisci_irq_TIMESYNC_EVENT_ROUTER0,
    &tisci_irq_CPSW0,
    &tisci_irq_DMASS0_INTAGGR_0,
    &tisci_irq_TIMER0,
    &tisci_irq_TIMER1,
    &tisci_irq_TIMER2,
    &tisci_irq_TIMER3,
    &tisci_irq_WKUP_GTC0,
    &tisci_irq_GPIO0,
    &tisci_irq_GPIO1,
    &tisci_irq_MCU_GPIO0,
    &tisci_irq_GPMC0,
    &tisci_irq_EPWM0,
    &tisci_irq_MCRC64_0,
    &tisci_irq_DEBUGSS0,
    &tisci_irq_DMASS1_INTAGGR_0,
}

gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])