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AM62Ax MCU+ SDK
10.01.00
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AM62Ax MCU+ SDK
10.01.00
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DMSC controls the power management, security and resource management of the device.
Data Structures | |
| struct | tisci_msg_rm_udmap_gcfg_cfg_req |
| Configures a Navigator Subsystem UDMAP global configuration region. Configures the non-real-time registers of a Navigator Subsystem UDMAP global configuration region. The GCFG region being programmed must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment array. Individual fields for registers specified as valid are not checked for correctness. It is the application's responsibility to verify if the register fields are being set according to the device specification. More... | |
| struct | tisci_msg_rm_udmap_gcfg_cfg_resp |
| Response to configuring UDMAP global configuration. More... | |
| struct | tisci_msg_rm_udmap_tx_ch_cfg_req |
| Configures a Navigator Subsystem UDMAP transmit channel. More... | |
| struct | tisci_msg_rm_udmap_tx_ch_cfg_resp |
| Response to configuring a UDMAP transmit channel. More... | |
| struct | tisci_msg_rm_udmap_rx_ch_cfg_req |
| Configures a Navigator Subsystem UDMAP receive channel. More... | |
| struct | tisci_msg_rm_udmap_rx_ch_cfg_resp |
| Response to configuring a UDMAP receive channel. More... | |
| struct | tisci_msg_rm_udmap_flow_cfg_req |
| Configures a Navigator Subsystem UDMAP receive flow. More... | |
| struct | tisci_msg_rm_udmap_flow_cfg_resp |
| Response to configuring a Navigator Subsystem UDMAP receive flow. More... | |
| struct | tisci_msg_rm_udmap_flow_size_thresh_cfg_req |
| Configures a Navigator Subsystem UDMAP receive flow's size threshold fields. More... | |
| struct | tisci_msg_rm_udmap_flow_size_thresh_cfg_resp |
| Response to configuring a Navigator Subsystem UDMAP receive flow's size threshold fields. More... | |
| struct | tisci_msg_rm_udmap_flow_delegate_req |
| Delegates the specified flow to another host for configuration. Only the original owner of the flow, as specified in the RM board configuration resource entries, can delegate an additional host as able to configure the flow. A flow's delegation can be cleared by the original owner of the flow using the clear parameter. More... | |
| struct | tisci_msg_rm_udmap_flow_delegate_resp |
| Response to delegating a flow to another host for configuration. More... | |
Functions | |
| struct tisci_msg_rm_udmap_gcfg_cfg_req | __attribute__ ((__packed__)) |
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID ((uint32_t) 1u << 0u) |
This file contains:
WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!
System Firmware TISCI RM UDMAP Messaging
TISCI Protocol Definitions for UDMAP messages The tx_pause_on_err and rx_pause_on_err parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID ((uint32_t) 1u << 1u) |
The tx_atype and rx_atype parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID ((uint32_t) 1u << 2u) |
The tx_chan_type and rx_chan_type parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID ((uint32_t) 1u << 3u) |
The tx_fetch_size and rx_fetch_size parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID ((uint32_t) 1u << 4u) |
The txcq_qnum and rxcq_qnum parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID ((uint32_t) 1u << 5u) |
The tx_priority and rx_priority parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID ((uint32_t) 1u << 6u) |
The tx_qos and rx_qos parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID ((uint32_t) 1u << 7u) |
The tx_orderid and rx_orderid parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID ((uint32_t) 1u << 8u) |
The tx_sched_priority and rx_sched_priority parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID ((uint32_t) 1u << 14U) |
The tx_burst_size and rx_burst_size parameters are valid for RM UDMAP tx and rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_EXTENDED_CH_TYPE_VALID ((uint32_t) 1u << 16U) |
The extended_ch_type field is valid or not.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED (0u) |
On error or exception the channel will drop current work and move on
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_ENABLED (1u) |
On error or exception the channel will pause and wait for software to investigate and un-pause the channel.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS (0u) |
Pointers are physical addresses configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_INTERMEDIATE (1u) |
Pointers are intermediate addresses requiring intermediate to physical translation before being decoded configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VIRTUAL (2u) |
Pointers are virtual addresses requiring virtual to physical translation before being decoded configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT (3U) |
Used for all non-coherent traffic like accelerator and real-time IP traffic. Configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET (2u) |
Channel performs packet oriented transfers using pass by reference rings configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET_SINGLE_BUF (3u) |
Channel performs packet oriented transfers using pass by reference rings with single buffer packet mode enable configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
NOTE: This type is only valid for UDMAP receive channel configuration
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF (10u) |
Channel performs Third Party DMA transfers using pass by reference rings configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_VAL (11u) |
Channel performs Third Party DMA transfers using pass by value rings configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF (12u) |
Channel performs Third Party Block Copy DMA transfers using pass by reference rings configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_VAL (13u) |
Channel performs Third Party Block Copy DMA transfers using pass by value rings configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH (0u) |
High priority scheduling priority configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH (1u) |
Medium to high priority scheduling priority configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDLOW (2u) |
Medium to low priority scheduling priority configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_LOW (3u) |
Low priority scheduling priority configuration for tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_MAX (127u) |
Maximum value allowed in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_fetch_size and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
| #define TISCI_MSG_VALUE_RM_UDMAP_QNUM_SUPPRESS (0xFFFFu) |
Value used to suppress usage of ring-based UDMAP channel parameters
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_MAX (7u) |
Maximum value allowed in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_priority and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_MAX (7u) |
Maximum value allowed in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_qos and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_MAX (15u) |
Maximum value allowed in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_orderid and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES (1U) |
Burst size of 64 bytes in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES (2U) |
Burst size of 128 bytes in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_256_BYTES (3U) |
Burst size of 256 bytes in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID ((uint32_t) 1U << 9U) |
The tx_filt_einfo parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID ((uint32_t) 1U << 10U) |
The tx_filt_pswords parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID ((uint32_t) 1U << 11U) |
The tx_supr_tdpkt parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID ((uint32_t) 1U << 12U) |
The tx_credit_count parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID ((uint32_t) 1U << 13U) |
The fdepth parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID ((uint32_t) 1U << 15U) |
The tdtype parameter is valid for RM UDMAP tx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED (0u) |
Descriptor extended packet info (if present) will be passed by the DMA controller to the back end application for UDMAP transmit channels.
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_ENABLED (1u) |
Descriptor extended packet info (if present) will be filtered by the DMA controller for UDMAP transmit channels.
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED (0u) |
Descriptor protocol specific words (if present) will be passed by the DMA controller to the back end application for UDMAP transmit channels.
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_ENABLED (1u) |
Descriptor protocol specific words (if present) will be filtered by the DMA controller for UDMAP transmit channels.
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED (0u) |
Do not suppress teardown packet generation by transmit channel
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_ENABLED (1u) |
Suppress teardown packet generation by transmit channel
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_CREDIT_CNT_MAX (7u) |
Maximum value allowed in tisci_msg_rm_udmap_tx_ch_cfg_req::tx_credit_count
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_IMMEDIATE (0U) |
Teardown immediately once all traffic is complete in UDMA tisci_msg_rm_udmap_tx_ch_cfg_req::tx_tdtype
| #define TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_WAIT (1U) |
Wait to teardown until remote peer sends back completion message tisci_msg_rm_udmap_tx_ch_cfg_req::tx_tdtype
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID ((uint32_t) 1u << 9u) |
The flowid_start parameter is valid for RM UDMAP rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID ((uint32_t) 1u << 10u) |
The flowid_cnt parameter is valid for RM UDMAP rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID ((uint32_t) 1u << 11u) |
The rx_ignore_short parameter is valid for RM UDMAP rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID ((uint32_t) 1u << 12u) |
The rx_ignore_long parameter is valid for RM UDMAP rx channel configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION (0u) |
Packets are treated as exceptions and handled appropriately by UDMAP receive channels. Used to configured receive channel short and long packet treatment via tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_IGNORED (1u) |
Packets are ignored by UDMAP receive channels. Used to configured receive channel short and long packet treatment via tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short and tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_CH_FLOW_CNT_NONE (0u) |
Reset value for tisci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt No flow IDs other than the default, statically mapped flow are used by the UDMAP receive channel.
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID ((uint32_t) 1u << 0u) |
The rx_einfo_present parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID ((uint32_t) 1u << 1u) |
The rx_psinfo_present parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID ((uint32_t) 1u << 2u) |
The rx_error_handling parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID ((uint32_t) 1u << 3u) |
The rx_desc_type parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID ((uint32_t) 1u << 4u) |
The rx_sop_offset parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID ((uint32_t) 1u << 5u) |
The rx_dest_qnum parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID ((uint32_t) 1u << 6u) |
The rx_src_tag_hi parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID ((uint32_t) 1u << 7u) |
The rx_src_tag_lo parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID ((uint32_t) 1u << 8u) |
The rx_dest_tag_hi parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID ((uint32_t) 1u << 9u) |
The rx_dest_tag_lo parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID ((uint32_t) 1u << 10u) |
The rx_src_tag_hi_sel parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID ((uint32_t) 1u << 11u) |
The rx_src_tag_lo_sel parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID ((uint32_t) 1u << 12u) |
The rx_dest_tag_hi_sel parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID ((uint32_t) 1u << 13u) |
The rx_dest_tag_lo_sel parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID ((uint32_t) 1u << 14u) |
The rx_fdq0_sz0_qnum parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID ((uint32_t) 1u << 15u) |
The rx_fdq1_qnum parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID ((uint32_t) 1u << 16u) |
The rx_fdq2_qnum parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID ((uint32_t) 1u << 17u) |
The rx_fdq3_qnum parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID ((uint32_t) 1u << 18u) |
The rx_ps_location parameter is valid for RM UDMAP rx flow configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH0_VALID ((uint32_t) 1u << 0u) |
The rx_size_thresh0 parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH1_VALID ((uint32_t) 1u << 1u) |
The rx_size_thresh1 parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH2_VALID ((uint32_t) 1u << 2u) |
The rx_size_thresh2 parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ1_QNUM_VALID ((uint32_t) 1u << 3u) |
The rx_fdq0_sz1_qnum parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ2_QNUM_VALID ((uint32_t) 1u << 4u) |
The rx_fdq0_sz2_qnum parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ3_QNUM_VALID ((uint32_t) 1u << 5u) |
The rx_fdq0_sz3_qnum parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH_EN_VALID ((uint32_t) 1u << 6u) |
The rx_size_thresh_en parameter is valid for RM UDMAP rx flow size threshold configure TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_NOT_PRESENT (0u) |
Configure receive flow to handle extended packet info not present in the received packet descriptor. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_PRESENT (1u) |
Configure receive flow to handle extended packet info present in the received packet descriptor. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_NOT_PRESENT (0u) |
Configure receive flow to handle PS words not present in the received packet descriptor. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_PRESENT (1u) |
Configure receive flow to handle PS words present in the received packet descriptor. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_DROP (0u) |
Drop the received packet on starvation error. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_RETRY (1u) |
Re-try descriptor allocation operation on starvation error. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_END_PD (0u) |
Configure receive flow to place the PS words at the end of the packet descriptor. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_BEGIN_DB (1u) |
Configure receive flow to place the PS words at the beginning of the data buffer. See the UDMAP section of the TRM for more information on this setting.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_HOST (0u) |
Host descriptor configure for tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_MONO (2u) |
Monolithic descriptor configure for tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_NONE (0u) |
Do not overwrite. Source tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_CFG_TAG (1u) |
Overwrite with value in rx_src_tag_hi or rx_src_tag_lo parameters of tisci_msg_rm_udmap_flow_cfg_req for hi_sel and lo_sel parameters, respectively. Source tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_FLOW_ID (2u) |
Overwrite with flow_id[7:0] from back end application. Source tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_SRC_TAG (4u) |
Overwrite with src_tag[7:0] from back end application. Source tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_NONE (0u) |
Do not overwrite destination tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_CFG_TAG (1u) |
Overwrite with value in rx_dest_tag_hi or rx_dest_tag_lo parameters of tisci_msg_rm_udmap_flow_cfg_req for hi_sel and lo_sel parameters, respectively. Destination tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_FLOW_ID (2u) |
Overwrite with flow_id[7:0] from back end application destination tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_LO (4u) |
Overwrite with src_tag[7:0] from back end application destination tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_HI (5u) |
Overwrite with src_tag[15:8] from back end application destination tag byte selector configuration for tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel and tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel parameters.
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SOP_MAX (255u) |
The receive flow start of packet offset maximum byte offset
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_0_ENABLE (1U) |
Enable usage of size threshold 0 in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_1_ENABLE (2U) |
Enable usage of size threshold 1 in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_2_ENABLE (4U) |
Enable usage of size threshold 2 in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en
| #define TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_MAX (7u) |
Maximum encoded size threshold setting in tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_HOST_VALID ((uint32_t) 1U << 0U) |
The delegated_host parameter is valid for RM UDMAP flow delegation TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR_VALID ((uint32_t) 1U << 1U) |
The clear parameter is valid for RM UDMAP flow delegation TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR (1U) |
Clear flow delegation setting in tisci_msg_rm_udmap_flow_delegate_req::clear
| #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PERF_CTRL_VALID ((uint32_t) 1U << 0U) |
The perf_ctrl register value is valid for UDMAP global configuration TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_EMU_CTRL_VALID ((uint32_t) 1U << 1U) |
The emu_ctrl register value is valid for UDMAP global configuration TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_PSIL_TO_VALID ((uint32_t) 1U << 2U) |
The psil_to register value is valid for UDMAP global configuration TISCI message
| #define TISCI_MSG_VALUE_RM_UDMAP_GCFG_RFLOWFWSTAT_VALID ((uint32_t) 1U << 3U) |
The rflowfwstat register value is valid for UDMAP global configuration TISCI message
| struct tisci_msg_rm_udmap_gcfg_cfg_req __attribute__ | ( | (__packed__) | ) |
1.8.20