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◆ MCAN_MSG_RAM_MAX_WORD_COUNT
#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U) |
◆ CSL_CORE_ID_MCU_R5FSS0_0
#define CSL_CORE_ID_MCU_R5FSS0_0 (0U) |
◆ CSL_CORE_ID_R5FSS0_0
#define CSL_CORE_ID_R5FSS0_0 (1U) |
◆ CSL_CORE_ID_A53SS0_0
#define CSL_CORE_ID_A53SS0_0 (2U) |
◆ CSL_CORE_ID_A53SS0_1
#define CSL_CORE_ID_A53SS0_1 (3U) |
◆ CSL_CORE_ID_A53SS1_0
#define CSL_CORE_ID_A53SS1_0 (4U) |
◆ CSL_CORE_ID_A53SS1_1
#define CSL_CORE_ID_A53SS1_1 (5U) |
◆ CSL_CORE_ID_HSM_M4FSS0_0
#define CSL_CORE_ID_HSM_M4FSS0_0 (6U) |
◆ CSL_CORE_ID_C75SS0_0
#define CSL_CORE_ID_C75SS0_0 (7U) |
◆ CSL_CORE_ID_MAX
#define CSL_CORE_ID_MAX (8U) |
◆ CSL_CORE_ID_INVALID
#define CSL_CORE_ID_INVALID (0xFFFFU) |
◆ CSL_ARM_R5_CLUSTER_GROUP_ID_0
#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U) |
◆ CSL_ARM_R5_CPU_ID_0
#define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U) |
◆ CSL_EPWM_PER_CNT
#define CSL_EPWM_PER_CNT (9U) |
Number of ePWM instances.