AM62Ax MCU+ SDK  09.01.00
soc.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2022-2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef SOC_AM62AX_H_
34 #define SOC_AM62AX_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 
50 #include <stdint.h>
51 #include <kernel/dpl/SystemP.h>
52 #if (ENABLE_SCICLIENT_DIRECT)
53 #include <drivers/device_manager/sciclient.h>
54 #else
55 #include <drivers/sciclient.h>
56 #endif
57 
63 #define SOC_DOMAIN_ID_MAIN (0U)
64 #define SOC_DOMAIN_ID_MCU (1U)
65 #define SOC_DOMAIN_ID_WKUP (2U)
66 
73 /* PSC Instances */
74 #define SOC_PSC_DOMAIN_ID_MAIN (0U)
75 #define SOC_PSC_DOMAIN_ID_MCU (1U)
76 
83 /* PSC (Power Sleep Controller) Module states */
84 #define SOC_PSC_SYNCRESETDISABLE (0x0U)
85 #define SOC_PSC_SYNCRESET (0x1U)
86 #define SOC_PSC_DISABLE (0x2U)
87 #define SOC_PSC_ENABLE (0x3U)
88 
95 #define SOC_PSC_DOMAIN_OFF (0x0U)
96 #define SOC_PSC_DOMAIN_ON (0x1U)
97 
102 #define SOC_BOOTMODE_MMCSD (0X36C3)
103 
113 int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
114 
125 int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
126 
134 const char *SOC_getCoreName(uint16_t coreId);
135 
143 uint32_t SOC_getCoreId(const char * coreName);
144 
150 uint64_t SOC_getSelfCpuClk(void);
151 
158 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
159 
160 
167 void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
168 
175 void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
176 
181 void SOC_unlockAllMMR(void);
182 
189 void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
190 
200 int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate);
201 
207 void SOC_setDevStat(uint32_t bootMode);
208 
214 
219 
224 
231 
236 
241 
246 
253 
262 void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause);
263 
279 int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation,
280  uint32_t mcu2MainIsolation,
281  uint32_t mcu2dmIsolation,
282  uint32_t debugIsolationEnable);
290 
295 
307 int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum,
308  uint32_t *domainState, uint32_t *moduleState);
309 
320 int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState);
321 
324 #ifdef __cplusplus
325 }
326 #endif
327 
328 #endif
SOC_triggerMcuLpmWakeup
void SOC_triggerMcuLpmWakeup(void)
Generates the MCU IPC interrupt to DM R5 to wakeup the main domain from MCU only LPM mode.
sciclient.h
This file contains prototypes for APIs contained as a part of SCICLIENT as well as the structures of ...
SOC_enableResetIsolation
int32_t SOC_enableResetIsolation(uint32_t main2McuIsolation, uint32_t mcu2MainIsolation, uint32_t mcu2dmIsolation, uint32_t debugIsolationEnable)
Enable reset isolation of MCU domain for safety applications.
SOC_getCoreId
uint32_t SOC_getCoreId(const char *coreName)
Convert a core ID to a user readable name.
SOC_moduleSetClockFrequency
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate)
Set module clock to specified frequency.
SOC_controlModuleUnlockMMR
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition)
Unlock control module partition to allow writes into control MMRs.
SOC_generateSwWarmResetMainDomainFromMcuDomain
void SOC_generateSwWarmResetMainDomainFromMcuDomain(void)
Generate SW WARM Reset Main Domain from Mcu Domain.
SOC_generateSwPORResetMainDomainFromMcuDomain
void SOC_generateSwPORResetMainDomainFromMcuDomain(void)
Generate SW POR Reset Main Domain from Mcu Domain.
SystemP.h
SOC_clearResetCauseMainMcuDomain
void SOC_clearResetCauseMainMcuDomain(uint32_t resetCause)
Clears reason for Warm and Main/Mcu Domain Power On Resets. CTRLMMR_RST_SRC is just a mirror of CTRLM...
SOC_unlockAllMMR
void SOC_unlockAllMMR(void)
Unlocks all the control MMRs.
SOC_setMCUResetIsolationDone
void SOC_setMCUResetIsolationDone(uint32_t value)
Set MCU reset isolation done flag.
SOC_generateSwWarmResetMcuDomain
void SOC_generateSwWarmResetMcuDomain(void)
Generate SW WARM Reset Mcu Domain.
SOC_moduleGetClockFrequency
int32_t SOC_moduleGetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t *clkRate)
Get module clock frequency.
SOC_getWarmResetCauseMainDomain
uint32_t SOC_getWarmResetCauseMainDomain(void)
Get the reset reason source for Main Domain.
SOC_waitMainDomainReset
void SOC_waitMainDomainReset(void)
Wait for main domain reset to complete.
value
uint32_t value
Definition: tisci_otp_revision.h:2
SOC_setPSCState
int32_t SOC_setPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t pscState)
Set PSC (Power Sleep Controller) state.
SOC_getSelfCpuClk
uint64_t SOC_getSelfCpuClk(void)
Get the clock frequency in Hz of the CPU on which the driver is running.
SOC_generateSwWarmResetMainDomain
void SOC_generateSwWarmResetMainDomain(void)
Generate SW Warm Reset Main Domain.
SOC_generateSwPORResetMainDomain
void SOC_generateSwPORResetMainDomain(void)
Generate SW POR Reset Main Domain.
SOC_controlModuleLockMMR
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition)
Lock control module partition to prevent writes into control MMRs.
SOC_moduleClockEnable
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable)
Enable clock to specified module.
SOC_setDevStat
void SOC_setDevStat(uint32_t bootMode)
Change boot mode by setting devstat register.
SOC_getPSCState
int32_t SOC_getPSCState(uint32_t instNum, uint32_t domainNum, uint32_t moduleNum, uint32_t *domainState, uint32_t *moduleState)
Get PSC (Power Sleep Controller) state.
SOC_getCoreName
const char * SOC_getCoreName(uint16_t coreId)
Convert a core ID to a user readable name.
SOC_setEpwmTbClk
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable)
Enable or disable ePWM time base clock from Control MMR.
SOC_getWarmResetCauseMcuDomain
uint32_t SOC_getWarmResetCauseMcuDomain(void)
Get the reset reason source for Mcu Domain.