Introduction

This module contains APIs to program and use the MCSPI module. The APIs can be used by other drivers to get access to MCSPI and also by application to initiate data transfer operation.

Sub Modules
	APIs for MCSPI DMA mode

Files
file	mcspi/v0/mcspi.h
	MCSPI Driver API/interface file.

Data Structures
struct	MCSPI_Transaction
	Data structure used with MCSPI_transfer() More...

struct	MCSPI_OpenParams
	MCSPI Parameters. More...

struct	MCSPI_ChConfig
	MCSPI configuration parameters for the channel. More...

struct	MCSPI_Attrs
	MCSPI instance attributes - used during init time. More...

struct	MCSPI_ChObject
	MCSPI channel object. More...

struct	MCSPI_Object
	MCSPI driver object. More...

struct	MCSPI_Config
	MCSPI global configuration array. More...

Functions
void	MCSPI_init (void)
	This function initializes the MCSPI module. More...

void	MCSPI_deinit (void)
	This function de-initializes the MCSPI module. More...

MCSPI_Handle	MCSPI_open (uint32_t index, const MCSPI_OpenParams *openPrms)
	This function opens a given MCSPI peripheral. More...

void	MCSPI_close (MCSPI_Handle handle)
	Function to close a MCSPI peripheral specified by the MCSPI handle. More...

int32_t	MCSPI_chConfig (MCSPI_Handle handle, const MCSPI_ChConfig *chCfg)
	Function to configure a MCSPI channel. More...

int32_t	MCSPI_dmaChConfig (MCSPI_Handle handle, const MCSPI_ChConfig chCfg, const MCSPI_DmaChConfig dmaChCfg)
	Function to configure a DMA of a channel. More...

int32_t	MCSPI_transfer (MCSPI_Handle handle, MCSPI_Transaction *transaction)
	Function to perform MCSPI transactions. More...

int32_t	MCSPI_transferCancel (MCSPI_Handle handle)
	Function to cancel MCSPI transactions on channel of a SPI peripheral specified by the MCSPI handle. More...

static void	MCSPI_OpenParams_init (MCSPI_OpenParams *openPrms)
	Function to initialize the MCSPI_OpenParams struct to its defaults. More...

static void	MCSPI_ChConfig_init (MCSPI_ChConfig *chConfig)
	Function to initialize the MCSPI_ChConfig struct to its defaults. More...

static void	MCSPI_Transaction_init (MCSPI_Transaction *trans)
	Function to initialize the MCSPI_Transaction struct to its defaults. More...

uint32_t	MCSPI_getBaseAddr (MCSPI_Handle handle)
	Function to get base address of MCSPI instance of a particular handle. More...

int32_t	MCSPI_reConfigFifo (MCSPI_Handle handle, uint32_t chNum, uint32_t numWordsRxTx)
	Function to re-configure Effective FIFO Words. More...

static uint32_t	MCSPI_getBufWidthShift (uint32_t dataSize)
	This API will return the buffer width in bytes based on dataSize. More...

static uint32_t	MCSPI_readChStatusReg (uint32_t baseAddr, uint32_t chNum)
	This API will return the status of the McSPI channel currently in use. More...

static uint32_t	MCSPI_readChCtrlReg (uint32_t baseAddr, uint32_t chNum)
	This API returns Channel control register value. More...

static void	MCSPI_writeChCtrlReg (uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
	This API sets Channel control register value. More...

static uint32_t	MCSPI_readChConf (uint32_t baseAddr, uint32_t chNum)
	This API returns Channel Config register value. More...

static void	MCSPI_writeChConfReg (uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
	This API sets Channel Config register value. More...

static void	MCSPI_writeTxDataReg (uint32_t baseAddr, uint32_t txData, uint32_t chNum)
	This API will put the data on to the McSPI Channel transmit register. More...

static void	MCSPI_enableTxFIFO (uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
	This API will enable/disable the Tx FIFOs of McSPI peripheral. More...

static void	MCSPI_enableRxFIFO (uint32_t baseAddr, uint32_t chNum, uint32_t enableFlag)
	This API will enable/disable the Rx FIFOs of McSPI peripheral. More...

static uint32_t	MCSPI_readRxDataReg (uint32_t baseAddr, uint32_t chNum)
	This API will return the data present in the MCSPI_RX register. More...

static void	MCSPI_setDataWidth (uint32_t baseAddr, uint32_t chNum, uint32_t dataWidth)
	This API will set the data width in the channel config register. More...

Typedefs
typedef void *	MCSPI_Handle
	A handle that is returned from a MCSPI_open() call. More...

typedef void(*	MCSPI_CallbackFxn) (MCSPI_Handle handle, MCSPI_Transaction *transaction)
	The definition of a callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_CALLBACK. More...

Macros
#define	MCSPI_MAX_NUM_CHANNELS (4U)
	Max number of channels/Chip Select (CS) supported. More...

#define	MCSPI_FIFO_LENGTH (64U)
	Total length of FIFO for both TX/RX. More...

#define	MCSPI_RX_FIFO_ENABLE
	McSPI peripheral Rx FIFO is enabled. More...

#define	MCSPI_RX_FIFO_DISABLE
	McSPI peripheral Rx FIFO is disabled. More...

#define	MCSPI_TX_FIFO_ENABLE
	McSPI peripheral Tx FIFO is enabled. More...

#define	MCSPI_TX_FIFO_DISABLE
	McSPI peripheral Tx FIFO is disabled. More...

#define	MCSPI_REG_OFFSET (0x14U)
	McSPI Register Offset for MCSPI_CHxCONF, MCSPI_CHxSTAT, MCSPI_CHxCTRL, MCSPI_TXx and MCSPI_RXx register set. More...

#define	MCSPI_CHCONF(x)
	Base address of McSPI_CHCONF(x) More...

#define	MCSPI_CHSTAT(x)
	Base address of McSPI_CHSTAT(x) More...

#define	MCSPI_CHCTRL(x)
	Base address of McSPI_CHCTRL(x) More...

#define	MCSPI_CHTX(x)
	Base address of McSPI_CHTX(x) More...

#define	MCSPI_CHRX(x)
	Base address of McSPI_CHRX(x) More...

#define	MCSPI_CLKD_MASK (0x0FU)

#define	MCSPI_IRQSTATUS_CLEAR_ALL
	Bit mask to clear all status bits. More...

Channel Id
Values used to determine the channel number used for McSPI communication. This determines which Chip Select (CS) line to use
#define	MCSPI_CHANNEL_0 (0U)

#define	MCSPI_CHANNEL_1 (1U)

#define	MCSPI_CHANNEL_2 (2U)

#define	MCSPI_CHANNEL_3 (3U)

Operating Mode
Values used to determine the McSPI driver operation.
#define	MCSPI_OPER_MODE_POLLED (0U)

#define	MCSPI_OPER_MODE_INTERRUPT (1U)

#define	MCSPI_OPER_MODE_DMA (2U)

Transfer Status Code
Status codes that are set by the MCSPI driver
#define	MCSPI_TRANSFER_COMPLETED (0U)

#define	MCSPI_TRANSFER_STARTED (1U)

#define	MCSPI_TRANSFER_CANCELLED (2U)

#define	MCSPI_TRANSFER_FAILED (3U)

#define	MCSPI_TRANSFER_CSN_DEASSERT (4U)

#define	MCSPI_TRANSFER_TIMEOUT (5U)

Transfer Mode
This determines whether the driver operates synchronously or asynchronously In MCSPI_TRANSFER_MODE_BLOCKING mode MCSPI_transfer() blocks code execution until the transaction has completed In MCSPI_TRANSFER_MODE_CALLBACK MCSPI_transfer() does not block code execution and instead calls a MCSPI_CallbackFxn callback function when the transaction has completed
#define	MCSPI_TRANSFER_MODE_BLOCKING (0U)
	MCSPI_transfer() blocks execution. This mode can only be used when called within a Task context More...

#define	MCSPI_TRANSFER_MODE_CALLBACK (1U)
	MCSPI_transfer() does not block code execution and will call a MCSPI_CallbackFxn. This mode can be used in a Task, Swi, or Hwi context More...

Modes of Operation
Definitions for various MCSPI modes of operation The MCSPI driver operates in both master and SPI slave modes. Logically, the implementation is identical, however the difference between these two modes is driven by hardware. The default mode is MCSPI_MS_MODE_MASTER, but can be set to slave mode by setting MCSPI_OpenParams.msMode to MCSPI_MS_MODE_SLAVE in the parameters passed to MCSPI_open().
#define	MCSPI_MS_MODE_MASTER (CSL_MCSPI_MODULCTRL_MS_MASTER)
	The module generates the clock and CS. More...

#define	MCSPI_MS_MODE_SLAVE (CSL_MCSPI_MODULCTRL_MS_SLAVE)
	The module receives the clock and CS. More...

Frame Format
Definitions for various SPI data frame formats POL0 = SPICLK is held low during the INACTIVE state POL1 = SPICLK is held high during the INACTIVE state PHA0 = Data are latched on odd-numbered edges of SPICLK PHA1 = Data are latched on even-numbered edges of SPICLK
#define	MCSPI_FF_POL0_PHA0 (0U)

#define	MCSPI_FF_POL0_PHA1 (1U)

#define	MCSPI_FF_POL1_PHA0 (2U)

#define	MCSPI_FF_POL1_PHA1 (3U)

Chip-select Polarity
Type for SPI Chip Select Polarity and Clock Idle Level
#define	MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)
	SPIEN (CS) is held high during the ACTIVE state. More...

#define	MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)
	SPIEN (CS) is held low during the ACTIVE state. More...

Transmit-Receive Modes

#define	MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)

#define	MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)

#define	MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)

Input Select

#define	MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)
	Data line 0 (SPIDAT[0]) selected for reception. More...

#define	MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)
	Data line 1 (SPIDAT[1]) selected for reception. More...

Transmission Enable for Data Line

#define	MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)
	Data line selected for transmission. More...

#define	MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)
	No transmission on Data Line. More...

Slave Chip-select Signal Select

#define	MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)

#define	MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)

#define	MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)

#define	MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)

Start-bit Polarity

#define	MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
	SStart-bit polarity is held to 1 during MCSPI transfer. More...

#define	MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)
	Start-bit polarity is held to 0 during MCSPI transfer. More...

Chip-select Idle Time
Values used to configure the chip select time control (TCS)
#define	MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)
	0.5 clock cycles delay More...

#define	MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)
	1.5 clock cycles delay More...

#define	MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)
	2.5 clock cycles delay More...

#define	MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)
	3.5 clock cycles delay More...

Channel Mode

#define	MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)
	Only one channel will be used in master mode. This should be used when CS is used in forced enable mode. More...

#define	MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)
	More than one channel will be used in master mode. More...

Pin Mode

#define	MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)
	SPIEN (CS) is not used. In this mode all related options to chip-select have no meaning. More...

#define	MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)

Init Delay
Values used to enable initial delay for first transfer
#define	MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)
	No delay. More...

#define	MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)
	4 SPI bus clock delays More...

#define	MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)
	8 SPI bus clock delays More...

#define	MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)
	16 SPI bus clock delays More...

#define	MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)
	32 SPI bus clock delays More...

Macro Definition Documentation

◆ MCSPI_CHANNEL_0

#define MCSPI_CHANNEL_0 (0U)

◆ MCSPI_CHANNEL_1

#define MCSPI_CHANNEL_1 (1U)

◆ MCSPI_CHANNEL_2

#define MCSPI_CHANNEL_2 (2U)

◆ MCSPI_CHANNEL_3

#define MCSPI_CHANNEL_3 (3U)

◆ MCSPI_OPER_MODE_POLLED

#define MCSPI_OPER_MODE_POLLED (0U)

◆ MCSPI_OPER_MODE_INTERRUPT

#define MCSPI_OPER_MODE_INTERRUPT (1U)

◆ MCSPI_OPER_MODE_DMA

#define MCSPI_OPER_MODE_DMA (2U)

◆ MCSPI_MAX_NUM_CHANNELS

#define MCSPI_MAX_NUM_CHANNELS (4U)

Max number of channels/Chip Select (CS) supported.

◆ MCSPI_TRANSFER_COMPLETED

#define MCSPI_TRANSFER_COMPLETED (0U)

◆ MCSPI_TRANSFER_STARTED

#define MCSPI_TRANSFER_STARTED (1U)

◆ MCSPI_TRANSFER_CANCELLED

#define MCSPI_TRANSFER_CANCELLED (2U)

◆ MCSPI_TRANSFER_FAILED

#define MCSPI_TRANSFER_FAILED (3U)

◆ MCSPI_TRANSFER_CSN_DEASSERT

#define MCSPI_TRANSFER_CSN_DEASSERT (4U)

◆ MCSPI_TRANSFER_TIMEOUT

#define MCSPI_TRANSFER_TIMEOUT (5U)

◆ MCSPI_TRANSFER_MODE_BLOCKING

#define MCSPI_TRANSFER_MODE_BLOCKING (0U)

MCSPI_transfer() blocks execution. This mode can only be used when called within a Task context

◆ MCSPI_TRANSFER_MODE_CALLBACK

#define MCSPI_TRANSFER_MODE_CALLBACK (1U)

MCSPI_transfer() does not block code execution and will call a MCSPI_CallbackFxn. This mode can be used in a Task, Swi, or Hwi context

◆ MCSPI_MS_MODE_MASTER

#define MCSPI_MS_MODE_MASTER (CSL_MCSPI_MODULCTRL_MS_MASTER)

The module generates the clock and CS.

◆ MCSPI_MS_MODE_SLAVE

#define MCSPI_MS_MODE_SLAVE (CSL_MCSPI_MODULCTRL_MS_SLAVE)

The module receives the clock and CS.

◆ MCSPI_FF_POL0_PHA0

#define MCSPI_FF_POL0_PHA0 (0U)

◆ MCSPI_FF_POL0_PHA1

#define MCSPI_FF_POL0_PHA1 (1U)

◆ MCSPI_FF_POL1_PHA0

#define MCSPI_FF_POL1_PHA0 (2U)

◆ MCSPI_FF_POL1_PHA1

#define MCSPI_FF_POL1_PHA1 (3U)

◆ MCSPI_CS_POL_HIGH

#define MCSPI_CS_POL_HIGH (CSL_MCSPI_CH0CONF_EPOL_ACTIVEHIGH)

SPIEN (CS) is held high during the ACTIVE state.

◆ MCSPI_CS_POL_LOW

#define MCSPI_CS_POL_LOW (CSL_MCSPI_CH0CONF_EPOL_ACTIVELOW)

SPIEN (CS) is held low during the ACTIVE state.

◆ MCSPI_TR_MODE_TX_RX

#define MCSPI_TR_MODE_TX_RX (CSL_MCSPI_CH0CONF_TRM_TRANSRECEI)

◆ MCSPI_TR_MODE_RX_ONLY

#define MCSPI_TR_MODE_RX_ONLY (CSL_MCSPI_CH0CONF_TRM_RECEIVONLY)

◆ MCSPI_TR_MODE_TX_ONLY

#define MCSPI_TR_MODE_TX_ONLY (CSL_MCSPI_CH0CONF_TRM_TRANSONLY)

◆ MCSPI_IS_D0

#define MCSPI_IS_D0 (CSL_MCSPI_CH0CONF_IS_LINE0)

Data line 0 (SPIDAT[0]) selected for reception.

◆ MCSPI_IS_D1

#define MCSPI_IS_D1 (CSL_MCSPI_CH0CONF_IS_LINE1)

Data line 1 (SPIDAT[1]) selected for reception.

◆ MCSPI_DPE_ENABLE

#define MCSPI_DPE_ENABLE (CSL_MCSPI_CH0CONF_DPE0_ENABLED)

Data line selected for transmission.

◆ MCSPI_DPE_DISABLE

#define MCSPI_DPE_DISABLE (CSL_MCSPI_CH0CONF_DPE0_DISABLED)

No transmission on Data Line.

◆ MCSPI_SLV_CS_SELECT_0

#define MCSPI_SLV_CS_SELECT_0 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN0)

◆ MCSPI_SLV_CS_SELECT_1

#define MCSPI_SLV_CS_SELECT_1 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN1)

◆ MCSPI_SLV_CS_SELECT_2

#define MCSPI_SLV_CS_SELECT_2 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN2)

◆ MCSPI_SLV_CS_SELECT_3

#define MCSPI_SLV_CS_SELECT_3 (CSL_MCSPI_CH0CONF_SPIENSLV_SPIEN3)

◆ MCSPI_SB_POL_HIGH

#define MCSPI_SB_POL_HIGH (CSL_MCSPI_CH0CONF_SBPOL_HIGHLEVEL)

SStart-bit polarity is held to 1 during MCSPI transfer.

◆ MCSPI_SB_POL_LOW

#define MCSPI_SB_POL_LOW (CSL_MCSPI_CH0CONF_SBPOL_LOWLEVEL)

Start-bit polarity is held to 0 during MCSPI transfer.

◆ MCSPI_TCS0_0_CLK

#define MCSPI_TCS0_0_CLK (CSL_MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY)

0.5 clock cycles delay

◆ MCSPI_TCS0_1_CLK

#define MCSPI_TCS0_1_CLK (CSL_MCSPI_CH0CONF_TCS0_ONECYCLEDLY)

1.5 clock cycles delay

◆ MCSPI_TCS0_2_CLK

#define MCSPI_TCS0_2_CLK (CSL_MCSPI_CH0CONF_TCS0_TWOCYCLEDLY)

2.5 clock cycles delay

◆ MCSPI_TCS0_3_CLK

#define MCSPI_TCS0_3_CLK (CSL_MCSPI_CH0CONF_TCS0_THREECYCLEDLY)

3.5 clock cycles delay

◆ MCSPI_CH_MODE_SINGLE

#define MCSPI_CH_MODE_SINGLE (CSL_MCSPI_MODULCTRL_SINGLE_SINGLE)

Only one channel will be used in master mode. This should be used when CS is used in forced enable mode.

◆ MCSPI_CH_MODE_MULTI

#define MCSPI_CH_MODE_MULTI (CSL_MCSPI_MODULCTRL_SINGLE_MULTI)

More than one channel will be used in master mode.

◆ MCSPI_PINMODE_3PIN

#define MCSPI_PINMODE_3PIN (CSL_MCSPI_MODULCTRL_PIN34_3PINMODE)

SPIEN (CS) is not used. In this mode all related options to chip-select have no meaning.

◆ MCSPI_PINMODE_4PIN

#define MCSPI_PINMODE_4PIN (CSL_MCSPI_MODULCTRL_PIN34_4PINMODE)

◆ MCSPI_INITDLY_0

#define MCSPI_INITDLY_0 (CSL_MCSPI_MODULCTRL_INITDLY_NODELAY)

No delay.

◆ MCSPI_INITDLY_4

#define MCSPI_INITDLY_4 (CSL_MCSPI_MODULCTRL_INITDLY_4CLKDLY)

4 SPI bus clock delays

◆ MCSPI_INITDLY_8

#define MCSPI_INITDLY_8 (CSL_MCSPI_MODULCTRL_INITDLY_8CLKDLY)

8 SPI bus clock delays

◆ MCSPI_INITDLY_16

#define MCSPI_INITDLY_16 (CSL_MCSPI_MODULCTRL_INITDLY_16CLKDLY)

16 SPI bus clock delays

◆ MCSPI_INITDLY_32

#define MCSPI_INITDLY_32 (CSL_MCSPI_MODULCTRL_INITDLY_32CLKDLY)

32 SPI bus clock delays

◆ MCSPI_FIFO_LENGTH

#define MCSPI_FIFO_LENGTH (64U)

Total length of FIFO for both TX/RX.

◆ MCSPI_RX_FIFO_ENABLE

#define MCSPI_RX_FIFO_ENABLE

Value:

                                      ((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFENABLED \
                                      <<                                      \
                                      CSL_MCSPI_CH0CONF_FFER_SHIFT)

McSPI peripheral Rx FIFO is enabled.

◆ MCSPI_RX_FIFO_DISABLE

#define MCSPI_RX_FIFO_DISABLE

Value:

((uint32_t) CSL_MCSPI_CH0CONF_FFER_FFDISABLED \

<< CSL_MCSPI_CH0CONF_FFER_SHIFT)

McSPI peripheral Rx FIFO is disabled.

◆ MCSPI_TX_FIFO_ENABLE

#define MCSPI_TX_FIFO_ENABLE

Value:

((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFENABLED \

<< CSL_MCSPI_CH0CONF_FFEW_SHIFT)

McSPI peripheral Tx FIFO is enabled.

◆ MCSPI_TX_FIFO_DISABLE

#define MCSPI_TX_FIFO_DISABLE

Value:

((uint32_t) CSL_MCSPI_CH0CONF_FFEW_FFDISABLED \

<< CSL_MCSPI_CH0CONF_FFEW_SHIFT)

McSPI peripheral Tx FIFO is disabled.

◆ MCSPI_REG_OFFSET

#define MCSPI_REG_OFFSET (0x14U)

McSPI Register Offset for MCSPI_CHxCONF, MCSPI_CHxSTAT, MCSPI_CHxCTRL, MCSPI_TXx and MCSPI_RXx register set.

◆ MCSPI_CHCONF

#define MCSPI_CHCONF ( x )

Value:

                                     ((uint32_t) CSL_MCSPI_CH0CONF +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))

Base address of McSPI_CHCONF(x)

◆ MCSPI_CHSTAT

#define MCSPI_CHSTAT ( x )

Value:

                                     ((uint32_t) CSL_MCSPI_CH0STAT +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))

Base address of McSPI_CHSTAT(x)

◆ MCSPI_CHCTRL

#define MCSPI_CHCTRL ( x )

Value:

                                     ((uint32_t) CSL_MCSPI_CH0CTRL +            \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))

Base address of McSPI_CHCTRL(x)

◆ MCSPI_CHTX

#define MCSPI_CHTX ( x )

Value:

                                     ((uint32_t) CSL_MCSPI_TX0 +                \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))

Base address of McSPI_CHTX(x)

◆ MCSPI_CHRX

#define MCSPI_CHRX ( x )

Value:

                                     ((uint32_t) CSL_MCSPI_RX0 +                \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                                 (uint32_t) (x)))

Base address of McSPI_CHRX(x)

◆ MCSPI_CLKD_MASK

#define MCSPI_CLKD_MASK (0x0FU)

◆ MCSPI_IRQSTATUS_CLEAR_ALL

#define MCSPI_IRQSTATUS_CLEAR_ALL

Value:

                                     (CSL_MCSPI_IRQSTATUS_EOW_MASK |            \
                                     CSL_MCSPI_IRQSTATUS_WKS_MASK |            \
                                     CSL_MCSPI_IRQSTATUS_RX3_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX3_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX3_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX2_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX2_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX2_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX1_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX1_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX1_EMPTY_MASK |      \
                                     CSL_MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK |   \
                                     CSL_MCSPI_IRQSTATUS_RX0_FULL_MASK |       \
                                     CSL_MCSPI_IRQSTATUS_TX0_UNDERFLOW_MASK |  \
                                     CSL_MCSPI_IRQSTATUS_TX0_EMPTY_MASK)

Bit mask to clear all status bits.

Typedef Documentation

◆ MCSPI_Handle

typedef void* MCSPI_Handle

A handle that is returned from a MCSPI_open() call.

◆ MCSPI_CallbackFxn

typedef void(* MCSPI_CallbackFxn) (MCSPI_Handle handle, MCSPI_Transaction *transaction)

The definition of a callback function used by the SPI driver when used in MCSPI_TRANSFER_MODE_CALLBACK.

Parameters

MCSPI_Handle	MCSPI_Handle
MCSPI_Transaction*	Pointer to a MCSPI_Transaction

Function Documentation

◆ MCSPI_init()

void MCSPI_init ( void )

This function initializes the MCSPI module.

◆ MCSPI_deinit()

void MCSPI_deinit ( void )

This function de-initializes the MCSPI module.

◆ MCSPI_open()

MCSPI_Handle MCSPI_open	(	uint32_t	index,
		const MCSPI_OpenParams *	openPrms
	)

This function opens a given MCSPI peripheral.

Precondition: MCSPI controller has been initialized using MCSPI_init()

Parameters

index	Index of config to use in the MCSPI_Config array
openPrms	Pointer to open parameters. If NULL is passed, then default values will be used

Returns: A MCSPI_Handle on success or a NULL on an error or if it has been opened already

See also: MCSPI_init(); MCSPI_close(); MCSPI_OpenParams_init

◆ MCSPI_close()

void MCSPI_close ( MCSPI_Handle handle )

Function to close a MCSPI peripheral specified by the MCSPI handle.

Precondition: MCSPI_open() has to be called first

Parameters

handle MCSPI_Handle returned from MCSPI_open()

See also: MCSPI_open()

◆ MCSPI_chConfig()

int32_t MCSPI_chConfig	(	MCSPI_Handle	handle,
		const MCSPI_ChConfig *	chCfg
	)

Function to configure a MCSPI channel.

Parameters

handle	MCSPI_Handle returned from MCSPI_open()
chCfg	Pointer to MCSPI_ChConfig. This parameter can't be NULL

Returns: SystemP_SUCCESS if successful; else error on failure

See also: MCSPI_open; MCSPI_ChConfig_init

◆ MCSPI_dmaChConfig()

int32_t MCSPI_dmaChConfig	(	MCSPI_Handle	handle,
		const MCSPI_ChConfig *	chCfg,
		const MCSPI_DmaChConfig *	dmaChCfg
	)

Function to configure a DMA of a channel.

Parameters

handle	MCSPI_Handle returned from MCSPI_open()
chCfg	Pointer to MCSPI_ChConfig. This parameter can't be NULL
dmaChCfg	Pointer to MCSPI_DmaChConfig. This parameter can't be NULL

Returns: SystemP_SUCCESS if successful; else error on failure

See also: MCSPI_open; MCSPI_ChConfig_init

◆ MCSPI_transfer()

int32_t MCSPI_transfer	(	MCSPI_Handle	handle,
		MCSPI_Transaction *	transaction
	)

Function to perform MCSPI transactions.

If the MCSPI is in MCSPI_MS_MODE_MASTER mode, it will immediately start the transaction. If the MCSPI is in MCSPI_MS_MODE_SLAVE mode, it prepares the driver for a transaction with a MCSPI master device. The device will then wait until the master begins the transfer.

In MCSPI_TRANSFER_MODE_BLOCKING, MCSPI_transfer() will block task execution until the transaction has completed or a timeout has occurred.

In MCSPI_TRANSFER_MODE_CALLBACK, MCSPI_transfer() does not block task execution, but calls a MCSPI_CallbackFxn once the transfer has finished. This makes MCSPI_transfer() safe to be used within a Task, software or hardware interrupt context.

From calling MCSPI_transfer() until transfer completion, the MCSPI_Transaction structure must stay persistent and must not be altered by application code. It is also forbidden to modify the content of the MCSPI_Transaction.txBuf during a transaction, even though the physical transfer might not have started yet. Doing this can result in data corruption. This is especially important for slave operations where MCSPI_transfer() might be called a long time before the actual data transfer begins.

Parameters

handle MCSPI_Handle returned from MCSPI_open()

transaction Pointer to a MCSPI_Transaction. All of the fields within transaction except MCSPI_Transaction.count and MCSPI_Transaction.status are WO (write-only) unless otherwise noted in the driver implementations. If a transaction timeout has occurred, MCSPI_Transaction.count will contain the number of frames that were transferred. Neither is it allowed to modify the transaction object nor the content of MCSPI_Transaction.txBuf until the transfer has completed

Returns: SystemP_SUCCESS if started successfully; else error on failure

See also: MCSPI_open; MCSPI_transferCancel

◆ MCSPI_transferCancel()

int32_t MCSPI_transferCancel ( MCSPI_Handle handle )

Function to cancel MCSPI transactions on channel of a SPI peripheral specified by the MCSPI handle.

In MCSPI_TRANSFER_MODE_BLOCKING, MCSPI_transferCancel has no effect.

In MCSPI_TRANSFER_MODE_CALLBACK, MCSPI_transferCancel() will stop an MCSPI transfer if if one is in progress. If a transaction was in progress, its callback function will be called in context from which this API is called from. The MCSPI_CallbackFxn function can determine if the transaction was successful or not by reading the MCSPI_TransferStatus status value in the MCSPI_Transaction structure.

Parameters

handle MCSPI_Handle returned from MCSPI_open()

See also: MCSPI_open; MCSPI_transfer

◆ MCSPI_OpenParams_init()

static void MCSPI_OpenParams_init ( MCSPI_OpenParams * openPrms )

inlinestatic

Function to initialize the MCSPI_OpenParams struct to its defaults.

Parameters

openPrms Pointer to MCSPI_OpenParams structure for initialization

◆ MCSPI_ChConfig_init()

static void MCSPI_ChConfig_init ( MCSPI_ChConfig * chConfig )

inlinestatic

Function to initialize the MCSPI_ChConfig struct to its defaults.

Parameters

chConfig Pointer to MCSPI_ChConfig structure for initialization

◆ MCSPI_Transaction_init()

static void MCSPI_Transaction_init ( MCSPI_Transaction * trans )

inlinestatic

Function to initialize the MCSPI_Transaction struct to its defaults.

Parameters

trans Pointer to MCSPI_Transaction structure for initialization

◆ MCSPI_getBaseAddr()

uint32_t MCSPI_getBaseAddr ( MCSPI_Handle handle )

Function to get base address of MCSPI instance of a particular handle.

Parameters

handle MCSPI_Handle returned from MCSPI_open()

See also: MCSPI_open

◆ MCSPI_reConfigFifo()

int32_t MCSPI_reConfigFifo	(	MCSPI_Handle	handle,
		uint32_t	chNum,
		uint32_t	numWordsRxTx
	)

Function to re-configure Effective FIFO Words.

Parameters

handle	MCSPI_Handle returned from MCSPI_open()
chNum	Channel used for communication.
numWordsRxTx	Number of words to transfer

Returns: SystemP_SUCCESS if successful; else error on failure

See also: MCSPI_open

◆ MCSPI_getBufWidthShift()

static uint32_t MCSPI_getBufWidthShift ( uint32_t dataSize )

inlinestatic

This API will return the buffer width in bytes based on dataSize.

Parameters

dataSize MCSPI data frame size in bits - valid values: 4 bits to 32 bits

Returns: bufWidthShift Width of buffer in bytes - used for accessing the TX/RX buffer. When dataWidth <= 8, (1 byte - 0 shift) When dataWidth > 8 && <= 16, (2 bytes - 1 shift) When dataWidth > 16 && <= 32, (4 bytes - 2 shift)

See also: MCSPI_open

◆ MCSPI_readChStatusReg()

static uint32_t MCSPI_readChStatusReg	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

inlinestatic

This API will return the status of the McSPI channel currently in use.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel used for communication. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n

Returns: This API will return the status of the McSPI channel status register. User can use the following macros to check the status
MCSPI_CH_STAT_RXS_FULL - Receiver register is full
MCSPI_CH_STAT_TXS_EMPTY - Transmitter register is full
MCSPI_CH_STAT_EOT - End of transfer status
MCSPI_CH_TXFFE - FIFO transmit buffer empty status
MCSPI_CH_TXFFF - FIFO transmit buffer full status
MCSPI_CH_RXFFE - FIFO receive buffer empty status
MCSPI_CH_RXFFF - FIFO receive buffer full status

See also: MCSPI_open

◆ MCSPI_readChCtrlReg()

static uint32_t MCSPI_readChCtrlReg	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

inlinestatic

This API returns Channel control register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.

Returns: Channel control register value.

See also: MCSPI_open

◆ MCSPI_writeChCtrlReg()

static void MCSPI_writeChCtrlReg	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	regVal
	)

inlinestatic

This API sets Channel control register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
regVal	register value to set in channel control register.

See also: MCSPI_open

◆ MCSPI_readChConf()

static uint32_t MCSPI_readChConf	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

inlinestatic

This API returns Channel Config register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.

Returns: Channel Config register value.

See also: MCSPI_open

◆ MCSPI_writeChConfReg()

static void MCSPI_writeChConfReg	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	regVal
	)

inlinestatic

This API sets Channel Config register value.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
regVal	register value to set in channel Config register.

See also: MCSPI_open

◆ MCSPI_writeTxDataReg()

static void MCSPI_writeTxDataReg	(	uint32_t	baseAddr,
		uint32_t	txData,
		uint32_t	chNum
	)

inlinestatic

This API will put the data on to the McSPI Channel transmit register.

Parameters

baseAddr	Memory Address of the McSPI instance used.
txData	32 bit data sent by the user which is put on to the MCSPI_TX register.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

See also: MCSPI_open

◆ MCSPI_enableTxFIFO()

static void MCSPI_enableTxFIFO	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	enableFlag
	)

inlinestatic

This API will enable/disable the Tx FIFOs of McSPI peripheral.

Parameters

baseAddr Memory Address of the McSPI instance used.

chNum Channel number of the McSPI instance used.

enableFlag

Flag to enable/diable FIFO transmit mode.

    'enableFlag' can take the following values.\n
    MCSPI_TX_FIFO_ENABLE - Enables the receiver FIFO of McSPI.\n
    MCSPI_TX_FIFO_DISABLE - Disables the receiver FIFO of McSPI.\n

    'chNum' can take the following values.\n
    MCSPI_CHANNEL_n - Channel n is used for communication.\n

    For chNum n can range from 0-3.\n

Note: : Enabling FIFO is restricted to only 1 channel.

See also: MCSPI_open

◆ MCSPI_enableRxFIFO()

static void MCSPI_enableRxFIFO	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	enableFlag
	)

inlinestatic

This API will enable/disable the Rx FIFOs of McSPI peripheral.

Parameters

baseAddr Memory Address of the McSPI instance used.

chNum Channel number of the McSPI instance used.

enableFlag

Flag to enable/diable FIFO receive mode.

    'enableFlag' can take the following values.\n
    MCSPI_RX_FIFO_ENABLE - Enables the receiver FIFO of McSPI.\n
    MCSPI_RX_FIFO_DISABLE - Disables the receiver FIFO of McSPI.\n

    'chNum' can take the following values.\n
    MCSPI_CHANNEL_n - Channel n is used for communication.\n

    For chNum n can range from 0-3.\n

Note: : Enabling FIFO is restricted to only 1 channel.

See also: MCSPI_open

◆ MCSPI_readRxDataReg()

static uint32_t MCSPI_readRxDataReg	(	uint32_t	baseAddr,
		uint32_t	chNum
	)

inlinestatic

This API will return the data present in the MCSPI_RX register.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n

See also: MCSPI_open

Returns: This API will return the data received in the MCSPI_RX register.

◆ MCSPI_setDataWidth()

static void MCSPI_setDataWidth	(	uint32_t	baseAddr,
		uint32_t	chNum,
		uint32_t	dataWidth
	)

inlinestatic

This API will set the data width in the channel config register.

Parameters

baseAddr	Memory Address of the McSPI instance used.
chNum	Channel number of the McSPI instance used.
dataWidth	MCSPI data frame width in bits. 'chNum' can take the following values.\n MCSPI_CHANNEL_n - Channel n is used for communication.\n For chNum n can range from 0-3.\n For dataWidth valid values: 4 bits to 32 bits

See also: MCSPI_open

Variable Documentation

◆ gMcspiConfig

MCSPI_Config gMcspiConfig[]

extern

Externally defined driver configuration array.

◆ gMcspiConfigNum

uint32_t gMcspiConfigNum

extern

Externally defined driver configuration array size.

Introduction

Sub Modules

Files

Data Structures

Functions

Typedefs

Macros

Channel Id

Operating Mode

Transfer Status Code

Transfer Mode

Modes of Operation

Frame Format

Chip-select Polarity

Transmit-Receive Modes

Input Select

Transmission Enable for Data Line

Slave Chip-select Signal Select

Start-bit Polarity

Chip-select Idle Time

Channel Mode

Pin Mode

Init Delay

Macro Definition Documentation

◆ MCSPI_CHANNEL_0

◆ MCSPI_CHANNEL_1

◆ MCSPI_CHANNEL_2

◆ MCSPI_CHANNEL_3

◆ MCSPI_OPER_MODE_POLLED

◆ MCSPI_OPER_MODE_INTERRUPT

◆ MCSPI_OPER_MODE_DMA

◆ MCSPI_MAX_NUM_CHANNELS

◆ MCSPI_TRANSFER_COMPLETED

◆ MCSPI_TRANSFER_STARTED

◆ MCSPI_TRANSFER_CANCELLED

◆ MCSPI_TRANSFER_FAILED

◆ MCSPI_TRANSFER_CSN_DEASSERT

◆ MCSPI_TRANSFER_TIMEOUT

◆ MCSPI_TRANSFER_MODE_BLOCKING

◆ MCSPI_TRANSFER_MODE_CALLBACK

◆ MCSPI_MS_MODE_MASTER

◆ MCSPI_MS_MODE_SLAVE

◆ MCSPI_FF_POL0_PHA0

◆ MCSPI_FF_POL0_PHA1

◆ MCSPI_FF_POL1_PHA0

◆ MCSPI_FF_POL1_PHA1

◆ MCSPI_CS_POL_HIGH

◆ MCSPI_CS_POL_LOW

◆ MCSPI_TR_MODE_TX_RX

◆ MCSPI_TR_MODE_RX_ONLY

◆ MCSPI_TR_MODE_TX_ONLY

◆ MCSPI_IS_D0

◆ MCSPI_IS_D1

◆ MCSPI_DPE_ENABLE

◆ MCSPI_DPE_DISABLE

◆ MCSPI_SLV_CS_SELECT_0

◆ MCSPI_SLV_CS_SELECT_1

◆ MCSPI_SLV_CS_SELECT_2

◆ MCSPI_SLV_CS_SELECT_3

◆ MCSPI_SB_POL_HIGH

◆ MCSPI_SB_POL_LOW

◆ MCSPI_TCS0_0_CLK

◆ MCSPI_TCS0_1_CLK

◆ MCSPI_TCS0_2_CLK

◆ MCSPI_TCS0_3_CLK

◆ MCSPI_CH_MODE_SINGLE

◆ MCSPI_CH_MODE_MULTI

◆ MCSPI_PINMODE_3PIN

◆ MCSPI_PINMODE_4PIN

◆ MCSPI_INITDLY_0

◆ MCSPI_INITDLY_4

◆ MCSPI_INITDLY_8

◆ MCSPI_INITDLY_16

◆ MCSPI_INITDLY_32

◆ MCSPI_FIFO_LENGTH

◆ MCSPI_RX_FIFO_ENABLE

◆ MCSPI_RX_FIFO_DISABLE

◆ MCSPI_TX_FIFO_ENABLE

◆ MCSPI_TX_FIFO_DISABLE

◆ MCSPI_REG_OFFSET