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Macros
#define	TISCI_DEV_ADC0 0U
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#define	TISCI_DEV_DBG_INTROUTER0 2U

#define	TISCI_DEV_MAIN_GPIOMUX_INTROUTER0 3U

#define	TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0 5U

#define	TISCI_DEV_TIMESYNC_EVENT_INTROUTER0 6U

#define	TISCI_DEV_CPSW0 13U

#define	TISCI_DEV_STM0 15U

#define	TISCI_DEV_DCC0 16U

#define	TISCI_DEV_DCC1 17U

#define	TISCI_DEV_DCC2 18U

#define	TISCI_DEV_DCC3 19U

#define	TISCI_DEV_DCC4 20U

#define	TISCI_DEV_DCC5 21U

#define	TISCI_DEV_SMS0 22U

#define	TISCI_DEV_MCU_DCC0 23U

#define	TISCI_DEV_DEBUGSS_WRAP0 24U

#define	TISCI_DEV_DMASS0 25U

#define	TISCI_DEV_DMASS0_BCDMA_0 26U

#define	TISCI_DEV_DMASS0_CBASS_0 27U

#define	TISCI_DEV_DMASS0_INTAGGR_0 28U

#define	TISCI_DEV_DMASS0_IPCSS_0 29U

#define	TISCI_DEV_DMASS0_PKTDMA_0 30U

#define	TISCI_DEV_DMASS0_RINGACC_0 33U

#define	TISCI_DEV_TIMER0 36U

#define	TISCI_DEV_TIMER1 37U

#define	TISCI_DEV_TIMER2 38U

#define	TISCI_DEV_TIMER3 39U

#define	TISCI_DEV_TIMER4 40U

#define	TISCI_DEV_TIMER5 41U

#define	TISCI_DEV_TIMER6 42U

#define	TISCI_DEV_TIMER7 43U

#define	TISCI_DEV_TIMER8 44U

#define	TISCI_DEV_TIMER9 45U

#define	TISCI_DEV_TIMER10 46U

#define	TISCI_DEV_TIMER11 47U

#define	TISCI_DEV_ECAP0 51U

#define	TISCI_DEV_ECAP1 52U

#define	TISCI_DEV_ECAP2 53U

#define	TISCI_DEV_MMCSD0 58U

#define	TISCI_DEV_WKUP_GTC0 61U

#define	TISCI_DEV_ESM0 63U

#define	TISCI_DEV_WKUP_ESM0 64U

#define	TISCI_DEV_FSS1 73U

#define	TISCI_DEV_FSS1_FSAS_0 74U

#define	TISCI_DEV_FSS1_OSPI_0 75U

#define	TISCI_DEV_GPIO0 77U

#define	TISCI_DEV_GPIO1 78U

#define	TISCI_DEV_MCU_GPIO0 79U

#define	TISCI_DEV_LED0 83U

#define	TISCI_DEV_DDPA0 85U

#define	TISCI_DEV_EPWM0 86U

#define	TISCI_DEV_EPWM1 87U

#define	TISCI_DEV_EPWM2 88U

#define	TISCI_DEV_WKUP_VTM0 95U

#define	TISCI_DEV_MAILBOX0 96U

#define	TISCI_DEV_MCAN0 98U

#define	TISCI_DEV_MCAN1 99U

#define	TISCI_DEV_I2C0 102U

#define	TISCI_DEV_I2C1 103U

#define	TISCI_DEV_I2C2 104U

#define	TISCI_DEV_I2C3 105U

#define	TISCI_DEV_WKUP_I2C0 107U

#define	TISCI_DEV_WKUP_TIMER0 110U

#define	TISCI_DEV_WKUP_TIMER1 111U

#define	TISCI_DEV_WKUP_UART0 114U

#define	TISCI_DEV_MCRC64_0 116U

#define	TISCI_DEV_WKUP_RTCSS0 117U

#define	TISCI_DEV_WKUP_R5FSS0_SS0 118U

#define	TISCI_DEV_WKUP_R5FSS0 119U

#define	TISCI_DEV_WKUP_R5FSS0_CORE0 121U

#define	TISCI_DEV_RTI0 127U

#define	TISCI_DEV_RTI1 128U

#define	TISCI_DEV_RTI2 130U

#define	TISCI_DEV_RTI3 131U

#define	TISCI_DEV_WKUP_RTI0 132U

#define	TISCI_DEV_PSCSS0 139U

#define	TISCI_DEV_WKUP_PSC0 140U

#define	TISCI_DEV_MCSPI0 141U

#define	TISCI_DEV_MCSPI1 142U

#define	TISCI_DEV_MCSPI2 143U

#define	TISCI_DEV_MCSPI3 144U

#define	TISCI_DEV_MCSPI4 145U

#define	TISCI_DEV_UART0 146U

#define	TISCI_DEV_SPINLOCK0 150U

#define	TISCI_DEV_UART1 152U

#define	TISCI_DEV_UART2 153U

#define	TISCI_DEV_UART3 154U

#define	TISCI_DEV_UART4 155U

#define	TISCI_DEV_UART5 156U

#define	TISCI_DEV_BOARD0 157U

#define	TISCI_DEV_UART6 158U

#define	TISCI_DEV_USB0 161U

#define	TISCI_DEV_WKUP_PBIST0 165U

#define	TISCI_DEV_DEBUGSS0 171U

#define	TISCI_DEV_WKUP_DEEPSLEEP_SOURCES0 176U

#define	TISCI_DEV_MAIN_USB0_ISO_VD 178U

#define	TISCI_DEV_MCU_MCU_16FF0 180U

#define	TISCI_DEV_DCC6 183U

#define	TISCI_DEV_MCASP0 190U

#define	TISCI_DEV_MCASP1 191U

#define	TISCI_DEV_MCASP2 192U

#define	TISCI_DEV_CLK_32K_RC_SEL_DEV_VD 193U

#define	TISCI_DEV_CPT2_AGGR1 194U

#define	TISCI_DEV_CPT2_AGGR0 195U

#define	TISCI_DEV_CPT2_AGGR2 196U

#define	TISCI_DEV_MCU_DCC1 197U

#define	TISCI_DEV_RTI4 205U

#define	TISCI_DEV_C7X256V0 207U

#define	TISCI_DEV_C7X256V0_C7XV_CORE_0 208U

#define	TISCI_DEV_C7X256V0_CORE0 209U

#define	TISCI_DEV_C7X256V0_CLEC 210U

#define	TISCI_DEV_C7X256V0_CLK 211U

#define	TISCI_DEV_C7X256V0_DEBUG 212U

#define	TISCI_DEV_C7X256V0_GICSS 213U

#define	TISCI_DEV_C7X256V0_PBIST 214U

#define	TISCI_DEV_WKUP_CLKOUT_SEL_DEV_VD 226U

#define	TISCI_DEV_MCU_OBSCLK_MUX_SEL_DEV_VD 227U

#define	TISCI_DEV_OBSCLK0_MUX_SEL_DEV_VD 228U

#define	TISCI_DEV_DCC7 229U

#define	TISCI_DEV_DCC8 230U

#define	TISCI_DEV_ATL0 246U

#define	TISCI_DEV_PBIST1 254U

#define	TISCI_DEV_MCASP3 255U

#define	TISCI_DEV_MCASP4 256U

#define	TISCI_DEV_I2C4 257U

#define	TISCI_DEV_RTI5 263U

#define	TISCI_DEV_C7X256V1 267U

#define	TISCI_DEV_C7X256V1_C7XV_CORE_0 268U

#define	TISCI_DEV_C7X256V1_CORE0 269U

#define	TISCI_DEV_C7X256V1_CLEC 270U

#define	TISCI_DEV_C7X256V1_CLK 271U

#define	TISCI_DEV_C7X256V1_DEBUG 272U

#define	TISCI_DEV_C7X256V1_GICSS 273U

#define	TISCI_DEV_C7X256V1_PBIST 274U

#define	TISCI_DEV_TIMER12 288U

#define	TISCI_DEV_TIMER13 289U

#define	TISCI_DEV_TIMER14 290U

#define	TISCI_DEV_TIMER15 291U

#define	TISCI_DEV_ECAP3 292U

#define	TISCI_DEV_ECAP4 293U

#define	TISCI_DEV_ECAP5 294U

#define	TISCI_DEV_FSS1_HYPERBUS1P0_0 295U

#define	TISCI_DEV_FSS1_MISC_0 296U

#define	TISCI_DEV_FSS1_OSPI_1 297U

#define	TISCI_DEV_FSS0 298U

#define	TISCI_DEV_AASRC0 299U

#define	TISCI_DEV_AASRC1 300U

#define	TISCI_DEV_PBIST0 301U

#define	TISCI_DEV_PBIST2 302U

#define	TISCI_DEV_PBIST3 303U

#define	TISCI_DEV_PBIST4 304U

#define	TISCI_DEV_PBIST5 305U

#define	TISCI_DEV_PBIST6 306U

#define	TISCI_DEV_PBIST7 307U

#define	TISCI_DEV_PBIST8 308U

#define	TISCI_DEV_WKUP_PBIST1 309U

#define	TISCI_DEV_MCAN2 310U

#define	TISCI_DEV_MCAN3 311U

#define	TISCI_DEV_MCAN4 312U

#define	TISCI_DEV_MLB0 313U

#define	TISCI_DEV_I2C5 314U

#define	TISCI_DEV_I2C6 315U

#define	TISCI_DEV_R5FSS0 316U

#define	TISCI_DEV_R5FSS1 317U

#define	TISCI_DEV_R5FSS0_CORE0 318U

#define	TISCI_DEV_R5FSS0_CORE1 319U

#define	TISCI_DEV_R5FSS1_CORE0 320U

#define	TISCI_DEV_R5FSS1_CORE1 321U

#define	TISCI_DEV_RL2_OF_CBA4_0 322U

#define	TISCI_DEV_RL2_OF_CBA4_1 323U

#define	TISCI_DEV_RL2_OF_CBA4_2 324U

#define	TISCI_DEV_RL2_OF_CBA4_3 325U

#define	TISCI_DEV_RL2_CORE0_CFG0 326U

#define	TISCI_DEV_RL2_CORE0_CFG1 327U

#define	TISCI_DEV_RL2_CORE1_CFG0 328U

#define	TISCI_DEV_RL2_CORE1_CFG1 329U

#define	TISCI_DEV_MCASP0_AUXCLK_SEL_DEV_VD 330U

#define	TISCI_DEV_MCASP1_AUXCLK_SEL_DEV_VD 331U

#define	TISCI_DEV_MCASP2_AUXCLK_SEL_DEV_VD 332U

#define	TISCI_DEV_MCASP3_AUXCLK_SEL_DEV_VD 333U

#define	TISCI_DEV_MCASP4_AUXCLK_SEL_DEV_VD 334U

#define	TISCI_DEV_MCASP0_LOCAL_AUXCLK_SEL_DEV_VD 335U

#define	TISCI_DEV_MCASP1_LOCAL_AUXCLK_SEL_DEV_VD 336U

#define	TISCI_DEV_MCASP2_LOCAL_AUXCLK_SEL_DEV_VD 337U

#define	TISCI_DEV_MCASP3_LOCAL_AUXCLK_SEL_DEV_VD 338U

#define	TISCI_DEV_MCASP4_LOCAL_AUXCLK_SEL_DEV_VD 339U

Macros