HYPERBUS_MemTiming Struct Reference

Detailed Description

Register structure for the Memory Timing Register.

Data Fields
uint32_t	latency
uint32_t	writeCSHold
uint32_t	readCSHold
uint32_t	writeCSSetup
uint32_t	readCSSetup
uint32_t	writeCSHigh
uint32_t	readCSHigh

Field Documentation

latency

uint32_t HYPERBUS_MemTiming::latency

< Initial latency for read/write access, only applicable for HyperRAM CS# hold time for write to CS# deassertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

writeCSHold

uint32_t HYPERBUS_MemTiming::writeCSHold

CS# hold time for read to CS# deassertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

readCSHold

uint32_t HYPERBUS_MemTiming::readCSHold

CS# setup time for write from CS# assertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

writeCSSetup

uint32_t HYPERBUS_MemTiming::writeCSSetup

CS# setup time for read from CS# assertion Range 0 to 15 0 means 1 Cycle 15 means 16 Cycles

readCSSetup

uint32_t HYPERBUS_MemTiming::readCSSetup

CS# high time for write between operations Range 0 to 15 0 means 1.5 Cycle 15 means 16.5 Cycles

writeCSHigh

uint32_t HYPERBUS_MemTiming::writeCSHigh

CS# high time for read between operations Range 0 to 15 0 means 1.5 Cycle 15 means 16.5 Cycles

readCSHigh

uint32_t HYPERBUS_MemTiming::readCSHigh