sdl_ecc_soc.h File Reference

Introduction

Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable.

declarations for SDL ECC interface.

Go to the source code of this file.

Macros
#define	SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (15U)
#define	SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (16U)
#define	SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)
#define	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)
#define	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)
#define	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)
#define	SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (55U)

Variables
static SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_Base_Address_TOTAL_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX]
static const SDL_MemConfig_t	SDL_C7X256V1_ECC_AGGR_MemEntries [SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries [SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries [SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_MemEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_MemEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries [SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_MemEntries [SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries [SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_MemEntries [SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_groupEntries [SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_groupEntries [SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries [SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_C7X256V0_ECC_AGGR_MemEntries [SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries [SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries [SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_MemEntries [SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_MemEntries [SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_MemEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SMS0_SMS_HSM_ECC_MemEntries [SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries [SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SMS0_SMS_TIFS_ECC_MemEntries [SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries [SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_MemEntries [SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries [SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries [SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries [SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries [SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries [SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_MemEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_MemEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_MemEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_MemEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries [SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MemEntries [SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries [SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_DMASS0_ECC_AGGR_0_MemEntries [SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_MemEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_MemEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_MemEntries [SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_groupEntries [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_RAMIdEntry_t	SDL_C7X256V1_ECC_AGGR_RamIdTable [SDL_C7X256V1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable [SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RamIdTable [SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RamIdTable [SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable [SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RamIdTable [SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable [SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RamIdTable [SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RamIdTable [SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable [SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable [SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_C7X256V0_ECC_AGGR_RamIdTable [SDL_C7X256V0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RamIdTable [SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RamIdTable [SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RamIdTable [SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable [SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable [SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SMS0_SMS_HSM_ECC_RamIdTable [SDL_SMS0_SMS_HSM_ECC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SMS0_SMS_TIFS_ECC_RamIdTable [SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RamIdTable [SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable [SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable [SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable [SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable [SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable [SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable [SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable [SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable [SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable [SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RamIdTable [SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RamIdTable [SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable [SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RamIdTable [SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable [SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable [SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable [SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DMASS0_ECC_AGGR_0_RamIdTable [SDL_DMASS0_ECC_AGGR_0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RamIdTable [SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RamIdTable [SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RamIdTable [SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RamIdTable [SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RamIdTable [SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_NUM_RAMS]
static const SDL_EccAggrEntry_t	SDL_ECC_aggrTable [SDL_ECC_MEMTYPE_MAX]

Macro Definition Documentation

SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)

SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (15U)

SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (16U)

SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)

SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (30U)

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES

#define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES

#define SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (0U)

SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES   (55U)

Variable Documentation

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]

static

SDL_ECC_aggrTransBaseAddressTable

SDL_ecc_aggrRegs* SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]

extern

SDL_C7X256V1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_C7X256V1_ECC_AGGR_MemEntries[SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
      SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
      SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_C7X256V1_ECC_AGGR

SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0 RAM ID

SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0 RAM ID

SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0 RAM ID

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0 RAM ID

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0 RAM ID

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0 RAM ID

SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x00000000u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_MemEntries

const SDL_MemConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_MemEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
      SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
      SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_IDOM0_PULSAR_PLL_ECC_AGGR10

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_MemEntries

const SDL_MemConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_MemEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
      SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
      SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_IDOM0_PULSAR_PLL_ECC_AGGR8

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_MemEntries[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR

SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_MemEntries[SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_FSS1_FSS_HB_WRAP_ECC_AGGR

SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC RAM ID

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_groupEntries[SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
    { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
      SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_groupEntries[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0 RAM ID

SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_MemEntries[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR

SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR

SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR

SDL_C7X256V0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_C7X256V0_ECC_AGGR_MemEntries[SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
      SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
      SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_C7X256V0_ECC_AGGR

SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_groupEntries[SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0 RAM ID

SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0 RAM ID

SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0 RAM ID

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0 RAM ID

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0 RAM ID

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0 RAM ID

SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries

const SDL_GrpChkConfig_t SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_groupEntries[SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0 RAM ID

SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR

SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM

SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_MemEntries[SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_MemEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_groupEntries[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
    { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC RAM ID

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_MemEntries

const SDL_MemConfig_t SDL_SMS0_SMS_HSM_ECC_MemEntries[SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_SMS0_SMS_HSM_ECC

SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL RAM ID

SDL_SMS0_SMS_TIFS_ECC_MemEntries

const SDL_MemConfig_t SDL_SMS0_SMS_TIFS_ECC_MemEntries[SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_SMS0_SMS_TIFS_ECC

SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1 RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC RAM ID

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_groupEntries[SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL RAM ID

SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_MemEntries[SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_ID, 0u,
      SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_SIZE, 4u,
      SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR

SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_MemEntries[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x41880000u,
      SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MemEntries[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID, 0u,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_SIZE, 4u,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_MemEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_MemEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0 RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC RAM ID

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_MemEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL RAM ID

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL RAM ID

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_MemEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0 RAM ID

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC RAM ID

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_groupEntries[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL RAM ID

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC RAM ID

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL RAM ID

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_MemEntries[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR

SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MemEntries[SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
      SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR

SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_MemEntries[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC RAM ID

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20738000u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20728000u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20718000u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_DMASS0_ECC_AGGR_0_MemEntries

const SDL_MemConfig_t SDL_DMASS0_ECC_AGGR_0_MemEntries[SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES]

static

---

This structure holds the memory config for each memory subtype SDL_DMASS0_ECC_AGGR_0

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20748000u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

---

This structure holds the memory config for each memory subtype SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_MemEntries

const SDL_MemConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_MemEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_IDOM1_PULSAR_PLL_ECC_AGGR9

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_MemEntries

const SDL_MemConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_MemEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_IDOM1_PULSAR_PLL_ECC_AGGR11

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC RAM ID

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_groupEntries[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0 RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1 RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2 RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC RAM ID

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_groupEntries[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL RAM ID

SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_MemEntries[SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_ID, 0u,
      SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)false) },
}

---

This structure holds the memory config for each memory subtype SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_groupEntries[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
}

---

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL RAM ID

SDL_C7X256V1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_C7X256V1_ECC_AGGR_RamIdTable[SDL_C7X256V1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_C7X256V1_ECC_AGGR

SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR

SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RamIdTable[SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_PULSAR_PLL_ECC_AGGR10

SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RamIdTable[SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_PULSAR_PLL_ECC_AGGR8

SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR

SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RamIdTable[SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR

SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RamIdTable[SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS1_FSS_HB_WRAP_ECC_AGGR

SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR

SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RamIdTable[SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_RAM_ID,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_groupEntries },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR

SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR

SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RamIdTable[SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR

SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR

SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR

SDL_C7X256V0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_C7X256V0_ECC_AGGR_RamIdTable[SDL_C7X256V0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_C7X256V0_ECC_AGGR

SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR

SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM

SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM

SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RamIdTable[SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_ID,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_ID,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR

SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RamIdTable[SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR

SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable[SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR

SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RamIdTable[SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR

SDL_SMS0_SMS_HSM_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_SMS0_SMS_HSM_ECC_RamIdTable[SDL_SMS0_SMS_HSM_ECC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SMS0_SMS_HSM_ECC

SDL_SMS0_SMS_TIFS_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_SMS0_SMS_TIFS_ECC_RamIdTable[SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_SMS0_SMS_TIFS_ECC

SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_ID,
      SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_INJECT_TYPE,
      SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR

SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR

SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR

SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RamIdTable[SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
    { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
      SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR

SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
      SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR

SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RamIdTable[SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_INJECT_TYPE,
      SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR

SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR

SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR

SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR

SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RamIdTable[SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR

SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_groupEntries },
    { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR

SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR

SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RamIdTable[SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR

SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RamIdTable[SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR

SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RamIdTable[SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR

SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable[SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR

SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RamIdTable[SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_groupEntries },
    { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
      SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR

SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_DMASS0_ECC_AGGR_0_RamIdTable

const SDL_RAMIdEntry_t SDL_DMASS0_ECC_AGGR_0_RamIdTable[SDL_DMASS0_ECC_AGGR_0_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_DMASS0_ECC_AGGR_0

SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR

SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RamIdTable[SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_PULSAR_PLL_ECC_AGGR9

SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RamIdTable

const SDL_RAMIdEntry_t SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RamIdTable[SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_IDOM1_PULSAR_PLL_ECC_AGGR11

SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RamIdTable[SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR

SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RamIdTable[SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_ID,
      SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

---

This structure holds the list of Ram Ids for each memory subtype in SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR

SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RamIdTable[SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_NUM_RAMS]

static

---

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR

SDL_ECC_aggrTable

const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]

static

SDL_ECC_aggrTable