sciclient_irq_rm.c File Reference

Introduction

irq_tree for AM275X

Variables
static struct Sciclient_rmIaUsedMapping	rom_usage_DMASS0_INTAGGR_0 [1U]
uint8_t	vint_usage_count_DMASS0_INTAGGR_0 [184U] = {0}
struct Sciclient_rmIaInst	gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
struct Sciclient_rmIrInst	gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE1_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE0_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE1_intr_32_47
const struct Sciclient_rmIrqIf	MAIN_GPIO_INTROUTER0_outp_48_57_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_25
const struct Sciclient_rmIrqIf *const	tisci_if_MAIN_GPIO_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MAIN_GPIO_INTROUTER0
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_12_15_to_WKUP_R5FSS0_CORE0_intr_50_53
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_100_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_100_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_100_107
const struct Sciclient_rmIrqIf	MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_100_107
const struct Sciclient_rmIrqIf *const	tisci_if_MCU_MCU_GPIO_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCU_MCU_GPIO_INTROUTER0
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_8_8_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_9_9_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf	TIMESYNC_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf *const	tisci_if_TIMESYNC_INTROUTER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMESYNC_INTROUTER0
const struct Sciclient_rmIrqIf	CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTROUTER0_in_16_16
const struct Sciclient_rmIrqIf	CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTROUTER0_in_17_17
const struct Sciclient_rmIrqIf	CPSW0_cpts_sync_3_3_to_TIMESYNC_INTROUTER0_in_18_18
const struct Sciclient_rmIrqIf *const	tisci_if_CPSW0 []
static const struct Sciclient_rmIrqNode	tisci_irq_CPSW0
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE0_intr_64_79
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE0_intr_153_160
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE1_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE1_intr_64_79
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE1_intr_153_160
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V0_CLEC_gic_spi_96_103
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V1_CLEC_gic_spi_96_103
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE0_intr_153_160
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE1_intr_8_15
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE1_intr_64_79
const struct Sciclient_rmIrqIf	DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE1_intr_153_160
const struct Sciclient_rmIrqIf *const	tisci_if_DMASS0_INTAGGR_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf	TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_216_216
const struct Sciclient_rmIrqIf	TIMER0_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_0_0
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER0
const struct Sciclient_rmIrqIf	TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_217_217
const struct Sciclient_rmIrqIf	TIMER1_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_1_1
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER1 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER1
const struct Sciclient_rmIrqIf	TIMER2_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_218_218
const struct Sciclient_rmIrqIf	TIMER2_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_2_2
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER2 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER2
const struct Sciclient_rmIrqIf	TIMER3_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_219_219
const struct Sciclient_rmIrqIf	TIMER3_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_3_3
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER3 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER3
const struct Sciclient_rmIrqIf	TIMER4_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_220_220
const struct Sciclient_rmIrqIf	TIMER4_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_4_4
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER4 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER4
const struct Sciclient_rmIrqIf	TIMER5_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_221_221
const struct Sciclient_rmIrqIf	TIMER5_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_5_5
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER5 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER5
const struct Sciclient_rmIrqIf	TIMER6_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_222_222
const struct Sciclient_rmIrqIf	TIMER6_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_6_6
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER6 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER6
const struct Sciclient_rmIrqIf	TIMER7_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_223_223
const struct Sciclient_rmIrqIf	TIMER7_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_7_7
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER7 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER7
const struct Sciclient_rmIrqIf	TIMER8_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_224_224
const struct Sciclient_rmIrqIf	TIMER8_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_8_8
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER8 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER8
const struct Sciclient_rmIrqIf	TIMER9_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_225_225
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER9 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER9
const struct Sciclient_rmIrqIf	TIMER10_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_226_226
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER10 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER10
const struct Sciclient_rmIrqIf	TIMER11_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_227_227
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER11 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER11
const struct Sciclient_rmIrqIf	WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_INTROUTER0_in_11_11
const struct Sciclient_rmIrqIf *const	tisci_if_WKUP_GTC0 []
static const struct Sciclient_rmIrqNode	tisci_irq_WKUP_GTC0
const struct Sciclient_rmIrqIf	GPIO0_gpio_0_52_to_MAIN_GPIO_INTROUTER0_in_0_52
const struct Sciclient_rmIrqIf	GPIO0_gpio_55_59_to_MAIN_GPIO_INTROUTER0_in_55_59
const struct Sciclient_rmIrqIf	GPIO0_gpio_62_92_to_MAIN_GPIO_INTROUTER0_in_62_92
const struct Sciclient_rmIrqIf	GPIO0_gpio_bank_93_98_to_MAIN_GPIO_INTROUTER0_in_192_197
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO0
const struct Sciclient_rmIrqIf	GPIO1_gpio_0_50_to_MAIN_GPIO_INTROUTER0_in_96_146
const struct Sciclient_rmIrqIf	GPIO1_gpio_72_72_to_MAIN_GPIO_INTROUTER0_in_168_168
const struct Sciclient_rmIrqIf	GPIO1_gpio_74_85_to_MAIN_GPIO_INTROUTER0_in_170_181
const struct Sciclient_rmIrqIf	GPIO1_gpio_bank_86_91_to_MAIN_GPIO_INTROUTER0_in_200_205
const struct Sciclient_rmIrqIf *const	tisci_if_GPIO1 []
static const struct Sciclient_rmIrqNode	tisci_irq_GPIO1
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_0_16_to_MCU_MCU_GPIO_INTROUTER0_in_0_16
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_19_25_to_MCU_MCU_GPIO_INTROUTER0_in_19_25
const struct Sciclient_rmIrqIf	MCU_GPIO0_gpio_bank_26_27_to_MCU_MCU_GPIO_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf *const	tisci_if_MCU_GPIO0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCU_GPIO0
const struct Sciclient_rmIrqIf	EPWM0_epwm_synco_o_0_0_to_TIMESYNC_INTROUTER0_in_9_9
const struct Sciclient_rmIrqIf *const	tisci_if_EPWM0 []
static const struct Sciclient_rmIrqNode	tisci_irq_EPWM0
const struct Sciclient_rmIrqIf	WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_214_214
const struct Sciclient_rmIrqIf *const	tisci_if_WKUP_TIMER0 []
static const struct Sciclient_rmIrqNode	tisci_irq_WKUP_TIMER0
const struct Sciclient_rmIrqIf	WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_215_215
const struct Sciclient_rmIrqIf *const	tisci_if_WKUP_TIMER1 []
static const struct Sciclient_rmIrqNode	tisci_irq_WKUP_TIMER1
const struct Sciclient_rmIrqIf	MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7
const struct Sciclient_rmIrqIf	MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31
const struct Sciclient_rmIrqIf *const	tisci_if_MCRC64_0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCRC64_0
const struct Sciclient_rmIrqIf	DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27
const struct Sciclient_rmIrqIf *const	tisci_if_DEBUGSS0 []
static const struct Sciclient_rmIrqNode	tisci_irq_DEBUGSS0
const struct Sciclient_rmIrqIf	MCASP0_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1
const struct Sciclient_rmIrqIf *const	tisci_if_MCASP0 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCASP0
const struct Sciclient_rmIrqIf	MCASP1_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2
const struct Sciclient_rmIrqIf *const	tisci_if_MCASP1 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCASP1
const struct Sciclient_rmIrqIf	MCASP2_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3
const struct Sciclient_rmIrqIf *const	tisci_if_MCASP2 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCASP2
const struct Sciclient_rmIrqIf	MCASP3_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4
const struct Sciclient_rmIrqIf *const	tisci_if_MCASP3 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCASP3
const struct Sciclient_rmIrqIf	MCASP4_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5
const struct Sciclient_rmIrqIf *const	tisci_if_MCASP4 []
static const struct Sciclient_rmIrqNode	tisci_irq_MCASP4
const struct Sciclient_rmIrqIf	TIMER12_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_228_228
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER12 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER12
const struct Sciclient_rmIrqIf	TIMER13_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_229_229
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER13 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER13
const struct Sciclient_rmIrqIf	TIMER14_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_230_230
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER14 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER14
const struct Sciclient_rmIrqIf	TIMER15_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_231_231
const struct Sciclient_rmIrqIf *const	tisci_if_TIMER15 []
static const struct Sciclient_rmIrqNode	tisci_irq_TIMER15
const struct Sciclient_rmIrqNode *const	gRmIrqTree [RM_IRQ_TREE_MAX]
const uint32_t	gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])

Variable Documentation

rom_usage_DMASS0_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[1U]

static

Initial value:

= {
    {
        .event = 30U,
        .cleared = false,
    },
}

vint_usage_count_DMASS0_INTAGGR_0

uint8_t vint_usage_count_DMASS0_INTAGGR_0[184U] = {0}

gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]

Initial value:

=
{
    {
        .dev_id             = TISCI_DEV_DMASS0_INTAGGR_0,
        .imap               = 0x48100000,
        .sevt_offset        = 0u,
        .n_sevt             = 1536u,
        .n_vint             = 184,
        .vint_usage_count   = &vint_usage_count_DMASS0_INTAGGR_0[0],
        .v0_b0_evt          = 0,
        .rom_usage = &rom_usage_DMASS0_INTAGGR_0[0U],
        .n_rom_usage = 1,
    }
}

gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]

Initial value:

=
{
    {
        .dev_id         = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
        .cfg            = 0xa00000,
        .n_inp          = 232u,
        .n_outp         = 80u,
        .inp0_mapping   = 0,
        .rom_usage      = NULL,
        .n_rom_usage    = 0U,
    },
    {
        .dev_id         = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
        .cfg            = 0x4210000,
        .n_inp          = 32u,
        .n_outp         = 32u,
        .inp0_mapping   = 0,
        .rom_usage      = NULL,
        .n_rom_usage    = 0U,
    },
    {
        .dev_id         = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
        .cfg            = 0xa40000,
        .n_inp          = 24u,
        .n_outp         = 32u,
        .inp0_mapping   = 0,
        .rom_usage      = NULL,
        .n_rom_usage    = 0U,
    },
}

MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_C7X256V1_CLEC,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE0_intr_32_47

Initial value:

= {
    .lbase = 16,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE1_intr_32_47

Initial value:

= {
    .lbase = 16,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE0_intr_32_47

Initial value:

= {
    .lbase = 32,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE1_intr_32_47

Initial value:

= {
    .lbase = 32,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 32,
}

MAIN_GPIO_INTROUTER0_outp_48_57_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_25

const struct Sciclient_rmIrqIf MAIN_GPIO_INTROUTER0_outp_48_57_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_25

Initial value:

= {
    .lbase = 48,
    .len = 10,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 16,
}

tisci_if_MAIN_GPIO_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_MAIN_GPIO_INTROUTER0[]

Initial value:

= {
    &MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V0_CLEC_gic_spi_32_47,
    &MAIN_GPIO_INTROUTER0_outp_0_15_to_C7X256V1_CLEC_gic_spi_32_47,
    &MAIN_GPIO_INTROUTER0_outp_0_15_to_WKUP_R5FSS0_CORE0_intr_32_47,
    &MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE0_intr_32_47,
    &MAIN_GPIO_INTROUTER0_outp_16_31_to_R5FSS0_CORE1_intr_32_47,
    &MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE0_intr_32_47,
    &MAIN_GPIO_INTROUTER0_outp_32_47_to_R5FSS1_CORE1_intr_32_47,
    &MAIN_GPIO_INTROUTER0_outp_48_57_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_25,
}

tisci_irq_MAIN_GPIO_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIO_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .n_if = 8,
    .p_if = &tisci_if_MAIN_GPIO_INTROUTER0[0],
}

MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 104,
}

MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_C7X256V1_CLEC,
    .rbase = 104,
}

MCU_MCU_GPIO_INTROUTER0_outp_12_15_to_WKUP_R5FSS0_CORE0_intr_50_53

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_12_15_to_WKUP_R5FSS0_CORE0_intr_50_53

Initial value:

= {
    .lbase = 12,
    .len = 4,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 50,
}

MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 104,
}

MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 88,
}

MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 92,
}

MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99

Initial value:

= {
    .lbase = 8,
    .len = 4,
    .rid = TISCI_DEV_WKUP_ESM0,
    .rbase = 96,
}

MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_100_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_100_107

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 100,
}

MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_100_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_100_107

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 100,
}

MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_100_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_100_107

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 100,
}

MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_100_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_100_107

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 100,
}

tisci_if_MCU_MCU_GPIO_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_MCU_GPIO_INTROUTER0[]

Initial value:

= {
    &MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V0_CLEC_gic_spi_104_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_C7X256V1_CLEC_gic_spi_104_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_12_15_to_WKUP_R5FSS0_CORE0_intr_50_53,
    &MCU_MCU_GPIO_INTROUTER0_outp_0_3_to_WKUP_R5FSS0_CORE0_intr_104_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event0_88_91,
    &MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event1_92_95,
    &MCU_MCU_GPIO_INTROUTER0_outp_8_11_to_WKUP_ESM0_esm_pls_event2_96_99,
    &MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_100_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_100_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_100_107,
    &MCU_MCU_GPIO_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_100_107,
}

tisci_irq_MCU_MCU_GPIO_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIO_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .n_if = 11,
    .p_if = &tisci_if_MCU_MCU_GPIO_INTROUTER0[0],
}

TIMESYNC_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

Initial value:

= {
    .lbase = 0,
    .len = 8,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 8,
}

TIMESYNC_INTROUTER0_outl_8_8_to_CPSW0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_8_8_to_CPSW0_cpts_hw1_push_0_0

Initial value:

= {
    .lbase = 8,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 0,
}

TIMESYNC_INTROUTER0_outl_9_9_to_CPSW0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_9_9_to_CPSW0_cpts_hw2_push_1_1

Initial value:

= {
    .lbase = 9,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 1,
}

TIMESYNC_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw3_push_2_2

Initial value:

= {
    .lbase = 10,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 2,
}

TIMESYNC_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw4_push_3_3

Initial value:

= {
    .lbase = 11,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 3,
}

TIMESYNC_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw5_push_4_4

Initial value:

= {
    .lbase = 12,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 4,
}

TIMESYNC_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw6_push_5_5

Initial value:

= {
    .lbase = 13,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 5,
}

TIMESYNC_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw7_push_6_6

Initial value:

= {
    .lbase = 14,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 6,
}

TIMESYNC_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw8_push_7_7

Initial value:

= {
    .lbase = 15,
    .len = 1,
    .rid = TISCI_DEV_CPSW0,
    .rbase = 7,
}

tisci_if_TIMESYNC_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_INTROUTER0[]

Initial value:

= {
    &TIMESYNC_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15,
    &TIMESYNC_INTROUTER0_outl_8_8_to_CPSW0_cpts_hw1_push_0_0,
    &TIMESYNC_INTROUTER0_outl_9_9_to_CPSW0_cpts_hw2_push_1_1,
    &TIMESYNC_INTROUTER0_outl_10_10_to_CPSW0_cpts_hw3_push_2_2,
    &TIMESYNC_INTROUTER0_outl_11_11_to_CPSW0_cpts_hw4_push_3_3,
    &TIMESYNC_INTROUTER0_outl_12_12_to_CPSW0_cpts_hw5_push_4_4,
    &TIMESYNC_INTROUTER0_outl_13_13_to_CPSW0_cpts_hw6_push_5_5,
    &TIMESYNC_INTROUTER0_outl_14_14_to_CPSW0_cpts_hw7_push_6_6,
    &TIMESYNC_INTROUTER0_outl_15_15_to_CPSW0_cpts_hw8_push_7_7,
}

tisci_irq_TIMESYNC_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_INTROUTER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .n_if = 9,
    .p_if = &tisci_if_TIMESYNC_INTROUTER0[0],
}

CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0

const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 0,
}

CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTROUTER0_in_16_16

const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTROUTER0_in_16_16

Initial value:

= {
    .lbase = 1,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 16,
}

CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTROUTER0_in_17_17

const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTROUTER0_in_17_17

Initial value:

= {
    .lbase = 2,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 17,
}

CPSW0_cpts_sync_3_3_to_TIMESYNC_INTROUTER0_in_18_18

const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_INTROUTER0_in_18_18

Initial value:

= {
    .lbase = 3,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 18,
}

tisci_if_CPSW0

const struct Sciclient_rmIrqIf* const tisci_if_CPSW0[]

Initial value:

= {
    &CPSW0_cpts_comp_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_0,
    &CPSW0_cpts_genf0_1_1_to_TIMESYNC_INTROUTER0_in_16_16,
    &CPSW0_cpts_genf1_2_2_to_TIMESYNC_INTROUTER0_in_17_17,
    &CPSW0_cpts_sync_3_3_to_TIMESYNC_INTROUTER0_in_18_18,
}

tisci_irq_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_CPSW0

static

Initial value:

= {
    .id = TISCI_DEV_CPSW0,
    .n_if = 4,
    .p_if = &tisci_if_CPSW0[0],
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE0_intr_8_15

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE0_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE0_intr_64_79

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE0_intr_153_160

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE0_intr_153_160

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE0,
    .rbase = 153,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE1_intr_8_15

Initial value:

= {
    .lbase = 16,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE1_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE1_intr_64_79

Initial value:

= {
    .lbase = 0,
    .len = 16,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE1_intr_153_160

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE1_intr_153_160

Initial value:

= {
    .lbase = 24,
    .len = 8,
    .rid = TISCI_DEV_R5FSS1_CORE1,
    .rbase = 153,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V0_CLEC_gic_spi_96_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V0_CLEC_gic_spi_96_103

Initial value:

= {
    .lbase = 32,
    .len = 8,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 96,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31

Initial value:

= {
    .lbase = 84,
    .len = 16,
    .rid = TISCI_DEV_C7X256V0_CLEC,
    .rbase = 16,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V1_CLEC_gic_spi_96_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V1_CLEC_gic_spi_96_103

Initial value:

= {
    .lbase = 32,
    .len = 8,
    .rid = TISCI_DEV_C7X256V1_CLEC,
    .rbase = 96,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31

Initial value:

= {
    .lbase = 100,
    .len = 16,
    .rid = TISCI_DEV_C7X256V1_CLEC,
    .rbase = 16,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15

Initial value:

= {
    .lbase = 72,
    .len = 8,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95

Initial value:

= {
    .lbase = 40,
    .len = 32,
    .rid = TISCI_DEV_WKUP_R5FSS0_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE0_intr_8_15

Initial value:

= {
    .lbase = 168,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79

Initial value:

= {
    .lbase = 152,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE0_intr_153_160

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE0_intr_153_160

Initial value:

= {
    .lbase = 176,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE0,
    .rbase = 153,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE1_intr_8_15

Initial value:

= {
    .lbase = 168,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 8,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE1_intr_64_79

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE1_intr_64_79

Initial value:

= {
    .lbase = 152,
    .len = 16,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 64,
}

DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE1_intr_153_160

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE1_intr_153_160

Initial value:

= {
    .lbase = 176,
    .len = 8,
    .rid = TISCI_DEV_R5FSS0_CORE1,
    .rbase = 153,
}

tisci_if_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqIf* const tisci_if_DMASS0_INTAGGR_0[]

Initial value:

= {
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE0_intr_64_79,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE0_intr_153_160,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_16_23_to_R5FSS1_CORE1_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_0_15_to_R5FSS1_CORE1_intr_64_79,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_24_31_to_R5FSS1_CORE1_intr_153_160,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V0_CLEC_gic_spi_96_103,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_84_99_to_C7X256V0_CLEC_soc_events_in_16_31,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_32_39_to_C7X256V1_CLEC_gic_spi_96_103,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_100_115_to_C7X256V1_CLEC_soc_events_in_16_31,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_WKUP_R5FSS0_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_WKUP_R5FSS0_CORE0_intr_64_95,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE0_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE0_intr_64_79,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE0_intr_153_160,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_168_175_to_R5FSS0_CORE1_intr_8_15,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_152_167_to_R5FSS0_CORE1_intr_64_79,
    &DMASS0_INTAGGR_0_intaggr_vintr_pend_176_183_to_R5FSS0_CORE1_intr_153_160,
}

tisci_irq_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0

static

Initial value:

= {
    .id = TISCI_DEV_DMASS0_INTAGGR_0,
    .n_if = 18,
    .p_if = &tisci_if_DMASS0_INTAGGR_0[0],
}

TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_216_216

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_216_216

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 216,
}

TIMER0_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_0_0

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_0_0

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 0,
}

tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]

Initial value:

= {
    &TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_216_216,
    &TIMER0_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_0_0,
}

tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0

static

Initial value:

= {
    .id = TISCI_DEV_TIMER0,
    .n_if = 2,
    .p_if = &tisci_if_TIMER0[0],
}

TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_217_217

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_217_217

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 217,
}

TIMER1_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_1_1

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_1_1

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 1,
}

tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]

Initial value:

= {
    &TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_217_217,
    &TIMER1_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_1_1,
}

tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1

static

Initial value:

= {
    .id = TISCI_DEV_TIMER1,
    .n_if = 2,
    .p_if = &tisci_if_TIMER1[0],
}

TIMER2_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_218_218

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_218_218

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 218,
}

TIMER2_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_2_2

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_2_2

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 2,
}

tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]

Initial value:

= {
    &TIMER2_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_218_218,
    &TIMER2_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_2_2,
}

tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2

static

Initial value:

= {
    .id = TISCI_DEV_TIMER2,
    .n_if = 2,
    .p_if = &tisci_if_TIMER2[0],
}

TIMER3_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_219_219

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_219_219

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 219,
}

TIMER3_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_3_3

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_3_3

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 3,
}

tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]

Initial value:

= {
    &TIMER3_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_219_219,
    &TIMER3_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_3_3,
}

tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3

static

Initial value:

= {
    .id = TISCI_DEV_TIMER3,
    .n_if = 2,
    .p_if = &tisci_if_TIMER3[0],
}

TIMER4_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_220_220

const struct Sciclient_rmIrqIf TIMER4_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_220_220

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 220,
}

TIMER4_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_4_4

const struct Sciclient_rmIrqIf TIMER4_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_4_4

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 4,
}

tisci_if_TIMER4

const struct Sciclient_rmIrqIf* const tisci_if_TIMER4[]

Initial value:

= {
    &TIMER4_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_220_220,
    &TIMER4_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_4_4,
}

tisci_irq_TIMER4

const struct Sciclient_rmIrqNode tisci_irq_TIMER4

static

Initial value:

= {
    .id = TISCI_DEV_TIMER4,
    .n_if = 2,
    .p_if = &tisci_if_TIMER4[0],
}

TIMER5_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_221_221

const struct Sciclient_rmIrqIf TIMER5_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_221_221

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 221,
}

TIMER5_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_5_5

const struct Sciclient_rmIrqIf TIMER5_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_5_5

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 5,
}

tisci_if_TIMER5

const struct Sciclient_rmIrqIf* const tisci_if_TIMER5[]

Initial value:

= {
    &TIMER5_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_221_221,
    &TIMER5_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_5_5,
}

tisci_irq_TIMER5

const struct Sciclient_rmIrqNode tisci_irq_TIMER5

static

Initial value:

= {
    .id = TISCI_DEV_TIMER5,
    .n_if = 2,
    .p_if = &tisci_if_TIMER5[0],
}

TIMER6_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_222_222

const struct Sciclient_rmIrqIf TIMER6_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_222_222

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 222,
}

TIMER6_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_6_6

const struct Sciclient_rmIrqIf TIMER6_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_6_6

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 6,
}

tisci_if_TIMER6

const struct Sciclient_rmIrqIf* const tisci_if_TIMER6[]

Initial value:

= {
    &TIMER6_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_222_222,
    &TIMER6_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_6_6,
}

tisci_irq_TIMER6

const struct Sciclient_rmIrqNode tisci_irq_TIMER6

static

Initial value:

= {
    .id = TISCI_DEV_TIMER6,
    .n_if = 2,
    .p_if = &tisci_if_TIMER6[0],
}

TIMER7_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_223_223

const struct Sciclient_rmIrqIf TIMER7_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_223_223

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 223,
}

TIMER7_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_7_7

const struct Sciclient_rmIrqIf TIMER7_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_7_7

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 7,
}

tisci_if_TIMER7

const struct Sciclient_rmIrqIf* const tisci_if_TIMER7[]

Initial value:

= {
    &TIMER7_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_223_223,
    &TIMER7_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_7_7,
}

tisci_irq_TIMER7

const struct Sciclient_rmIrqNode tisci_irq_TIMER7

static

Initial value:

= {
    .id = TISCI_DEV_TIMER7,
    .n_if = 2,
    .p_if = &tisci_if_TIMER7[0],
}

TIMER8_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_224_224

const struct Sciclient_rmIrqIf TIMER8_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_224_224

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 224,
}

TIMER8_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_8_8

const struct Sciclient_rmIrqIf TIMER8_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_8_8

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 8,
}

tisci_if_TIMER8

const struct Sciclient_rmIrqIf* const tisci_if_TIMER8[]

Initial value:

= {
    &TIMER8_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_224_224,
    &TIMER8_timer_pwm_0_0_to_TIMESYNC_INTROUTER0_in_8_8,
}

tisci_irq_TIMER8

const struct Sciclient_rmIrqNode tisci_irq_TIMER8

static

Initial value:

= {
    .id = TISCI_DEV_TIMER8,
    .n_if = 2,
    .p_if = &tisci_if_TIMER8[0],
}

TIMER9_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_225_225

const struct Sciclient_rmIrqIf TIMER9_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_225_225

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 225,
}

tisci_if_TIMER9

const struct Sciclient_rmIrqIf* const tisci_if_TIMER9[]

Initial value:

= {
    &TIMER9_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_225_225,
}

tisci_irq_TIMER9

const struct Sciclient_rmIrqNode tisci_irq_TIMER9

static

Initial value:

= {
    .id = TISCI_DEV_TIMER9,
    .n_if = 1,
    .p_if = &tisci_if_TIMER9[0],
}

TIMER10_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_226_226

const struct Sciclient_rmIrqIf TIMER10_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_226_226

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 226,
}

tisci_if_TIMER10

const struct Sciclient_rmIrqIf* const tisci_if_TIMER10[]

Initial value:

= {
    &TIMER10_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_226_226,
}

tisci_irq_TIMER10

const struct Sciclient_rmIrqNode tisci_irq_TIMER10

static

Initial value:

= {
    .id = TISCI_DEV_TIMER10,
    .n_if = 1,
    .p_if = &tisci_if_TIMER10[0],
}

TIMER11_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_227_227

const struct Sciclient_rmIrqIf TIMER11_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_227_227

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 227,
}

tisci_if_TIMER11

const struct Sciclient_rmIrqIf* const tisci_if_TIMER11[]

Initial value:

= {
    &TIMER11_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_227_227,
}

tisci_irq_TIMER11

const struct Sciclient_rmIrqNode tisci_irq_TIMER11

static

Initial value:

= {
    .id = TISCI_DEV_TIMER11,
    .n_if = 1,
    .p_if = &tisci_if_TIMER11[0],
}

WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_INTROUTER0_in_11_11

const struct Sciclient_rmIrqIf WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_INTROUTER0_in_11_11

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 11,
}

tisci_if_WKUP_GTC0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_GTC0[]

Initial value:

= {
    &WKUP_GTC0_gtc_push_event_0_0_to_TIMESYNC_INTROUTER0_in_11_11,
}

tisci_irq_WKUP_GTC0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_GTC0

static

Initial value:

= {
    .id = TISCI_DEV_WKUP_GTC0,
    .n_if = 1,
    .p_if = &tisci_if_WKUP_GTC0[0],
}

GPIO0_gpio_0_52_to_MAIN_GPIO_INTROUTER0_in_0_52

const struct Sciclient_rmIrqIf GPIO0_gpio_0_52_to_MAIN_GPIO_INTROUTER0_in_0_52

Initial value:

= {
    .lbase = 0,
    .len = 53,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

GPIO0_gpio_55_59_to_MAIN_GPIO_INTROUTER0_in_55_59

const struct Sciclient_rmIrqIf GPIO0_gpio_55_59_to_MAIN_GPIO_INTROUTER0_in_55_59

Initial value:

= {
    .lbase = 55,
    .len = 5,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 55,
}

GPIO0_gpio_62_92_to_MAIN_GPIO_INTROUTER0_in_62_92

const struct Sciclient_rmIrqIf GPIO0_gpio_62_92_to_MAIN_GPIO_INTROUTER0_in_62_92

Initial value:

= {
    .lbase = 62,
    .len = 31,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 62,
}

GPIO0_gpio_bank_93_98_to_MAIN_GPIO_INTROUTER0_in_192_197

const struct Sciclient_rmIrqIf GPIO0_gpio_bank_93_98_to_MAIN_GPIO_INTROUTER0_in_192_197

Initial value:

= {
    .lbase = 93,
    .len = 6,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 192,
}

tisci_if_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[]

Initial value:

= {
    &GPIO0_gpio_0_52_to_MAIN_GPIO_INTROUTER0_in_0_52,
    &GPIO0_gpio_55_59_to_MAIN_GPIO_INTROUTER0_in_55_59,
    &GPIO0_gpio_62_92_to_MAIN_GPIO_INTROUTER0_in_62_92,
    &GPIO0_gpio_bank_93_98_to_MAIN_GPIO_INTROUTER0_in_192_197,
}

tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_GPIO0,
    .n_if = 4,
    .p_if = &tisci_if_GPIO0[0],
}

GPIO1_gpio_0_50_to_MAIN_GPIO_INTROUTER0_in_96_146

const struct Sciclient_rmIrqIf GPIO1_gpio_0_50_to_MAIN_GPIO_INTROUTER0_in_96_146

Initial value:

= {
    .lbase = 0,
    .len = 51,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 96,
}

GPIO1_gpio_72_72_to_MAIN_GPIO_INTROUTER0_in_168_168

const struct Sciclient_rmIrqIf GPIO1_gpio_72_72_to_MAIN_GPIO_INTROUTER0_in_168_168

Initial value:

= {
    .lbase = 72,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 168,
}

GPIO1_gpio_74_85_to_MAIN_GPIO_INTROUTER0_in_170_181

const struct Sciclient_rmIrqIf GPIO1_gpio_74_85_to_MAIN_GPIO_INTROUTER0_in_170_181

Initial value:

= {
    .lbase = 74,
    .len = 12,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 170,
}

GPIO1_gpio_bank_86_91_to_MAIN_GPIO_INTROUTER0_in_200_205

const struct Sciclient_rmIrqIf GPIO1_gpio_bank_86_91_to_MAIN_GPIO_INTROUTER0_in_200_205

Initial value:

= {
    .lbase = 86,
    .len = 6,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 200,
}

tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]

Initial value:

= {
    &GPIO1_gpio_0_50_to_MAIN_GPIO_INTROUTER0_in_96_146,
    &GPIO1_gpio_72_72_to_MAIN_GPIO_INTROUTER0_in_168_168,
    &GPIO1_gpio_74_85_to_MAIN_GPIO_INTROUTER0_in_170_181,
    &GPIO1_gpio_bank_86_91_to_MAIN_GPIO_INTROUTER0_in_200_205,
}

tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1

static

Initial value:

= {
    .id = TISCI_DEV_GPIO1,
    .n_if = 4,
    .p_if = &tisci_if_GPIO1[0],
}

MCU_GPIO0_gpio_0_16_to_MCU_MCU_GPIO_INTROUTER0_in_0_16

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_16_to_MCU_MCU_GPIO_INTROUTER0_in_0_16

Initial value:

= {
    .lbase = 0,
    .len = 17,
    .rid = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .rbase = 0,
}

MCU_GPIO0_gpio_19_25_to_MCU_MCU_GPIO_INTROUTER0_in_19_25

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_19_25_to_MCU_MCU_GPIO_INTROUTER0_in_19_25

Initial value:

= {
    .lbase = 19,
    .len = 7,
    .rid = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .rbase = 19,
}

MCU_GPIO0_gpio_bank_26_27_to_MCU_MCU_GPIO_INTROUTER0_in_30_31

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_26_27_to_MCU_MCU_GPIO_INTROUTER0_in_30_31

Initial value:

= {
    .lbase = 26,
    .len = 2,
    .rid = TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0,
    .rbase = 30,
}

tisci_if_MCU_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[]

Initial value:

= {
    &MCU_GPIO0_gpio_0_16_to_MCU_MCU_GPIO_INTROUTER0_in_0_16,
    &MCU_GPIO0_gpio_19_25_to_MCU_MCU_GPIO_INTROUTER0_in_19_25,
    &MCU_GPIO0_gpio_bank_26_27_to_MCU_MCU_GPIO_INTROUTER0_in_30_31,
}

tisci_irq_MCU_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0

static

Initial value:

= {
    .id = TISCI_DEV_MCU_GPIO0,
    .n_if = 3,
    .p_if = &tisci_if_MCU_GPIO0[0],
}

EPWM0_epwm_synco_o_0_0_to_TIMESYNC_INTROUTER0_in_9_9

const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_INTROUTER0_in_9_9

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_TIMESYNC_EVENT_INTROUTER0,
    .rbase = 9,
}

tisci_if_EPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[]

Initial value:

= {
    &EPWM0_epwm_synco_o_0_0_to_TIMESYNC_INTROUTER0_in_9_9,
}

tisci_irq_EPWM0

const struct Sciclient_rmIrqNode tisci_irq_EPWM0

static

Initial value:

= {
    .id = TISCI_DEV_EPWM0,
    .n_if = 1,
    .p_if = &tisci_if_EPWM0[0],
}

WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_214_214

const struct Sciclient_rmIrqIf WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_214_214

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 214,
}

tisci_if_WKUP_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_TIMER0[]

Initial value:

= {
    &WKUP_TIMER0_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_214_214,
}

tisci_irq_WKUP_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER0

static

Initial value:

= {
    .id = TISCI_DEV_WKUP_TIMER0,
    .n_if = 1,
    .p_if = &tisci_if_WKUP_TIMER0[0],
}

WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_215_215

const struct Sciclient_rmIrqIf WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_215_215

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 215,
}

tisci_if_WKUP_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_WKUP_TIMER1[]

Initial value:

= {
    &WKUP_TIMER1_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_215_215,
}

tisci_irq_WKUP_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_WKUP_TIMER1

static

Initial value:

= {
    .id = TISCI_DEV_WKUP_TIMER1,
    .n_if = 1,
    .p_if = &tisci_if_WKUP_TIMER1[0],
}

MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7

const struct Sciclient_rmIrqIf MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7

Initial value:

= {
    .lbase = 4,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 7,
}

MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31

const struct Sciclient_rmIrqIf MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31

Initial value:

= {
    .lbase = 0,
    .len = 4,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 28,
}

tisci_if_MCRC64_0

const struct Sciclient_rmIrqIf* const tisci_if_MCRC64_0[]

Initial value:

= {
    &MCRC64_0_int_mcrc_4_4_to_DMASS0_INTAGGR_0_intaggr_levi_pend_7_7,
    &MCRC64_0_dma_event_0_3_to_DMASS0_INTAGGR_0_intaggr_levi_pend_28_31,
}

tisci_irq_MCRC64_0

const struct Sciclient_rmIrqNode tisci_irq_MCRC64_0

static

Initial value:

= {
    .id = TISCI_DEV_MCRC64_0,
    .n_if = 2,
    .p_if = &tisci_if_MCRC64_0[0],
}

DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27

const struct Sciclient_rmIrqIf DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 27,
}

tisci_if_DEBUGSS0

const struct Sciclient_rmIrqIf* const tisci_if_DEBUGSS0[]

Initial value:

= {
    &DEBUGSS0_davdma_level_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_27_27,
}

tisci_irq_DEBUGSS0

const struct Sciclient_rmIrqNode tisci_irq_DEBUGSS0

static

Initial value:

= {
    .id = TISCI_DEV_DEBUGSS0,
    .n_if = 1,
    .p_if = &tisci_if_DEBUGSS0[0],
}

MCASP0_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1

const struct Sciclient_rmIrqIf MCASP0_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 1,
}

tisci_if_MCASP0

const struct Sciclient_rmIrqIf* const tisci_if_MCASP0[]

Initial value:

= {
    &MCASP0_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_1_1,
}

tisci_irq_MCASP0

const struct Sciclient_rmIrqNode tisci_irq_MCASP0

static

Initial value:

= {
    .id = TISCI_DEV_MCASP0,
    .n_if = 1,
    .p_if = &tisci_if_MCASP0[0],
}

MCASP1_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2

const struct Sciclient_rmIrqIf MCASP1_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 2,
}

tisci_if_MCASP1

const struct Sciclient_rmIrqIf* const tisci_if_MCASP1[]

Initial value:

= {
    &MCASP1_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_2_2,
}

tisci_irq_MCASP1

const struct Sciclient_rmIrqNode tisci_irq_MCASP1

static

Initial value:

= {
    .id = TISCI_DEV_MCASP1,
    .n_if = 1,
    .p_if = &tisci_if_MCASP1[0],
}

MCASP2_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3

const struct Sciclient_rmIrqIf MCASP2_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 3,
}

tisci_if_MCASP2

const struct Sciclient_rmIrqIf* const tisci_if_MCASP2[]

Initial value:

= {
    &MCASP2_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_3_3,
}

tisci_irq_MCASP2

const struct Sciclient_rmIrqNode tisci_irq_MCASP2

static

Initial value:

= {
    .id = TISCI_DEV_MCASP2,
    .n_if = 1,
    .p_if = &tisci_if_MCASP2[0],
}

MCASP3_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4

const struct Sciclient_rmIrqIf MCASP3_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 4,
}

tisci_if_MCASP3

const struct Sciclient_rmIrqIf* const tisci_if_MCASP3[]

Initial value:

= {
    &MCASP3_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_4_4,
}

tisci_irq_MCASP3

const struct Sciclient_rmIrqNode tisci_irq_MCASP3

static

Initial value:

= {
    .id = TISCI_DEV_MCASP3,
    .n_if = 1,
    .p_if = &tisci_if_MCASP3[0],
}

MCASP4_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5

const struct Sciclient_rmIrqIf MCASP4_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_DMASS0_INTAGGR_0,
    .rbase = 5,
}

tisci_if_MCASP4

const struct Sciclient_rmIrqIf* const tisci_if_MCASP4[]

Initial value:

= {
    &MCASP4_xmit_dma_event_req_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_5_5,
}

tisci_irq_MCASP4

const struct Sciclient_rmIrqNode tisci_irq_MCASP4

static

Initial value:

= {
    .id = TISCI_DEV_MCASP4,
    .n_if = 1,
    .p_if = &tisci_if_MCASP4[0],
}

TIMER12_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_228_228

const struct Sciclient_rmIrqIf TIMER12_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_228_228

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 228,
}

tisci_if_TIMER12

const struct Sciclient_rmIrqIf* const tisci_if_TIMER12[]

Initial value:

= {
    &TIMER12_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_228_228,
}

tisci_irq_TIMER12

const struct Sciclient_rmIrqNode tisci_irq_TIMER12

static

Initial value:

= {
    .id = TISCI_DEV_TIMER12,
    .n_if = 1,
    .p_if = &tisci_if_TIMER12[0],
}

TIMER13_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_229_229

const struct Sciclient_rmIrqIf TIMER13_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_229_229

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 229,
}

tisci_if_TIMER13

const struct Sciclient_rmIrqIf* const tisci_if_TIMER13[]

Initial value:

= {
    &TIMER13_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_229_229,
}

tisci_irq_TIMER13

const struct Sciclient_rmIrqNode tisci_irq_TIMER13

static

Initial value:

= {
    .id = TISCI_DEV_TIMER13,
    .n_if = 1,
    .p_if = &tisci_if_TIMER13[0],
}

TIMER14_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_230_230

const struct Sciclient_rmIrqIf TIMER14_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_230_230

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 230,
}

tisci_if_TIMER14

const struct Sciclient_rmIrqIf* const tisci_if_TIMER14[]

Initial value:

= {
    &TIMER14_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_230_230,
}

tisci_irq_TIMER14

const struct Sciclient_rmIrqNode tisci_irq_TIMER14

static

Initial value:

= {
    .id = TISCI_DEV_TIMER14,
    .n_if = 1,
    .p_if = &tisci_if_TIMER14[0],
}

TIMER15_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_231_231

const struct Sciclient_rmIrqIf TIMER15_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_231_231

Initial value:

= {
    .lbase = 0,
    .len = 1,
    .rid = TISCI_DEV_MAIN_GPIOMUX_INTROUTER0,
    .rbase = 231,
}

tisci_if_TIMER15

const struct Sciclient_rmIrqIf* const tisci_if_TIMER15[]

Initial value:

= {
    &TIMER15_timer_pwm_0_0_to_MAIN_GPIO_INTROUTER0_in_231_231,
}

tisci_irq_TIMER15

const struct Sciclient_rmIrqNode tisci_irq_TIMER15

static

Initial value:

= {
    .id = TISCI_DEV_TIMER15,
    .n_if = 1,
    .p_if = &tisci_if_TIMER15[0],
}

gRmIrqTree

const struct Sciclient_rmIrqNode* const gRmIrqTree[RM_IRQ_TREE_MAX]

gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])