Introduction

DMSC controls the power management, security and resource management of the device.

Macros
#define	TISCI_HOST_ID_TIFS (0U)
	This file contains: More...

#define	TISCI_HOST_ID_DM (254U)

#define	TISCI_HOST_ID_WKUP_0_R5_0 (35U)

#define	TISCI_HOST_ID_WKUP_0_R5_1 (36U)

#define	TISCI_HOST_ID_MAIN_0_R5_0 (40U)

#define	TISCI_HOST_ID_MAIN_0_R5_1 (41U)

#define	TISCI_HOST_ID_MAIN_0_R5_2 (42U)

#define	TISCI_HOST_ID_MAIN_0_R5_3 (43U)

#define	TISCI_HOST_ID_MAIN_1_R5_0 (45U)

#define	TISCI_HOST_ID_MAIN_1_R5_1 (46U)

#define	TISCI_HOST_ID_MAIN_1_R5_2 (47U)

#define	TISCI_HOST_ID_MAIN_1_R5_3 (48U)

#define	TISCI_HOST_ID_C7X_0_0 (20U)

#define	TISCI_HOST_ID_C7X_1_0 (22U)

#define	TISCI_HOST_ID_DM2TIFS (250U)

#define	TISCI_HOST_ID_TIFS2DM (251U)

#define	TISCI_HOST_ID_HSM (253U)

#define	TISCI_HOST_ID_ALL (128U)

#define	TISCI_HOST_ID_CNT (17U)

Macro Definition Documentation

◆ TISCI_HOST_ID_TIFS

#define TISCI_HOST_ID_TIFS (0U)

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

System Firmware Source File

Host IDs for AM275X device

Data version: 241217_073541 TIFS(Secure): TI Foundational Security

◆ TISCI_HOST_ID_DM

#define TISCI_HOST_ID_DM (254U)

DM(Non Secure): Device Management

◆ TISCI_HOST_ID_WKUP_0_R5_0

#define TISCI_HOST_ID_WKUP_0_R5_0 (35U)

WKUP_0_R5_0(Secure): Cortex R5_0 context 0 on WKUP domain (BOOT)

◆ TISCI_HOST_ID_WKUP_0_R5_1

#define TISCI_HOST_ID_WKUP_0_R5_1 (36U)

WKUP_0_R5_1(Non Secure): Cortex R5_0 context 1 on WKUP domain

◆ TISCI_HOST_ID_MAIN_0_R5_0

#define TISCI_HOST_ID_MAIN_0_R5_0 (40U)

MAIN_0_R5_0(Secure): Cortex R5_0 context 0 on MAIN domain

◆ TISCI_HOST_ID_MAIN_0_R5_1

#define TISCI_HOST_ID_MAIN_0_R5_1 (41U)

MAIN_0_R5_1(Non Secure): Cortex R5_0 context 1 on MAIN domain

◆ TISCI_HOST_ID_MAIN_0_R5_2

#define TISCI_HOST_ID_MAIN_0_R5_2 (42U)

MAIN_0_R5_2(Secure): Cortex R5_0 context 2 on MAIN domain

◆ TISCI_HOST_ID_MAIN_0_R5_3

#define TISCI_HOST_ID_MAIN_0_R5_3 (43U)

MAIN_0_R5_3(Non Secure): Cortex R5_0 context 3 on MAIN domain

◆ TISCI_HOST_ID_MAIN_1_R5_0

#define TISCI_HOST_ID_MAIN_1_R5_0 (45U)

MAIN_1_R5_0(Secure): Cortex R5_1 context 0 on MAIN domain

◆ TISCI_HOST_ID_MAIN_1_R5_1

#define TISCI_HOST_ID_MAIN_1_R5_1 (46U)

MAIN_1_R5_1(Non Secure): Cortex R5_1 context 1 on MAIN domain

◆ TISCI_HOST_ID_MAIN_1_R5_2

#define TISCI_HOST_ID_MAIN_1_R5_2 (47U)

MAIN_1_R5_2(Secure): Cortex R5_1 context 2 on MAIN domain

◆ TISCI_HOST_ID_MAIN_1_R5_3

#define TISCI_HOST_ID_MAIN_1_R5_3 (48U)

MAIN_1_R5_3(Non Secure): Cortex R5_1 context 3 on MAIN domain

◆ TISCI_HOST_ID_C7X_0_0

#define TISCI_HOST_ID_C7X_0_0 (20U)

C7X_0_0(Non Secure): C7x_0 context 0 on MAIN domain

◆ TISCI_HOST_ID_C7X_1_0

#define TISCI_HOST_ID_C7X_1_0 (22U)

C7X_1_0(Non Secure): C7x_1 context 0 on MAIN domain

◆ TISCI_HOST_ID_DM2TIFS

#define TISCI_HOST_ID_DM2TIFS (250U)

DM2TIFS(Secure): DM to TIFS communication

◆ TISCI_HOST_ID_TIFS2DM

#define TISCI_HOST_ID_TIFS2DM (251U)

TIFS2DM(Non Secure): TIFS to DM communication

◆ TISCI_HOST_ID_HSM

#define TISCI_HOST_ID_HSM (253U)

HSM(Secure): HSM Controller

◆ TISCI_HOST_ID_ALL

#define TISCI_HOST_ID_ALL (128U)

Host catch all. Used in board configuration resource assignments to define resource ranges useable by all hosts. Cannot be used

◆ TISCI_HOST_ID_CNT

#define TISCI_HOST_ID_CNT (17U)

Number of unique hosts on the SoC