SDL_stcRegs Struct Reference

Data Fields
volatile uint32_t	STCGCR0
volatile uint32_t	STCGCR1
volatile uint32_t	STCTPR
volatile uint32_t	STC_CADDR
volatile uint32_t	STCCICR
volatile uint32_t	STCGSTAT
volatile uint32_t	STCFSTAT
volatile uint32_t	STCSCSCR
volatile uint32_t	STC_CADDR2
volatile uint32_t	STC_CLKDIV
volatile uint32_t	STC_SEGPLR
volatile uint32_t	SEG0_START_ADDR
volatile uint32_t	SEG1_START_ADDR
volatile uint32_t	SEG2_START_ADDR
volatile uint32_t	SEG3_START_ADDR
volatile uint32_t	CORE1_CURMISR_0
volatile uint32_t	CORE1_CURMISR_1
volatile uint32_t	CORE1_CURMISR_2
volatile uint32_t	CORE1_CURMISR_3
volatile uint32_t	CORE1_CURMISR_4
volatile uint32_t	CORE1_CURMISR_5
volatile uint32_t	CORE1_CURMISR_6
volatile uint32_t	CORE1_CURMISR_7
volatile uint32_t	CORE1_CURMISR_8
volatile uint32_t	CORE1_CURMISR_9
volatile uint32_t	CORE1_CURMISR_10
volatile uint32_t	CORE1_CURMISR_11
volatile uint32_t	CORE1_CURMISR_12
volatile uint32_t	CORE1_CURMISR_13
volatile uint32_t	CORE1_CURMISR_14
volatile uint32_t	CORE1_CURMISR_15
volatile uint32_t	CORE1_CURMISR_16
volatile uint32_t	CORE1_CURMISR_17
volatile uint32_t	CORE1_CURMISR_18
volatile uint32_t	CORE1_CURMISR_19
volatile uint32_t	CORE1_CURMISR_20
volatile uint32_t	CORE1_CURMISR_21
volatile uint32_t	CORE1_CURMISR_22
volatile uint32_t	CORE1_CURMISR_23
volatile uint32_t	CORE1_CURMISR_24
volatile uint32_t	CORE1_CURMISR_25
volatile uint32_t	CORE1_CURMISR_26
volatile uint32_t	CORE1_CURMISR_27

Field Documentation

STCGCR0

volatile uint32_t SDL_stcRegs::STCGCR0

STC Self test Global control register0

STCGCR1

volatile uint32_t SDL_stcRegs::STCGCR1

STC Self test Global control register1

STCTPR

volatile uint32_t SDL_stcRegs::STCTPR

STC Time out counter preload register

STC_CADDR

volatile uint32_t SDL_stcRegs::STC_CADDR

STC Current Address register for CORE1

STCCICR

volatile uint32_t SDL_stcRegs::STCCICR

STC Current Interval count register

STCGSTAT

volatile uint32_t SDL_stcRegs::STCGSTAT

STC Global Status Register

STCFSTAT

volatile uint32_t SDL_stcRegs::STCFSTAT

STC Fail Status Register

STCSCSCR

volatile uint32_t SDL_stcRegs::STCSCSCR

STC Signature compare Self Check Register

STC_CADDR2

volatile uint32_t SDL_stcRegs::STC_CADDR2

STC Current Address register for CORE2

STC_CLKDIV

volatile uint32_t SDL_stcRegs::STC_CLKDIV

STC Clock Divider Register

STC_SEGPLR

volatile uint32_t SDL_stcRegs::STC_SEGPLR

STC Segment 1st interval Preload Register

SEG0_START_ADDR

volatile uint32_t SDL_stcRegs::SEG0_START_ADDR

STC ROM Start address for Segment0

SEG1_START_ADDR

volatile uint32_t SDL_stcRegs::SEG1_START_ADDR

STC ROM Start address for Segment1

SEG2_START_ADDR

volatile uint32_t SDL_stcRegs::SEG2_START_ADDR

STC ROM Start address for Segment2

SEG3_START_ADDR

volatile uint32_t SDL_stcRegs::SEG3_START_ADDR

STC ROM Start address for Segment3

CORE1_CURMISR_0

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_0

STC Holds the MISR signature for CORE1

CORE1_CURMISR_1

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_1

STC Holds the MISR signature for CORE1

CORE1_CURMISR_2

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_2

STC Holds the MISR signature for CORE1

CORE1_CURMISR_3

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_3

STC Holds the MISR signature for CORE1

CORE1_CURMISR_4

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_4

STC Holds the MISR signature for CORE1

CORE1_CURMISR_5

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_5

STC Holds the MISR signature for CORE1

CORE1_CURMISR_6

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_6

STC Holds the MISR signature for CORE1

CORE1_CURMISR_7

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_7

STC Holds the MISR signature for CORE1

CORE1_CURMISR_8

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_8

STC Holds the MISR signature for CORE1

CORE1_CURMISR_9

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_9

STC Holds the MISR signature for CORE1

CORE1_CURMISR_10

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_10

STC Holds the MISR signature for CORE1

CORE1_CURMISR_11

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_11

STC Holds the MISR signature for CORE1

CORE1_CURMISR_12

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_12

STC Holds the MISR signature for CORE1

CORE1_CURMISR_13

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_13

STC Holds the MISR signature for CORE1

CORE1_CURMISR_14

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_14

STC Holds the MISR signature for CORE1

CORE1_CURMISR_15

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_15

STC Holds the MISR signature for CORE1

CORE1_CURMISR_16

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_16

STC Holds the MISR signature for CORE1

CORE1_CURMISR_17

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_17

STC Holds the MISR signature for CORE1

CORE1_CURMISR_18

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_18

STC Holds the MISR signature for CORE1

CORE1_CURMISR_19

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_19

STC Holds the MISR signature for CORE1

CORE1_CURMISR_20

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_20

STC Holds the MISR signature for CORE1

CORE1_CURMISR_21

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_21

STC Holds the MISR signature for CORE1

CORE1_CURMISR_22

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_22

STC Holds the MISR signature for CORE1

CORE1_CURMISR_23

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_23

STC Holds the MISR signature for CORE1

CORE1_CURMISR_24

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_24

STC Holds the MISR signature for CORE1

CORE1_CURMISR_25

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_25

STC Holds the MISR signature for CORE1

CORE1_CURMISR_26

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_26

STC Holds the MISR signature for CORE1

CORE1_CURMISR_27

volatile uint32_t SDL_stcRegs::CORE1_CURMISR_27

STC Holds the MISR signature for CORE1