Detailed Description

Structure containing R5F CPU Static Registers.

Design: PROC_SDL-6331

Data Fields
uint32_t	MIDR

uint32_t	CTR

uint32_t	TCMTR

uint32_t	MPUIR

uint32_t	MPIDR

uint32_t	PFR0

uint32_t	PFR1

uint32_t	ID_DFR0

uint32_t	ID_AFR0

uint32_t	ID_MMFR0

uint32_t	ID_MMFR1

uint32_t	ID_MMFR2

uint32_t	ID_MMFR3

uint32_t	ID_ISAR0

uint32_t	ID_ISAR1

uint32_t	ID_ISAR2

uint32_t	ID_ISAR3

uint32_t	ID_ISAR4

uint32_t	ID_ISAR5

uint32_t	CCSIDR

uint32_t	CLIDR

uint32_t	AIDR

uint32_t	CSSELR

uint32_t	SCTLR

uint32_t	ACTLR

uint32_t	SecondaryACTLR

uint32_t	CPACR

uint32_t	MPURegionBaseADDR

uint32_t	MPURegionEnableR

uint32_t	MPURegionAccessControlR

uint32_t	RGNR

uint32_t	BTCMRegionR

uint32_t	ATCMRegionR

uint32_t	SlavePortControlR

uint32_t	CONTEXTIDR

uint32_t	ThreadProcessIDR1

uint32_t	ThreadProcessIDR2

uint32_t	ThreadProcessIDR3

uint32_t	nVALIRQSET

uint32_t	nVALFIQSET

uint32_t	nVALRESETSET

uint32_t	nVALDEBUGSET

uint32_t	nVALIRQCLEAR

uint32_t	nVALFIQCLEAR

uint32_t	nVALRESETCLEAR

uint32_t	nVALDEBUGCLEAR

uint32_t	BuildOption1R

uint32_t	BuildOption2R

uint32_t	PinOptionR

uint32_t	LLPPnormalAXIRR

uint32_t	LLPPvirtualAXIRR

uint32_t	AHBRR

uint32_t	CFLR

uint32_t	PMOVSR

uint32_t	DFSR

uint32_t	ADFSR

uint32_t	DFAR

uint32_t	IFSR

uint32_t	IFAR

uint32_t	AIFSR

Field Documentation

◆ MIDR

uint32_t SDL_R5FCPU_StaticRegs::MIDR

◆ CTR

uint32_t SDL_R5FCPU_StaticRegs::CTR

◆ TCMTR

uint32_t SDL_R5FCPU_StaticRegs::TCMTR

◆ MPUIR

uint32_t SDL_R5FCPU_StaticRegs::MPUIR

◆ MPIDR

uint32_t SDL_R5FCPU_StaticRegs::MPIDR

◆ PFR0

uint32_t SDL_R5FCPU_StaticRegs::PFR0

◆ PFR1

uint32_t SDL_R5FCPU_StaticRegs::PFR1

◆ ID_DFR0

uint32_t SDL_R5FCPU_StaticRegs::ID_DFR0

◆ ID_AFR0

uint32_t SDL_R5FCPU_StaticRegs::ID_AFR0

◆ ID_MMFR0

uint32_t SDL_R5FCPU_StaticRegs::ID_MMFR0

◆ ID_MMFR1

uint32_t SDL_R5FCPU_StaticRegs::ID_MMFR1

◆ ID_MMFR2

uint32_t SDL_R5FCPU_StaticRegs::ID_MMFR2

◆ ID_MMFR3

uint32_t SDL_R5FCPU_StaticRegs::ID_MMFR3

◆ ID_ISAR0

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR0

◆ ID_ISAR1

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR1

◆ ID_ISAR2

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR2

◆ ID_ISAR3

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR3

◆ ID_ISAR4

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR4

◆ ID_ISAR5

uint32_t SDL_R5FCPU_StaticRegs::ID_ISAR5

◆ CCSIDR

uint32_t SDL_R5FCPU_StaticRegs::CCSIDR

◆ CLIDR

uint32_t SDL_R5FCPU_StaticRegs::CLIDR

◆ AIDR

uint32_t SDL_R5FCPU_StaticRegs::AIDR

◆ CSSELR

uint32_t SDL_R5FCPU_StaticRegs::CSSELR

◆ SCTLR

uint32_t SDL_R5FCPU_StaticRegs::SCTLR

◆ ACTLR

uint32_t SDL_R5FCPU_StaticRegs::ACTLR

◆ SecondaryACTLR

uint32_t SDL_R5FCPU_StaticRegs::SecondaryACTLR

◆ CPACR

uint32_t SDL_R5FCPU_StaticRegs::CPACR

◆ MPURegionBaseADDR

uint32_t SDL_R5FCPU_StaticRegs::MPURegionBaseADDR

◆ MPURegionEnableR

uint32_t SDL_R5FCPU_StaticRegs::MPURegionEnableR

◆ MPURegionAccessControlR

uint32_t SDL_R5FCPU_StaticRegs::MPURegionAccessControlR

◆ RGNR

uint32_t SDL_R5FCPU_StaticRegs::RGNR

◆ BTCMRegionR

uint32_t SDL_R5FCPU_StaticRegs::BTCMRegionR

◆ ATCMRegionR

uint32_t SDL_R5FCPU_StaticRegs::ATCMRegionR

◆ SlavePortControlR

uint32_t SDL_R5FCPU_StaticRegs::SlavePortControlR

◆ CONTEXTIDR

uint32_t SDL_R5FCPU_StaticRegs::CONTEXTIDR

◆ ThreadProcessIDR1

uint32_t SDL_R5FCPU_StaticRegs::ThreadProcessIDR1

◆ ThreadProcessIDR2

uint32_t SDL_R5FCPU_StaticRegs::ThreadProcessIDR2

◆ ThreadProcessIDR3

uint32_t SDL_R5FCPU_StaticRegs::ThreadProcessIDR3

◆ nVALIRQSET

uint32_t SDL_R5FCPU_StaticRegs::nVALIRQSET

◆ nVALFIQSET

uint32_t SDL_R5FCPU_StaticRegs::nVALFIQSET

◆ nVALRESETSET

uint32_t SDL_R5FCPU_StaticRegs::nVALRESETSET

◆ nVALDEBUGSET

uint32_t SDL_R5FCPU_StaticRegs::nVALDEBUGSET

◆ nVALIRQCLEAR

uint32_t SDL_R5FCPU_StaticRegs::nVALIRQCLEAR

◆ nVALFIQCLEAR

uint32_t SDL_R5FCPU_StaticRegs::nVALFIQCLEAR

◆ nVALRESETCLEAR

uint32_t SDL_R5FCPU_StaticRegs::nVALRESETCLEAR

◆ nVALDEBUGCLEAR

uint32_t SDL_R5FCPU_StaticRegs::nVALDEBUGCLEAR

◆ BuildOption1R

uint32_t SDL_R5FCPU_StaticRegs::BuildOption1R

◆ BuildOption2R

uint32_t SDL_R5FCPU_StaticRegs::BuildOption2R

◆ PinOptionR

uint32_t SDL_R5FCPU_StaticRegs::PinOptionR

◆ LLPPnormalAXIRR

uint32_t SDL_R5FCPU_StaticRegs::LLPPnormalAXIRR

◆ LLPPvirtualAXIRR

uint32_t SDL_R5FCPU_StaticRegs::LLPPvirtualAXIRR

◆ AHBRR

uint32_t SDL_R5FCPU_StaticRegs::AHBRR

◆ CFLR

uint32_t SDL_R5FCPU_StaticRegs::CFLR

◆ PMOVSR

uint32_t SDL_R5FCPU_StaticRegs::PMOVSR

◆ DFSR

uint32_t SDL_R5FCPU_StaticRegs::DFSR

◆ ADFSR

uint32_t SDL_R5FCPU_StaticRegs::ADFSR

◆ DFAR

uint32_t SDL_R5FCPU_StaticRegs::DFAR

◆ IFSR

uint32_t SDL_R5FCPU_StaticRegs::IFSR

◆ IFAR

uint32_t SDL_R5FCPU_StaticRegs::IFAR

◆ AIFSR

uint32_t SDL_R5FCPU_StaticRegs::AIFSR