AM273x MCU+ SDK  09.02.00
sdl_ecc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022-2024
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
47 #ifndef INCLUDE_SDL_ECC_H_
48 #define INCLUDE_SDL_ECC_H_
49 
50 #include <stdint.h>
51 #include <stdbool.h>
52 
53 #include "sdl_common.h"
54 #include <sdl/ecc/sdl_ip_ecc.h>
55 #if defined(SOC_AM263X)
56 #include <sdl/esm/v0/sdl_esm.h>
57 #endif
58 #if defined(SOC_AM263PX)
59 #include <sdl/esm/v2/sdl_esm.h>
60 #endif
61 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
62 #include <sdl/esm/v1/sdl_esm.h>
63 #endif
64 #if defined(SOC_AM64X) || defined(SOC_AM243X)
65 #include <sdl/esm/v0/sdl_esm.h>
66 #endif
67 
68 #ifdef __cplusplus
69 extern "C" {
70 #endif
71 
77 #if defined(SOC_AM263X) || defined(SOC_AM263PX)
78 
79 #define SDL_SOC_ECC_AGGR (0U)
80 #define SDL_R5FSS0_CORE0_ECC_AGGR (1U)
81 #define SDL_R5FSS0_CORE1_ECC_AGGR (2U)
82 #define SDL_R5FSS1_CORE0_ECC_AGGR (3U)
83 #define SDL_R5FSS1_CORE1_ECC_AGGR (4U)
84 #define SDL_HSM_ECC_AGGR (5U)
85 #define SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6U)
86 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7U)
87 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8U)
88 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9U)
89 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10U)
90 #if defined(SOC_AM263PX)
91 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (11U)
92 #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (12U)
93 #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (13U)
94 #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (14U)
95 #define SDL_FSS_OSPI_RAM_ECC_AGGR (15U)
96 #define SDL_FSS_FOTA_8051_RAM_ECC_AGGR (16U)
97 #define SDL_CPSW3GCSS_ECC_AGGR (17U)
98 #else
99 #define SDL_CPSW3GCSS_ECC_AGGR (11U)
100 #endif
101 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
102 
103 /* Parity */
104 #define SDL_R5SS0_CPU0_TCM (0U)
105 #define SDL_R5SS1_CPU0_TCM (1U)
106 /* SDL_R5SS0_CPU0_TCM */
107 #define SDL_R5FSS0_CORE0_ATCM0 (1U)
108 #define SDL_R5FSS0_CORE0_B0TCM0 (3U)
109 #define SDL_R5FSS0_CORE0_B1TCM0 (5U)
110 /* SDL_R5SS0_CPU10_TCM */
111 #define SDL_R5FSS0_CORE1_ATCM1 (2U)
112 #define SDL_R5FSS0_CORE1_B0TCM1 (4U)
113 #define SDL_R5FSS0_CORE1_B1TCM1 (6U)
114 /* SDL_R5SS1_CPU0_TCM */
115 #define SDL_R5FSS1_CORE0_ATCM0 (7U)
116 #define SDL_R5FSS1_CORE0_B0TCM0 (9U)
117 #define SDL_R5FSS1_CORE0_B1TCM0 (11U)
118 /* SDL_R5SS1_CPU1_TCM */
119 #define SDL_R5FSS1_CORE1_ATCM1 (8U)
120 #define SDL_R5FSS1_CORE1_B0TCM1 (10U)
121 #define SDL_R5FSS1_CORE1_B1TCM1 (12U)
122 /* TPCC */
123 #define SDL_TPCC0 (2)
124 #endif
125 
126 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
127 #define SDL_R5FSS0_CORE0_ECC_AGGR (0U)
128 #define SDL_R5FSS0_CORE1_ECC_AGGR (1U)
129 #define SDL_MSS_ECC_AGG_MSS (2U)
130 #define SDL_DSS_ECC_AGG (3U)
131 #define SDL_MSS_MCANA_ECC (4U)
132 #define SDL_MSS_MCANB_ECC (5U)
133 #define SDL_CPSW3GCSS_ECC_AGGR (6U)
134 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
135 /* TCM PARITY */
136 #define SDL_TCM_PARITY_ATCM0 (1U)
137 #define SDL_TCM_PARITY_ATCM1 (2U)
138 #define SDL_TCM_PARITY_B0TCM0 (3U)
139 #define SDL_TCM_PARITY_B0TCM1 (4U)
140 #define SDL_TCM_PARITY_B1TCM0 (5U)
141 #define SDL_TCM_PARITY_B1TCM1 (6U)
142 
143 /* TPCC */
144 #define SDL_TPCC0A (2U)
145 #define SDL_TPCC0B (3U)
146 #define SDL_DSS_TPCCA (4U)
147 #define SDL_DSS_TPCCB (5U)
148 #define SDL_DSS_TPCCC (6U)
149 #endif
150 
151 #if defined(SOC_AM64X) || defined(SOC_AM243X)
152 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (0u)
153 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (1u)
154 #define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR (2u)
155 #define SDL_ECC_AGGR1 (3u)
156 #define SDL_ECC_AGGR0 (4u)
157 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (5u)
158 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (6u)
159 #define SDL_DMASS0_DMSS_AM64_ECCAGGR (7u)
160 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (8u)
161 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (9u)
162 #define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR (10u)
163 #define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR (11u)
164 #define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR (12u)
165 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (13u)
166 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (14u)
167 #define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR (15u)
168 #define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR (16u)
169 #define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR (17u)
170 #define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR (18u)
171 #define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR (19u)
172 #define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM (20u)
173 #define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM (21u)
174 #define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (22u)
175 #define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR (23u)
176 #define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR (24u)
177 #define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR (25u)
178 #define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR (26u)
179 #define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR (27u)
180 #define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR (28u)
181 #define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR (29u)
182 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM (30u)
183 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM (31u)
184 #define SDL_VTM0_K3VTM_N16FFC_ECCAGGR (32u)
185 #define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR (33u)
186 #define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR (34u)
187 #define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR (35u)
188 #define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR (36u)
189 #if defined(SOC_AM64X)
190 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (37u)
191 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (38u)
192 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (39u)
193 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
194 #endif
195 #if defined(SOC_AM243X)
196 #define SDL_ECC_MEMTYPE_MAX (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
197 #endif
198 #endif
199 
200 /* The following are the memory sub type for Memory type
201  SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
202 /* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
203 #if defined(SOC_AM273X) || defined(SOC_AWR294X) || defined(SOC_AM263X) || defined(SOC_AM263PX)
204 
205 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
206 
207 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
208 
209 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
210 
211 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
212 
213 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
214 
215 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
216 
217 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
218 #endif
219 
220 #if defined(SOC_AM64X) || defined(SOC_AM243X)
221 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID)
222 
223 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID)
224 
225 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID)
226 
227 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID)
228 
229 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID)
230 
231 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID)
232 
233 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
234 #endif
235 
247 typedef enum {
248  SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
250  SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
252 } SDL_ECC_AggregatorType;
253 
254 
260 typedef enum {
262  SDL_INJECT_ECC_NO_ERROR = 0,
264  SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
266  SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
268  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
270  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
272  SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
274  SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
276  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
278  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
279 } SDL_ECC_InjectErrorType;
280 
281 
286 typedef enum {
287  SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
289  SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
291 } SDL_ECC_RamIdType;
292 
298 typedef uint32_t SDL_ECC_MemSubType;
299 
305 typedef uint32_t SDL_ECC_MemType;
306 
310 typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
311 
313 typedef void (*SDL_ECC_VIMDEDVector_t) (void);
314 
324 typedef struct SDL_ECC_InitConfig_s
325 {
326  uint32_t numRams;
329  SDL_ECC_MemSubType *pMemSubTypeList;
331 } SDL_ECC_InitConfig_t;
332 
337 typedef struct SDL_ECC_InjectErrorConfig_s
338 {
339  uint32_t *pErrMem;
341  uint32_t flipBitMask;
343  uint32_t chkGrp;
345 } SDL_ECC_InjectErrorConfig_t;
346 
351 typedef struct SDL_ECC_ErrorInfo_s
352 {
353  SDL_ECC_MemType eccMemType;
355  SDL_ECC_MemSubType memSubType;
357  SDL_Ecc_AggrIntrSrc intrSrc;
359  uint32_t bitErrCnt;
361  uint32_t injectBitErrCnt;
363  uint32_t bitErrorGroup;
365  uint64_t bitErrorOffset;
367 } SDL_ECC_ErrorInfo_t;
368 
384 int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);
385 
395 int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
396  const SDL_ECC_InitConfig_t *pECCInitConfig);
397 
408 int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
409  SDL_ECC_MemSubType memSubType);
410 
424 int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
425  SDL_ECC_MemSubType memSubType,
426  SDL_ECC_InjectErrorType errorType,
427  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
428  uint32_t selfTestTimeOut);
429 
442 int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
443  SDL_ECC_MemSubType memSubType,
444  SDL_ECC_InjectErrorType errorType,
445  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);
446 
456 int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
457  SDL_ECC_staticRegs *pStaticRegs);
458 
470 int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
471  SDL_Ecc_AggrIntrSrc intrSrc,
472  SDL_ECC_ErrorInfo_t *pErrorInfo);
473 
483 int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
484  SDL_Ecc_AggrIntrSrc intrSrc);
485 
499 int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
500  SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);
501 
515 int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
516  SDL_Ecc_AggrIntrSrc intrSrc,
517  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);
518 
535 void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
536  uint32_t errorSrc,
537  uint32_t address,
538  uint32_t ramId,
539  uint64_t bitErrorOffset,
540  uint32_t bitErrorGroup);
541 #if defined(SOC_AM263X) || defined(SOC_AM263PX)
542 
552 int32_t SDL_ECC_tcmParity(SDL_ECC_MemType eccMemType,
553  SDL_ECC_MemSubType memSubType,
554  uint32_t bitValue);
562 int32_t SDL_cleartcmStatusRegs(uint32_t clearVal);
563 #endif
564 #if defined(SOC_AM273X)|| defined(SOC_AWR294X)
565 
574 int32_t SDL_ECC_tcmParity(SDL_ECC_MemSubType memSubType,
575  uint32_t bitValue);
576 
577 /***********************************************************************
578  *
579  * \brief DSS L2 parity init
580  *
581  * \param1 void
582  * @return void
583  **********************************************************************/
584 void SDL_ECC_dss_l2_parity_init(void);
585 
586 /***********************************************************************
587  *
588  * \brief DSS L2 parity error inject
589  *
590  * \param1 injectError : single bit inject for parity error
591  * \param2 injectErrAdd: Inject memory address
592  * \param3 value : Initial value before injecting
593  * @return void
594  **********************************************************************/
595 void SDL_ECC_dss_l2_parity_errorInject(uint32_t injectError, uint32_t injectErrAdd, uint32_t value);
596 
597 /***********************************************************************
598  *
599  * \brief The single-bit error correction and double-bit error
600  * detection errors from the memories of L1 and L2 using EDC
601  * Mask and FLG registers
602  *
603  * \param1 exception_mask_flag : Register value used to enable
604  * propagation of particular exceptions
605  * @return void
606  **********************************************************************/
607 void SDL_ECC_DSP_Aggregated_EDC_Errors(uint32_t exception_mask_flag);
608 
609 /***********************************************************************
610  *
611  * \brief EDC Command Enable for L1P memory
612  *
613  * \param1 void
614  * @return SDL_PASS or SDL_EFAIL
615  **********************************************************************/
616 int32_t SDL_ECC_dss_l1p_edc_CMD_EN(void);
617 
618 /***********************************************************************
619  *
620  * \brief EDC Command Suspend for L1P memory
621  *
622  * \param1 void
623  * @return SDL_PASS or SDL_EFAIL
624  **********************************************************************/
625 int32_t SDL_ECC_dss_l1p_CMD_SUSP(void);
626 
627 /***********************************************************************
628  *
629  * \brief EDC Command Enable for L2 memory
630  *
631  * \param1 void
632  * @return SDL_PASS or SDL_EFAIL
633  **********************************************************************/
634 int32_t SDL_ECC_dss_l2_edc_CMD_EN(void);
635 
636 /***********************************************************************
637  *
638  * \brief EDC Command Suspend for L2 memory
639  *
640  * \param1 void
641  * @return SDL_PASS or SDL_EFAIL
642  **********************************************************************/
643 int32_t SDL_ECC_dss_l2_CMD_SUSP(void);
644 
645 /***********************************************************************
646  *
647  * \brief IDMA 1 Transfer function
648  *
649  * \param1 srcAddr : Source address of the IDMA 1 transfer
650  * \param2 destAddr: Destination address of the IDMA 1 transfer
651  *
652  * @return void
653  **********************************************************************/
654 void SDL_ECC_IDMA1_transfer(uint32_t srcAddr, uint32_t destAddr);
655 
656 #endif
657 
658 
669 int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType,
670  uint32_t bitValue,
671  uint32_t paramregvalue,
672  uint32_t regval);
673 
674 #if defined(SOC_AM263PX)
675 
680 void SDL_ECC_enableTMUROMParity(void);
681 
688 void SDL_ECC_enableTMUROMParityForceError(void);
689 
696 void SDL_ECC_disableTMUROMParity(void);
697 
704 void SDL_ECC_disableTMUROMParityErrorForce(void);
705 
712 void SDL_ECC_clearTMUROMParityError(void);
713 
714 #endif
715 
718 #ifdef __cplusplus
719 }
720 #endif /* extern "C" */
721 
722 #endif
SDL_ECC_ErrorCallback_t
void(* SDL_ECC_ErrorCallback_t)(uint32_t errorSrc, uint32_t address)
Definition: sdl_ecc.h:310
SDL_ECC_InitConfig_t
Definition: sdl_ecc.h:325
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_ErrorInfo_t::memSubType
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:355
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:326
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:266
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
SDL_ECC_ackIntr
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
SDL_ECC_InjectErrorConfig_t::chkGrp
uint32_t chkGrp
Definition: sdl_ecc.h:343
sdl_esm.h
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...
SDL_Ecc_AggrEDCErrorSubType
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:190
SDL_ECC_getStaticRegisters
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
Gets the static registers for the specified ECC instance.
SDL_ECC_AGGR_TYPE_INJECT_ONLY
@ SDL_ECC_AGGR_TYPE_INJECT_ONLY
Definition: sdl_ecc.h:248
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
Definition: sdl_ecc.h:268
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:264
SDL_ECC_selfTest
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
Runs self test by injecting and error and monitor response Assumes ECC is already enabled.
SDL_ECC_ErrorInfo_t::bitErrorGroup
uint32_t bitErrorGroup
Definition: sdl_ecc.h:363
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
Definition: sdl_ecc.h:270
SDL_ECC_ErrorInfo_t::intrSrc
SDL_Ecc_AggrIntrSrc intrSrc
Definition: sdl_ecc.h:357
SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
Definition: sdl_ecc.h:272
sdl_common.h
Header file contains enumerations, structure definitions and function declarations for SDL COMMON int...
SDL_ECC_InjectErrorConfig_t
Definition: sdl_ecc.h:338
SDL_INJECT_ECC_NO_ERROR
@ SDL_INJECT_ECC_NO_ERROR
Definition: sdl_ecc.h:262
sdl_ip_ecc.h
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:339
SDL_ECC_staticRegs
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:310
SDL_ECC_AGGR_TYPE_FULL_FUNCTION
@ SDL_ECC_AGGR_TYPE_FULL_FUNCTION
Definition: sdl_ecc.h:250
SDL_ECC_VIMDEDVector_t
void(* SDL_ECC_VIMDEDVector_t)(void)
Definition: sdl_ecc.h:313
SDL_ECC_InjectErrorType
SDL_ECC_InjectErrorType
ECC Inject error types.
Definition: sdl_ecc.h:260
SDL_ECC_initEsm
int32_t SDL_ECC_initEsm(const SDL_ESM_Inst esmInstType)
Initializes an module for usage with ECC module.
SDL_ECC_ErrorInfo_t::bitErrorOffset
uint64_t bitErrorOffset
Definition: sdl_ecc.h:365
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:341
SDL_ECC_AggregatorType
SDL_ECC_AggregatorType
Definition: sdl_ecc.h:247
SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
Definition: sdl_ecc.h:274
SDL_ECC_RAM_ID_TYPE_INTERCONNECT
@ SDL_ECC_RAM_ID_TYPE_INTERCONNECT
Definition: sdl_ecc.h:289
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
SDL_ECC_getESMErrorInfo
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
SDL_ECC_ErrorInfo_t
Definition: sdl_ecc.h:352
SDL_ECC_InitConfig_t::pMemSubTypeList
SDL_ECC_MemSubType * pMemSubTypeList
Definition: sdl_ecc.h:329
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:298
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:276
SDL_ECC_clearNIntrPending
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
SDL_ECC_ErrorInfo_t::injectBitErrCnt
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:361
SDL_ECC_getErrorInfo
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ECC_ErrorInfo_t::bitErrCnt
uint32_t bitErrCnt
Definition: sdl_ecc.h:359
SDL_ECC_ErrorInfo_t::eccMemType
SDL_ECC_MemType eccMemType
Definition: sdl_ecc.h:353
SDL_ECC_applicationCallbackFunction
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
Application provided external callback function for ECC handling Called inside the reference function...
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:278
SDL_ECC_RamIdType
SDL_ECC_RamIdType
Definition: sdl_ecc.h:286
SDL_ECC_RAM_ID_TYPE_WRAPPER
@ SDL_ECC_RAM_ID_TYPE_WRAPPER
Definition: sdl_ecc.h:287
SDL_ECC_MemType
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:305
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SDL_ECC_tpccParity
int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType, uint32_t bitValue, uint32_t paramregvalue, uint32_t regval)
Injects TPCC Parity error.