AM273x MCU+ SDK  08.06.00
sdl_ecc_bus_safety_soc.h
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1 /*
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3  *
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33 
39 #ifndef SDL_ECC_BUS_SAFETY_SOC_H_
40 #define SDL_ECC_BUS_SAFETY_SOC_H_
41 
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45 
46 #include <sdl/include/am273x/sdlr_soc_baseaddress.h>
47 #include <sdl/include/am273x/sdlr_mss_ctrl.h>
48 #include <sdl/include/am273x/sdlr_dss_ctrl.h>
49 
50 #ifdef _cplusplus
51 extern "C" {
52 #endif
53 
54 /* ========================================================================== */
55 /* Macros & Typedefs */
56 /* ========================================================================== */
57 /* MSS CTRL BASE Address */
58 #define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
59 /* DSS CTRL base Address */
60 #define SDL_ECC_BUS_SAFETY_DSS_BUS_CFG (uint32_t)SDL_DSS_CTRL_U_BASE
61 #define DWORD (0x20U)
62 /* Adress of different memory section */
63 /* DSS_CMC */
64 #define SDL_DSS_CMC_COMP_U_END (SDL_DSS_CMC_COMP_U_BASE + 0X3FFCU-DWORD)
65 /* DSS MCRC */
66 #define SDL_DSS_MCRC_U_END (SDL_DSS_MCRC_U_BASE + 0x144U-DWORD)
67 /* DSS CBUFF FIFO */
68 #define SDL_DSS_CBUFF_FIFO_U_END (SDL_DSS_CBUFF_FIFO_U_BASE + 0X3FFCU-DWORD)
69 /* DSS MDO FIFO */
70 #define SDL_DSS_MDO_FIFO_U_END (SDL_DSS_MDO_FIFO_U_BASE + SDL_DSS_MDO_FIFO_U_SIZE-DWORD)
71 /* DSS BANK A */
72 #define SDL_DSS_L3_BANKA_ADDRESS SDL_DSS_L3_U_BASE
73 #define SDL_DSS_L3_BANK_SIZE (0x100000U)
74 /* DSS BANK B */
75 #define SDL_DSS_L3_BANKB_ADDRESS SDL_DSS_L3_BANKA_ADDRESS+SDL_DSS_L3_BANK_SIZE
76 /* DSS BANK C */
77 #define SDL_DSS_L3_BANKC_ADDRESS SDL_DSS_L3_BANKB_ADDRESS+SDL_DSS_L3_BANK_SIZE
78 /* DSS BANK D */
79 #define SDL_DSS_L3_BANKD_ADDRESS SDL_DSS_L3_BANKC_ADDRESS+SDL_DSS_L3_BANK_SIZE
80 /* DSS L3 */
81 #define SDL_DSS_L3_END_ADDRESS (SDL_DSS_L3_U_BASE+SDL_DSS_L3_U_SIZE)
82 /* DSS BANK A END Address*/
83 #define SDL_DSS_L3_BANKA_ADDRESS_END (SDL_DSS_L3_BANKB_ADDRESS-DWORD)
84 /* DSS BANK B END Address*/
85 #define SDL_DSS_L3_BANKB_ADDRESS_END (SDL_DSS_L3_BANKC_ADDRESS-DWORD)
86 /* DSS BANK C END Address*/
87 #define SDL_DSS_L3_BANKC_ADDRESS_END (SDL_DSS_L3_BANKD_ADDRESS-DWORD)
88 /* DSS BANK D END Address*/
89 #define SDL_DSS_L3_BANKD_ADDRESS_END (SDL_DSS_L3_END_ADDRESS-DWORD)
90 /* DSS HWA DMA 0 */
91 #define SDL_DSS_HWA_DMA0_U_BASE_END (SDL_DSS_HWA_DMA0_U_BASE+SDL_DSS_HWA_DMA0_U_SIZE-DWORD)
92 /* DSS HWA DMA 1 */
93 #define SDL_DSS_HWA_DMA1_U_BASE_END (SDL_DSS_HWA_DMA1_U_BASE+SDL_DSS_HWA_DMA1_U_SIZE-DWORD)
94 /* DSS MAILBOX*/
95 #define SDL_DSS_MAILBOX_U_BASE_END (SDL_DSS_MAILBOX_U_BASE+SDL_DSS_MAILBOX_U_SIZE-DWORD)
96 /* DSS L2*/
97 #define SDL_DSS_L2_U_BASE_END (SDL_DSS_L2_U_BASE+SDL_DSS_L2_U_SIZE-DWORD)
98 /* MSS DMM A DATA */
99 #define SDL_MSS_DMM_A_DATA_U_BASE_END (SDL_MSS_DMM_A_DATA_U_BASE+0x90U-DWORD)
100 /* MSS GPADC DATA RAM */
101 #define SDL_MSS_GPADC_DATA_RAM_U_BASE_END (SDL_MSS_GPADC_DATA_RAM_U_BASE+SDL_MSS_GPADC_DATA_RAM_U_SIZE-DWORD)
102 /* MSS L2 */
103 #define SDL_MSS_L2_U_BASE_END (SDL_MSS_L2_U_BASE+SDL_MSS_L2_U_SIZE-DWORD)
104 /* MSS L2 A */
105 #define SDL_MSS_L2_A_BASE_START (0x10200000U)
106 #define SDL_MSS_L2_A_BASE_END (SDL_MSS_L2_A_BASE_START+0X7FFFCU-DWORD)
107 /* MSS L2 B */
108 #define SDL_MSS_L2_B_BASE_START (0x102E0000U)
109 #define SDL_MSS_L2_B_BASE_END (SDL_MSS_L2_B_BASE_START+0X6FFFCU-DWORD)
110 /* MSS DMM */
111 #define SDL_MSS_DMM_A_DATA_U_BASE (0xCD000000U)
112 #define SDL_MSS_DMM_B_DATA_U_BASE (0xCD010000U)
113 /* MSS CR5A AHB */
114 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (SDL_MSS_CTRL_R5A_AHB_BASE )
115 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5A_AHB_BASE + SDL_MSS_CTRL_R5A_AHB_SIZE-DWORD)
116 /* MSS CR5B AHB */
117 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (SDL_MSS_CTRL_R5B_AHB_BASE )
118 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5B_AHB_BASE + SDL_MSS_CTRL_R5B_AHB_SIZE-DWORD)
119 /* MSS MBOX */
120 #define SDL_MSS_MBOX_U_END (SDL_MSS_MBOX_U_BASE+ 0x00001FFCU-DWORD)
121 /* MSS QSPI */
122 #define SDL_MSS_QSPI_U_END (0xC8000070U-DWORD)
123 /* MSS MCRC */
124 #define SDL_MSS_MCRC_U_SIZE (0x00000144U)
125 #define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE-DWORD)
126 /* MSS SWBUF */
127 #define SDL_MSS_SWBUF_U_BASE (SDL_MSS_RETRAM_U_BASE)
128 #define SDL_MSS_SWBUF_U_SIZE (0x000007FCU)
129 #define SDL_MSS_SWBUF_U_END (SDL_MSS_SWBUF_U_BASE + SDL_MSS_SWBUF_U_SIZE-DWORD)
130 /* MSS TO MDO */
131 #define SDL_MSS_TO_MDO_U_BASE (0xCA000000U)
132 #define SDL_MSS_TO_MDO_U_END (0xCA00FFFCU-DWORD)
133 
134 /* Macro defines Ecc Bus Safety Nodes in the DSS Subsystem */
135 #define SDL_ECC_BUS_SAFETY_DSS_DSP_MDMA 0U
136 #define SDL_ECC_BUS_SAFETY_DSS_L3_BANKA 1U
137 #define SDL_ECC_BUS_SAFETY_DSS_L3_BANKB 2U
138 #define SDL_ECC_BUS_SAFETY_DSS_L3_BANKC 3U
139 #define SDL_ECC_BUS_SAFETY_DSS_L3_BANKD 4U
140 #define SDL_ECC_BUS_SAFETY_DSS_DSP_SDMA 5U
141 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_A0_RD 6U
142 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_A1_RD 7U
143 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_B0_RD 8U
144 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_B1_RD 9U
145 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C0_RD 10U
146 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C1_RD 11U
147 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C2_RD 12U
148 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C3_RD 13U
149 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C4_RD 14U
150 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C5_RD 15U
151 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_A0_WR 16U
152 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_A1_WR 17U
153 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_B0_WR 18U
154 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_B1_WR 19U
155 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C0_WR 20U
156 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C1_WR 21U
157 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C2_WR 22U
158 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C3_WR 23U
159 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C4_WR 24U
160 #define SDL_ECC_BUS_SAFETY_DSS_TPTC_C5_WR 25U
161 #define SDL_ECC_BUS_SAFETY_DSS_CBUFF_FIFO 26U
162 #define SDL_ECC_BUS_SAFETY_DSS_MCRC 27U
163 #define SDL_ECC_BUS_SAFETY_DSS_PCR 28U
164 #define SDL_ECC_BUS_SAFETY_DSS_HWA_DMA0 29U
165 #define SDL_ECC_BUS_SAFETY_DSS_HWA_DMA1 30U
166 #define SDL_ECC_BUS_SAFETY_DSS_MBOX 31U
167 #define SDL_ECC_BUS_SAFETY_DSS_MDO_FIFO 32U
168 
169 /* Macro defines Ecc Bus Safety Nodes in the MSS Subsystem */
170 #define SDL_ECC_BUS_SAFETY_MSS_MBOX 0U
171 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 1U
172 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 2U
173 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_B0_RD 3U
174 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 4U
175 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 5U
176 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_B0_WR 6U
177 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 7U
178 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 8U
179 #define SDL_ECC_BUS_SAFETY_MSS_SCRP 9U
180 #define SDL_ECC_BUS_SAFETY_MSS_DMM 10U
181 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 11U
182 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 12U
183 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 13U
184 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 14U
185 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 15U
186 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 16U
187 #define SDL_ECC_BUS_SAFETY_MSS_QSPI 17U
188 #define SDL_ECC_BUS_SAFETY_MSS_CPSW 18U
189 #define SDL_ECC_BUS_SAFETY_MSS_MCRC 19U
190 #define SDL_ECC_BUS_SAFETY_MSS_PCR 20U
191 #define SDL_ECC_BUS_SAFETY_MSS_PCR2 21U
192 #define SDL_ECC_BUS_SAFETY_MSS_L2_A 22U
193 #define SDL_ECC_BUS_SAFETY_MSS_L2_B 23U
194 #define SDL_ECC_BUS_SAFETY_MSS_SWBUF 24U
195 #define SDL_ECC_BUS_SAFETY_MSS_GPADC 25U
196 #define SDL_ECC_BUS_SAFETY_MSS_DMM_SLV 26U
197 #define SDL_ECC_BUS_SAFETY_MSS_TO_MDO 27U
198 #define SDL_ECC_BUS_SAFETY_DAP_R232 28U
199 
200 #ifdef _cplusplus
201 }
202 
203 #endif /*extern "C" */
204 
205 #endif
206