AM273x MCU+ SDK  08.05.00
hwa/v0/hwa.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
67 #ifndef HWA_H_
68 #define HWA_H_
69 
70 /* ========================================================================== */
71 /* Include Files */
72 /* ========================================================================== */
73 
74 #include <stdint.h>
75 #include <stddef.h>
76 #include <stdbool.h>
77 #include <drivers/hw_include/csl_complex_math_types.h>
78 #include <kernel/dpl/HwiP.h>
79 #include <drivers/hw_include/cslr_hwa.h>
80 
81 #ifdef __cplusplus
82 extern "C" {
83 #endif
84 
85 /* ========================================================================== */
86 /* Macros & Typedefs */
87 /* ========================================================================== */
88 
90 #define HWADRV_ADDR_TRANSLATE_CPU_TO_HWA(x) (uint32_t)((uint32_t)(x) & 0x000FFFFFU)
91 
99 #define HWA_ERRNO_BASE (-2800)
100 
101 #define HWA_EINVAL (HWA_ERRNO_BASE-1)
102 
103 #define HWA_ENOINIT (HWA_ERRNO_BASE-2)
104 
105 #define HWA_EOUTOFRANGE (HWA_ERRNO_BASE-3)
106 
107 #define HWA_EOUTOFMEM (HWA_ERRNO_BASE-4)
108 
109 #define HWA_ENOTSUPP (HWA_ERRNO_BASE-5)
110 
111 #define HWA_EINUSE (HWA_ERRNO_BASE-6)
112 
113 #define HWA_ENOTALIGNED (HWA_ERRNO_BASE-7)
114 
115 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET (HWA_ERRNO_BASE-8)
116 
117 #define HWA_EINVAL_COMMON_REGISTER_PARAMSET_ALT (HWA_ERRNO_BASE-9)
118 
119 #define HWA_EINVAL_COMMON_REGISTER_FFTCONFIG (HWA_ERRNO_BASE-10)
120 
121 #define HWA_EINVAL_COMMON_REGISTER_DCEST (HWA_ERRNO_BASE-11)
122 
123 #define HWA_EINVAL_COMMON_REGISTER_CFAR (HWA_ERRNO_BASE-12)
124 
125 #define HWA_EINVAL_COMMON_REGISTER_INTERFERENCE (HWA_ERRNO_BASE-13)
126 
127 #define HWA_EINVAL_COMMON_REGISTER_COMPLEXMULT (HWA_ERRNO_BASE-14)
128 
129 #define HWA_EINVAL_COMMON_REGISTER_CHANCOMB (HWA_ERRNO_BASE-15)
130 
131 #define HWA_EINVAL_COMMON_REGISTER_ZEROINSERT (HWA_ERRNO_BASE-16)
132 
133 #define HWA_EINVAL_COMMON_REGISTER_ADVSTAT (HWA_ERRNO_BASE-17)
134 
135 #define HWA_EINVAL_COMMON_REGISTER_COMPRESS (HWA_ERRNO_BASE-18)
136 
137 #define HWA_EINVAL_COMMON_REGISTER_LOCALMAXIMUM (HWA_ERRNO_BASE-19)
138 
139 #define HWA_EINVAL_PARAMSET_GENERALCONFIG (HWA_ERRNO_BASE - 20)
140 
141 #define HWA_EINVAL_PARAMSET_SOURCE (HWA_ERRNO_BASE - 21)
142 
143 #define HWA_EINVAL_PARAMSET_DEST (HWA_ERRNO_BASE - 22)
144 
145 #define HWA_EINVAL_PARAMSET_SRCDST_ADDRESS (HWA_ERRNO_BASE - 23)
146 
147 #define HWA_EINVAL_PARAMSET_FFTMODE_GENERALCONFIG (HWA_ERRNO_BASE - 24)
148 
149 #define HWA_EINVAL_PARAMSET_FFTMODE_SIZE (HWA_ERRNO_BASE - 25)
150 
151 #define HWA_EINVAL_PARAMSET_FFTMODE_POSTPROC (HWA_ERRNO_BASE - 26)
152 
153 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC (HWA_ERRNO_BASE - 27)
154 
155 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_INTERF (HWA_ERRNO_BASE - 28)
156 
157 #define HWA_EINVAL_PARAMSET_FFTMODE_PREPROC_COMPLEXMULT (HWA_ERRNO_BASE - 29)
158 
159 #define HWA_EINVAL_PARAMSET_CFARMODE_GENERALCONFIG (HWA_ERRNO_BASE - 30)
160 
161 #define HWA_EINVAL_PARAMSET_CFARMODE_OSCONFIG (HWA_ERRNO_BASE - 31)
162 
163 #define HWA_EINVAL_PARAMSET_CFARMODE_CACONFIG (HWA_ERRNO_BASE - 32)
164 
165 #define HWA_EINVAL_PARAMSET_COMPRESSMODE (HWA_ERRNO_BASE - 33)
166 
167 #define HWA_EINVAL_PARAMSET_LOCALMAXMODE (HWA_ERRNO_BASE - 34)
168 
169 #define HWA_PARAMSET_POLLINGNOTALLOWED (HWA_ERRNO_BASE - 35)
170 
173 #define HWA_NUM_RXCHANNELS (12U)
174 
175 #define HWA_NUM_INTERFMITG_WINARRAY (5U)
176 
177 #define HWA_BPMPATTERN_LENGTH_INWORDS (8U)
178 
179 #define HWA_CHANCOMB_LENGTH_INWORDS (8U)
180 
181 #define HWA_ZEROINSERT_LENGTH_INWORDS (8U)
182 
183 #define HWA_NUM_RAMS (10U)
184 
185 #define HWA_MAXNUM_LOOPS (4095U)
186 
187 #define HWA_CMP_K_ARR_LEN (8U)
188 
202 #define HWA_DONE_INTERRUPT_PRIORITY (1U)
203 
204 #define HWA_ALTDONE_INTERRUPT_PRIORITY (1U)
205 
206 #define HWA_PARAMSETDONE_INTERRUPT1_PRIORITY (1U)
207 
208 #define HWA_PARAMSETDONE_INTERRUPT2_PRIORITY (1U)
209 
210 #define HWA_LOCAL_RAM_ERR_PRIORITY (1U)
211 
218 #define HWA_FEATURE_BIT_ENABLE ((uint8_t)1U)
219 #define HWA_FEATURE_BIT_DISABLE ((uint8_t)0U)
227 #define HWA_SAMPLES_WIDTH_16BIT ((uint8_t)0U)
228 #define HWA_SAMPLES_WIDTH_32BIT ((uint8_t)1U)
236 #define HWA_SAMPLES_FORMAT_COMPLEX ((uint8_t)0U)
237 #define HWA_SAMPLES_FORMAT_REAL ((uint8_t)1U)
245 #define HWA_SAMPLES_UNSIGNED ((uint8_t)0U)
246 #define HWA_SAMPLES_SIGNED ((uint8_t)1U)
254 #define HWA_FFT_WINDOW_NONSYMMETRIC ((uint8_t)0U)
255 #define HWA_FFT_WINDOW_SYMMETRIC ((uint8_t)1U)
267 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_NONE ((uint8_t)0U)
268 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_4K ((uint8_t)2U)
269 #define HWA_FFT_WINDOW_INTERPOLATE_MODE_8K ((uint8_t)1U)
277 #define HWA_FFT_MODE_MAGNITUDE_LOG2_DISABLED ((uint8_t)0U)
278 #define HWA_FFT_MODE_MAGNITUDE_ONLY_ENABLED ((uint8_t)2U)
279 #define HWA_FFT_MODE_MAGNITUDE_LOG2_ENABLED ((uint8_t)3U)
287 #define HWA_FFT_MODE_OUTPUT_DEFAULT ((uint8_t)0U)
288 #define HWA_FFT_MODE_OUTPUT_MAX_STATS ((uint8_t)2U)
289 #define HWA_FFT_MODE_OUTPUT_SUM_STATS ((uint8_t)3U)
297 #define HWA_NOISE_AVG_MODE_CFAR_CA ((uint8_t)0U)
298 #define HWA_NOISE_AVG_MODE_CFAR_CAGO ((uint8_t)1U)
299 #define HWA_NOISE_AVG_MODE_CFAR_CASO ((uint8_t)2U)
300 #define HWA_NOISE_AVG_MODE_CFAR_OS ((uint8_t)3U)
308 #define HWA_TRIG_MODE_IMMEDIATE ((uint8_t)0U)
309 #define HWA_TRIG_MODE_SOFTWARE ((uint8_t)1U)
310 #define HWA_TRIG_MODE_RESERVED1 ((uint8_t)2U)
311 #define HWA_TRIG_MODE_DMA ((uint8_t)3U)
312 #define HWA_TRIG_MODE_HARDWARE ((uint8_t)4U)
313 #define HWA_TRIG_MODE_RESERVED2 ((uint8_t)5U)
314 #define HWA_TRIG_MODE_RESERVED3 ((uint8_t)6U)
315 #define HWA_TRIG_MODE_M4CONTROL ((uint8_t)7U)
323 #define HWA_CONTEXTSWITCH_TRIG_MODE_DMA ((uint8_t)3U)
324 #define HWA_CONTEXTSWITCH_TRIG_MODE_HARDWARE ((uint8_t)4U)
325 #define HWA_CONTEXTSWITCH_TRIG_MODE_SOFTWARE ((uint8_t)5U)
333 #define HWA_THREAD_BACKGROUNDCONTEXT ((uint8_t)0U)
334 #define HWA_THREAD_ALTCONTEXT ((uint8_t)1U)
342 #define HWA_ACCELMODE_FFT ((uint8_t)0U)
343 #define HWA_ACCELMODE_CFAR ((uint8_t)1U)
344 #define HWA_ACCELMODE_COMPRESS ((uint8_t)2U)
345 #define HWA_ACCELMODE_LOCALMAX ((uint8_t)3U)
346 #define HWA_ACCELMODE_NONE ((uint8_t)7U)
366 #define HWA_CFAR_OPER_MODE_LOG_INPUT_REAL 0U
367 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX 1U
368 #define HWA_CFAR_OPER_MODE_MAG_INPUT_REAL 2U
369 #define HWA_CFAR_OPER_MODE_MAG_INPUT_COMPLEX 3U
370 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_REAL 4U
371 #define HWA_CFAR_OPER_MODE_MAG_SQR_INPUT_COMPLEX 5U
372 #define HWA_CFAR_OPER_MODE_LOG_INPUT_COMPLEX_LINEARCFAR 6U
390 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_CUT ((uint8_t)0U)
392 #define HWA_CFAR_OUTPUT_MODE_I_nAVG_ALL_Q_DET_FLAG ((uint8_t)1U)
394 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_NEIGHBOR_NOISE_VAL ((uint8_t)2U)
396 #define HWA_CFAR_OUTPUT_MODE_I_PEAK_IDX_Q_CUT ((uint8_t)3U)
398 #define HWA_CFAR_OUTPUT_MODE_FILTER_LARGE_PEAK ((uint8_t)4U)
407 #define HWA_RAM_TYPE_WINDOW_RAM ((uint8_t)0U)
408 #define HWA_RAM_TYPE_VECTORMULTIPLY_RAM ((uint8_t)1U)
409 #define HWA_RAM_TYPE_LUT_FREQ_DEROTATE_RAM ((uint8_t)2U)
410 #define HWA_RAM_TYPE_SHUFFLE_RAM ((uint8_t)3U)
411 #define HWA_RAM_TYPE_HIST_THRESH_RAM ((uint8_t)4U)
412 #define HWA_RAM_TYPE_2DSTAT_ITER_VAL ((uint8_t)5U)
413 #define HWA_RAM_TYPE_2DSTAT_ITER_IDX ((uint8_t)6U)
414 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_VAL ((uint8_t)7U)
415 #define HWA_RAM_TYPE_2DSTAT_SAMPLE_IDX ((uint8_t)8U)
416 #define HWA_RAM_TYPE_HISTOGRAM_RAM ((uint8_t)9U)
424 #define HWA_CLIPREG_TYPE_DCACC ((uint8_t)0U)
425 #define HWA_CLIPREG_TYPE_DCEST ((uint8_t)1U)
426 #define HWA_CLIPREG_TYPE_DCSUB ((uint8_t)2U)
427 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGACC ((uint8_t)3U)
428 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFACC ((uint8_t)4U)
429 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGTHRESHOLD ((uint8_t)5U)
430 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFTHRESHOLD ((uint8_t)6U)
431 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGSUM ((uint8_t)7U)
432 #define HWA_CLIPREG_TYPE_INTFSTATS_MAGDIFFSUM ((uint8_t)8U)
433 #define HWA_CLIPREG_TYPE_TWIDINCR_DELTAFRAC ((uint8_t)9U)
434 #define HWA_CLIPREG_TYPE_CHANCOMB ((uint8_t)10U)
435 #define HWA_CLIPREG_TYPE_FFT ((uint8_t)11U)
436 #define HWA_CLIPREG_TYPE_INPUTFORMAT ((uint8_t)12U)
437 #define HWA_CLIPREG_TYPE_OUTPUTFORMAT ((uint8_t)13U)
445 #define HWA_ACCUMULATORREG_TYPE_DC ((uint8_t)0U)
446 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAG ((uint8_t)1U)
447 #define HWA_ACCUMULATORREG_TYPE_INTERF_MAGDIFF ((uint8_t)2U)
448 #define HWA_ACCUMULATORREG_TYPE_INTERF ((uint8_t)3U)
456 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAG ((uint8_t)0U)
457 #define HWA_INTERFERENCE_THRESHOLD_TYPE_MAGDIFF ((uint8_t)1U)
467 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR1 ((uint8_t)1U)
468 #define HWA_PARAMDONE_INTERRUPT_TYPE_CPU_INTR2 ((uint8_t)2U)
469 #define HWA_PARAMDONE_INTERRUPT_TYPE_DMA ((uint8_t)4U)
478 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG ((uint64_t)0x00000001U)
479 #define HWA_COMMONCONFIG_MASK_STATEMACHINE_CFG_ALT ((uint64_t)0x00000002U)
480 #define HWA_COMMONCONFIG_CONTEXTSWITCH_TRIG_CFG ((uint64_t)0x00000004U)
481 #define HWA_COMMONCONFIG_MASK_BPMCFG ((uint64_t)0x00000008U)
482 #define HWA_COMMONCONFIG_MASK_TWIDDITHERENABLE ((uint64_t)0x00000010U)
483 #define HWA_COMMONCONFIG_MASK_LFSRSEED ((uint64_t)0x00000020U)
484 #define HWA_COMMONCONFIG_MASK_FFTSUMDIV ((uint64_t)0x00000040U)
485 #define HWA_COMMONCONFIG_MASK_CFARTHRESHOLDSCALE ((uint64_t)0x00000080U)
486 #define HWA_COMMONCONFIG_MASK_DCEST_SCALESHIFT ((uint64_t)0x00000100U)
487 #define HWA_COMMONCONFIG_MASK_DCSUB_SWVAL ((uint64_t)0x00000200U)
488 #define HWA_COMMONCONFIG_MASK_INTERFMAG_THRESHOLD ((uint64_t)0x00000400U)
489 #define HWA_COMMONCONFIG_MASK_INTERFMAGDIFF_THRESHOLD ((uint64_t)0x00000800U)
490 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAG ((uint64_t)0x00001000U)
491 #define HWA_COMMONCONFIG_MASK_INTERFSUM_MAGDIFF ((uint64_t)0x00002000U)
492 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALEARRAY ((uint64_t)0x00004000U)
495 #define HWA_COMMONCONFIG_MASK_COMPLEXMULT_SCALECONST ((uint64_t)0x00008000U)
498 #define HWA_COMMONCONFIG_MASK_RECWIN_RESET ((uint64_t)0x00010000U)
499 #define HWA_COMMONCONFIG_MASK_TWIDINCR_DELTA_FRAC ((uint64_t)0x00020000U)
501 #define HWA_COMMONCONFIG_MASK_CHANCOMB_VEC_SIZE ((uint64_t)0x00400000U)
502 #define HWA_COMMONCONFIG_MASK_ZEROINSERT_NUM_MASK ((uint64_t)0x00800000U)
503 #define HWA_COMMONCONFIG_MASK_MAX2D_OFFSETBOTHDIM ((uint64_t)0x01000000U)
504 #define HWA_COMMONCONFIG_MASK_CDFCNT_THRESHOLD ((uint64_t)0x02000000U)
505 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMB_THRESHOLDSW ((uint64_t)0x04000000U)
506 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMC_THRESHOLDSW ((uint64_t)0x08000000U)
507 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMBTHRESH_OFFSET ((uint64_t)0x10000000U)
508 #define HWA_COMMONCONFIG_MASK_LOCALMAXDIMCTHRESH_OFFSET ((uint64_t)0x20000000U)
509 #define HWA_COMMONCONFIG_MASK_INTERF_MITG_WINDOW_PARAM ((uint64_t)0x40000000U)
510 #define HWA_COMMONCONFIG_MASK_EGECOMRESS_KPARAM ((uint64_t)0x80000000U)
512 #if defined (SOC_AWR294X)
513 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED0 ((uint64_t)0x100000000U)
514 #define HWA_COMMONCONFIG_MASK_CMP_LFSRSEED1 ((uint64_t)0x200000000U)
515 #define HWA_COMMONCONFIG_MASK_SW_RESTART_LOOP ((uint64_t)0x400000000U)
516 #endif
517 
525 #define HWA_SRC_SHUFFLE_AB_MODE_DISABLE ((uint8_t)0U)
526 #define HWA_SRC_SHUFFLE_AB_MODE_ADIM ((uint8_t)1U)
527 #define HWA_SRC_SHUFFLE_AB_MODE_BDIM ((uint8_t)2U)
535 #define HWA_COMPLEX_MULTIPLY_MODE_DISABLE ((uint8_t)0U)
536 #define HWA_COMPLEX_MULTIPLY_MODE_FREQ_SHIFTER ((uint8_t)1U)
537 #define HWA_COMPLEX_MULTIPLY_MODE_SLOW_DFT ((uint8_t)2U)
538 #define HWA_COMPLEX_MULTIPLY_MODE_FFT_STITCHING ((uint8_t)3U)
539 #define HWA_COMPLEX_MULTIPLY_MODE_MAG_SQUARED ((uint8_t)4U)
540 #define HWA_COMPLEX_MULTIPLY_MODE_SCALAR_MULT ((uint8_t)5U)
541 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT ((uint8_t)6U)
542 #define HWA_COMPLEX_MULTIPLY_MODE_VECTOR_MULT_2 ((uint8_t)7U)
543 #define HWA_COMPLEX_MULTIPLY_MODE_RECURSIVE_WIN ((uint8_t)8U)
544 #define HWA_COMPLEX_MULTIPLY_MODE_LUT_FREQ_DEROTATE ((uint8_t)9U)
545 #define HWA_COMPLEX_MULTIPLY_MODE_FREQSHIFT_FREQINCREMENT ((uint8_t)10U)
554 #define HWA_FFT_STITCHING_TWID_PATTERN_4K ((uint8_t)1U)
555 #define HWA_FFT_STITCHING_TWID_PATTERN_8K ((uint8_t)2U)
564 #define HWA_RECURSIVE_WIN_MODE_SELECT_ITERATION_COUNT ((uint8_t)0U)
565 #define HWA_FFT_STITCHING_TWID_PATTERN_EXE_COUNT ((uint8_t)1U)
573 #define HWA_WINDOW_MODE_18BITREAL ((uint8_t)0U)
575 #define HWA_WINDOW_MODE_16BITREAL ((uint8_t)1U)
577 #define HWA_WINDOW_MODE_COMPLEX ((uint8_t)2U)
586 #define HWA_FFT3x_BFLY_SCALING_MSBSATURATED ((uint8_t)0U)
587 #define HWA_FFT3x_BFLY_SCALING_MSBSATLSBRND ((uint8_t)1U)
589 #define HWA_FFT3x_BFLY_SCALING_LSBROUNDED ((uint8_t)2U)
598 #define HWA_DCEST_INTERFSUM_RESET_MODE_NOUPDATE ((uint8_t)0U)
599 #define HWA_DCEST_INTERFSUM_RESET_MODE_SOFTWARERESET ((uint8_t)1U)
600 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET ((uint8_t)2U)
601 #define HWA_DCEST_INTERFSUM_RESET_MODE_PARAMRESET_ZEROLPCONT ((uint8_t)3U)
609 #define HWA_INTERFTHRESH_MODE_MAG_OR_MAGDIF ((uint8_t)0U)
610 #define HWA_INTERFTHRESH_MODE_MAGDIFF ((uint8_t)1U)
611 #define HWA_INTERFTHRESH_MODE_MAG ((uint8_t)2U)
612 #define HWA_INTERFTHRESH_MODE_MAG_AND_MAGDIFF ((uint8_t)3U)
620 #define HWA_DCSUB_SELECT_DCSW ((uint8_t)0U)
621 #define HWA_DCSUB_SELECT_DCEST ((uint8_t)1U)
629 #define HWA_INTERFTHRESH_SELECT_SW ((uint8_t)0U)
631 #define HWA_INTERFTHRESH_SELECT_EST_AVERAGE ((uint8_t)1U)
633 #define HWA_INTERFTHRESH_SELECT_EST_INDIVIDUAL ((uint8_t)2U)
642 #define HWA_INTERFMITIGATION_PATH_ZEROOUT ((uint8_t)0U)
643 #define HWA_INTERFMITIGATION_PATH_WINDOWZEROOUT ((uint8_t)1U)
644 #define HWA_INTERFMITIGATION_PATH_LINEARINTERPOLATION ((uint8_t)2U)
645 #define HWA_INTERFMITIGATION_PATH_UNUSED ((uint8_t)3U)
656 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_WRAPAROUND ((uint8_t)0U)
657 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_AUTOINCR_SATURATED ((uint8_t)1U)
658 #define HWA_LUT_FREQ_DEROTATE_RAMIDX_NONINCR ((uint8_t)2U)
666 #define HWA_HISTOGRAM_MODE_DISABLED ((uint8_t)0U)
667 #define HWA_HISTOGRAM_MODE_HISTOGRAM ((uint8_t)1U)
668 #define HWA_HISTOGRAM_MODE_CDF ((uint8_t)2U)
669 #define HWA_HISTOGRAM_MODE_CDF_THRESHOLD ((uint8_t)3U)
677 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_EN ((uint8_t)0U)
678 #define HWA_LOCALMAX_THRESH_BITMASK_CDIM_EN ((uint8_t)1U)
679 #define HWA_LOCALMAX_THRESH_BITMASK_BDIM_EN ((uint8_t)2U)
680 #define HWA_LOCALMAX_THRESH_BITMASK_BOTH_DIS ((uint8_t)3U)
688 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCREG ((uint8_t)0U)
689 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCREG ((uint8_t)1U)
690 #define HWA_LOCALMAX_THRESH_SELECT_DIMBREG_DIMCRAM ((uint8_t)2U)
691 #define HWA_LOCALMAX_THRESH_SELECT_DIMBRAM_DIMCRAM ((uint8_t)3U)
699 #define HWA_COMPRESS_METHOD_EGE ((uint8_t)0U)
700 #define HWA_COMPRESS_METHOD_BFP ((uint8_t)1U)
708 #define HWA_CMP_DCMP_COMPRESS ((uint8_t)0U)
709 #define HWA_CMP_DCMP_DECOMPRESS ((uint8_t)1U)
717 #define HWA_COMPRESS_PATHSELECT_BOTHPASSES ((uint8_t)3U)
718 #define HWA_COMPRESS_PATHSELECT_SECONDPASS ((uint8_t)1U)
730 #define HWA_PARAMSET_CONTEXTSWITCH_DISABLE (0U)
731 
732 #define HWA_PARAMSET_CONTEXTSWITCH_NONFORCE_ENABLE (1U)
733 
735 #define HWA_PARAMSET_CONTEXTSWITCH_FORCE_ENABLE (2U)
736 
744 #define HWA_APP_MEMINIT_PARAM_RAM (1U << 8U)
745 
746 #define HWA_APP_MEMINIT_WINDOW_RAM (1U << 9U)
747 
748 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM (1U << 10U)
749 
750 #define HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM (1U << 11U)
751 
752 #define HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM (1U << 12U)
753 
754 #define HWA_APP_MEMINIT_HIST_EVEN_RAM (1U << 13U)
755 
756 #define HWA_APP_MEMINIT_HIST_ODD_RAM (1U << 14U)
757 
758 #define HWA_APP_MEMINIT_MEMBANK_ALL (HWA_APP_MEMINIT_PARAM_RAM | \
759  HWA_APP_MEMINIT_WINDOW_RAM | \
760  HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_EVEN_RAM | \
761  HWA_APP_MEMINIT_PER_SAMPLE_MAX_VAL_ODD_RAM | \
762  HWA_APP_MEMINIT_PER_ITER_MAX_VAL_RAM | \
763  HWA_APP_MEMINIT_HIST_EVEN_RAM | \
764  HWA_APP_MEMINIT_HIST_ODD_RAM )
765 
767 /* ========================================================================== */
768 /* Structures and Enums */
769 /* ========================================================================== */
770 
774 typedef void* HWA_Handle;
775 
782 typedef void (*HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void * arg);
783 
790 typedef void (*HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void * arg);
791 
798 typedef struct HWA_Attrs_t {
799  uint32_t instanceNum;
800  volatile uint32_t ctrlBaseAddr;
801  volatile uint32_t paramBaseAddr;
802  volatile uint32_t ramBaseAddr;
803  volatile uint32_t dssBaseAddr;
804  uint32_t numHwaParamSets;
805  uint32_t intNum1ParamSet;
806  uint32_t intNum2ParamSet;
807  uint32_t intNumDone;
808  uint32_t intNumDoneALT;
809  uint32_t intNumLocalRamErr;
810  uint32_t numDmaChannels;
811  volatile uint32_t accelMemBaseAddr;
812  uint32_t accelMemSize;
813  bool isConcurrentAccessAllowed;
815 } HWA_Attrs;
816 
823 typedef struct HWA_RAMAttrs_t
824 {
825  uint32_t ramBaseAddress;
826  uint32_t ramSizeInBytes;
827 } HWA_RAMAttrs;
828 
840 typedef struct HWA_SrcDMAConfig_t {
841  uint32_t srcAddr;
842  uint32_t destAddr;
843  uint16_t aCnt;
844  uint16_t bCnt;
845  uint16_t cCnt;
847 
854 typedef struct HWA_CommonConfig_t {
855  uint64_t configMask;
858  uint16_t numLoops;
862  uint16_t paramStartIdx;
865  uint16_t paramStopIdx;
868  uint16_t numLoopsALT;
871  uint16_t paramStartIdxALT;
874  uint16_t paramStopIdxALT;
877  uint8_t contextswitchTriggerMode;
880  uint8_t contextswitchTriggerSrc;
884 #if defined (SOC_AWR294X)
885  /* This Field is applicable for only AWR294x ES2.0 devices */
886  uint8_t swRestartLoop;
888 #endif
889  struct {
890  uint16_t bpmRate;
894  uint32_t bpmPattern[HWA_BPMPATTERN_LENGTH_INWORDS];
900  uint8_t twidDitherEnable;
905  uint32_t lfsrSeed;
908  uint8_t fftSumDiv;
912  } fftConfig;
913 
914 
915  struct {
916  uint16_t scale;
922  uint8_t shift;
927  } dcEstimateConfig;
928 
929  struct
930  {
931  int32_t swIVal[HWA_NUM_RXCHANNELS];
936  int32_t swQVal[HWA_NUM_RXCHANNELS];
940  } dcSubtractConfig;
941 
942 
943  struct {
944 
945  uint32_t thresholdMagSw[HWA_NUM_RXCHANNELS];
953  uint32_t thresholdMagDiffSw[HWA_NUM_RXCHANNELS];
961  uint8_t sumMagScale;
968  int8_t sumMagShift;
973  uint8_t sumMagDiffScale;
978  int8_t sumMagDiffShift;
983  uint8_t mitigationWindowParam[HWA_NUM_INTERFMITG_WINARRAY];
989  } interfConfig;
990 
991 
992  struct {
993 
994  int32_t Iscale[HWA_NUM_RXCHANNELS];
1000  int32_t Qscale[HWA_NUM_RXCHANNELS];
1006  int16_t twiddleDeltaFrac;
1014  uint8_t recWindowReset;
1017  } complexMultiplyConfig;
1019  struct {
1020 
1021  uint8_t size;
1025  uint32_t vector[HWA_CHANCOMB_LENGTH_INWORDS];
1033  } chanCombConfig;
1035  struct {
1036 
1037  uint8_t number;
1041  uint32_t mask[HWA_ZEROINSERT_LENGTH_INWORDS];
1048  } zeroInsertConfig;
1050  struct {
1051 
1052  uint32_t thresholdScale;
1059  } cfarConfig;
1061  struct {
1062 
1063  int32_t max2DoffsetDim1;
1067  int32_t max2DoffsetDim2;
1072  uint16_t cdfCntThresh;
1078  } advStatConfig;
1080  struct {
1081 
1082  uint16_t dimBThreshold;
1087  uint16_t dimCThreshold;
1092  uint16_t dimBBaseAddress;
1097  uint16_t dimCBaseAddress;
1101  } localMaxConfig;
1103  struct {
1104 
1105  uint8_t EGEKparam[HWA_CMP_K_ARR_LEN];
1110 #if defined (SOC_AWR294X) /* These fields are applicable for only ES2.0 devices. */
1111  uint32_t cmpLfsrSeed0;
1113  uint32_t cmpLfsrSeed1;
1115 #endif
1116 
1117  } compressConfig;
1118 
1120 
1127 typedef struct HWA_SourceConfig_t {
1128  uint32_t srcAddr;
1133  uint16_t srcAcnt;
1137  int32_t srcAIdx;
1140  uint16_t srcBcnt;
1142  int32_t srcBIdx;
1146  uint16_t srcCcnt;
1148  int32_t srcCIdx;
1152  uint16_t srcAcircShift;
1156  uint8_t srcAcircShiftWrap;
1163  uint16_t srcBcircShift;
1166  uint8_t srcBcircShiftWrap;
1173  uint16_t srcCcircShift;
1177  uint8_t srcCcircShiftWrap;
1184  uint8_t srcCircShiftWrap3;
1188  uint8_t shuffleMode ;
1191  uint8_t srcRealComplex;
1194  uint8_t srcWidth;
1197  uint8_t srcSign;
1204  uint8_t srcConjugate;
1213  uint8_t srcScale;
1220  uint8_t srcIQSwap;
1223  uint32_t wrapComb;
1227  uint8_t shuffleStart;
1231 
1238 typedef struct HWA_DestConfig_t {
1239 
1240  uint32_t dstAddr;
1245  uint16_t dstAcnt;
1250  int32_t dstAIdx;
1254  int32_t dstBIdx;
1259  uint8_t dstRealComplex;
1263  uint8_t dstWidth;
1267  uint8_t dstSign;
1274  uint8_t dstConjugate;
1283  uint8_t dstScale;
1286  uint16_t dstSkipInit;
1292  uint8_t dstIQswap; /* See \ref HWA_FEATURE_BIT macros for correct values
1293  sets bits DST_IQSWAP of register DST in paramset */
1294 } HWA_DestConfig;
1295 
1302 typedef struct HWA_PostProcStat_t {
1303 
1304  uint8_t magLogEn;
1309  uint8_t fftOutMode;
1317  uint8_t max2Denable;
1321  uint8_t histogramMode;
1326  uint8_t histogramScaleSelect;
1331  uint8_t histogramSizeSelect;
1336 
1343 typedef struct HWA_ComplexMultiply_t {
1344 
1345  uint8_t cmultMode;
1350  union {
1351  struct
1352  {
1353  uint16_t freqShiftTwiddleIncr;
1356  } freqShift;
1358  struct
1359  {
1360  uint16_t startFreq;
1365  } slowDFT;
1367  struct
1368  {
1369  uint16_t twiddlePattern;
1374  uint8_t winInterpolateMode;
1380  } FFTstitching;
1382  struct
1383  {
1384  uint8_t scaleCmultScaleEn;
1394  } scalerMultiply;
1396  struct
1397  {
1398  uint8_t cmultScaleEn;
1405  uint16_t vecMultiMode1RamAddrOffset;
1407  } vectorMultiplyMode1;
1409  struct
1410  {
1411  uint16_t vecMultiMode2RamAddrOffset;
1415  } vectorMultiplyMode2;
1417  struct
1418  {
1419  uint8_t recwinModeSel;
1422  } recursiveWin;
1424  struct
1425  {
1426  uint16_t ramAddrOffset;
1428  uint8_t ramIdxIncrMode;
1431  } lutFreqDerotate;
1433  struct
1434  {
1435  uint16_t twiddleIncr;
1438  } freqShiftWithFreIncrement;
1439  } modeCfg ;
1441 
1448 typedef struct HWA_PreProcessing_t {
1449 
1450  uint8_t dcEstResetMode;
1455  uint8_t dcSubEnable;
1459  uint8_t dcSubSelect;
1462  struct {
1463  uint8_t thresholdEnable;
1467  uint8_t thresholdMode;
1471  uint8_t thresholdSelect;
1476  } interfLocalize;
1477 
1478  struct {
1479  uint8_t resetMode;
1484  } interfStat;
1486  struct {
1487 
1488  uint8_t enable;
1492  uint8_t countThreshold;
1497  uint8_t pathSelect;
1501  uint8_t leftHystOrder;
1505  uint8_t rightHystOrder;
1509  } interfMitigation;
1510 
1511  uint8_t chanCombEn;
1516  uint8_t zeroInsertEn;
1521  HWA_ComplexMultiply complexMultiply;
1524 
1531 typedef struct HWA_AccelModeFFT_t{
1532  uint8_t fftEn;
1537  uint8_t fftSize;
1544  uint16_t butterflyScaling;
1551  uint8_t windowEn;
1555  uint16_t windowStart;
1560  uint8_t winSymm;
1565  uint8_t windowMode;
1568  uint8_t fftSize3xEn;
1573  uint8_t fftSizeDim2;
1578  uint8_t butterflyScalingFFT3x;
1583  uint8_t bpmEnable;
1589  uint8_t bpmPhase;
1592  HWA_PostProcStat postProcCfg;
1594  HWA_PreProcessing preProcCfg;
1596 
1603 typedef struct HWA_AccelModeCFAR_t{
1604  uint8_t numNoiseSamplesLeft;
1610  uint8_t numNoiseSamplesRight;
1615  uint8_t numGuardCells;
1617  uint8_t nAvgDivFactor;
1623  uint8_t nAvgMode;
1627  uint8_t cfarOsKvalue;
1630  uint8_t cfarOsEdgeKScaleEn;
1634  uint8_t operMode;
1637  uint8_t outputMode;
1641  uint8_t cfarAdvOutMode;
1646  uint8_t peakGroupEn;
1655  uint8_t cyclicModeEn;
1661 
1668 typedef struct HWA_AccelModeLocalMax_t{
1669 
1670  uint8_t neighbourBitmask;
1674  uint8_t thresholdBitMask;
1678  uint8_t thresholdMode;
1681  uint8_t dimBNonCyclic;
1683  uint8_t dimCNonCyclic;
1686 
1693 typedef struct HWA_AccelModeCompress_t {
1694  uint8_t EGEKidx;
1697  uint8_t EGEKarrayLength;
1700  uint8_t scaleFactorBW;
1705  uint8_t BFPMantissaBW;
1708  uint8_t scaleFactor;
1710  uint8_t passSelect;
1712  uint8_t headerEnable;
1716  uint8_t method;
1719  uint8_t compressDecompress;
1721  uint8_t ditherEnable;
1724 #if defined (SOC_AWR294X)
1725  /* These fields are applicable for only AWR294x ES2.0 devices. */
1726  uint8_t decrImagBitw;
1728  uint8_t cmpRoundEn;
1730  uint8_t selLfsr;
1732 #endif
1734 
1741 typedef struct HWA_ParamConfig_t {
1742  uint8_t triggerMode;
1744  uint8_t triggerSrc;
1750  uint8_t accelMode;
1755  HWA_SourceConfig source;
1758  union {
1761  HWA_AccelModeLocalMax localMaxMode;
1762  HWA_AccelModeCompress compressMode;
1763  } accelModeArgs;
1764 
1765  uint8_t contextswitchCfg;
1767 } HWA_ParamConfig;
1768 
1775 typedef struct HWA_InterruptConfig_t {
1776  uint8_t interruptTypeFlag;
1782  struct {
1783  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1784  void *callbackArg;
1785  } cpu;
1786  struct {
1787  uint8_t dstChannel;
1789  } dma;
1791 
1798 typedef struct HWA_Stats_t {
1799  uint32_t maxValue;
1800  uint16_t maxIndex;
1801  uint8_t iSumMSB;
1802  uint8_t qSumMSB;
1803  uint32_t iSumLSB;
1804  uint32_t qSumLSB;
1805 } HWA_Stats;
1806 
1811 typedef struct HWA_AccmulatorVal_t {
1812  uint32_t accValLSB;
1813  uint16_t accValMSB;
1815 
1822 typedef struct HWA_DebugStats_t {
1823  uint8_t currentParamSet;
1828  uint8_t paramSetIdxCpuIntr0;
1829  uint8_t paramSetIdxCpuIntr1;
1840  uint8_t fsmStateInfo;
1841  uint16_t currentLoopCount;
1843  uint16_t otherThreadLoopCount;
1844  uint32_t trigStatus[2];
1845 } HWA_DebugStats;
1846 
1853 typedef struct HWA_MemInfo_t {
1854  uint32_t baseAddress;
1855  uint16_t bankSize;
1856  uint16_t numBanks;
1857 } HWA_MemInfo;
1858 
1865 typedef struct HWA_CdfThreshold_t {
1867  uint32_t pdfValue : 12;
1868  uint32_t cdfValue : 12;
1869  uint32_t binNumber : 6;
1870  uint32_t reserved : 2;
1873 
1878 typedef struct HWA_InterruptPriority_t {
1880  uint32_t backgroundDone;
1881  uint32_t ALTDone;
1882  uint32_t paramsetDone1;
1883  uint32_t paramsetDone2;
1884  uint32_t loalRamErr;
1887 
1892 typedef struct HWA_OpenConfig_t {
1893 
1894  HWA_InterruptPriority interruptPriority ;
1907 } HWA_OpenConfig;
1908  /* end of HWA_DRIVER_EXTERNAL_DATA_STRUCTURE*/
1910 
1911 /* ========================================================================== */
1912 /* Internal/Private Structure Declarations */
1913 /* ========================================================================== */
1914 
1923 typedef struct HWA_InterruptCtx_t {
1924  HWA_ParamDone_IntHandlerFuncPTR callbackFn;
1925  void *callbackArg;
1927 
1936 typedef struct HWA_DoneInterruptCtx_t {
1937  bool bIsEnabled;
1938  HWA_Done_IntHandlerFuncPTR callbackFn;
1939  void *callbackArg;
1941 
1945 typedef struct HWA_Driver_t {
1949  uint32_t instanceNum;
1953  uint32_t refCnt;
1958  uint8_t configInProgress;
1964  uint16_t paramSetMapInProgress;
1968  HWA_Attrs const *hwAttrs;
1969 
1973  HwiP_Object hwiHandleParamSet;
1974 
1978  HwiP_Object hwiHandleDone;
1979 
1983  HwiP_Object hwiHandleParamSetALT;
1984 
1988  HwiP_Object hwiHandleDoneALT;
1989 
1993  HwiP_Object hwiHandleLocalRamErr;
1994 
1998  HWA_InterruptCtx *interruptCtxParamSet; /*[NUM_HWA_PARAMSETS_PER_INSTANCE];*/
1999 
2003  uint64_t interrupt1ParamSetMask;
2004 
2008  uint64_t interrupt2ParamSetMask;
2009 
2010 
2014  HWA_DoneInterruptCtx interruptCtxDone;
2015 
2019  HWA_DoneInterruptCtx interruptCtxDoneALT;
2020 
2021 #if defined (SOC_AWR294X)
2022 
2025  bool isES2P0Device;
2026 #endif
2027 } HWA_Object;
2028 
2030 extern HWA_Attrs gHwaAttrs[];
2034 extern HWA_Object gHwaObject[];
2036 extern HWA_Object *gHwaObjectPtr[];
2038 extern uint32_t gHwaConfigNum;
2039 
2040 /* ========================================================================== */
2041 /* Global Variables Declarations */
2042 /* ========================================================================== */
2043 
2044 /* None */
2045 
2046 /* ========================================================================== */
2047 /* Function Declarations */
2048 /* ========================================================================== */
2049 
2060 extern void HWA_init(void);
2061 
2065 extern void HWA_deinit(void);
2066 
2084 extern HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig * hwaCfg, int32_t* errCode);
2085 
2097 extern int32_t HWA_close(HWA_Handle handle);
2098 
2110 extern int32_t HWA_reset(HWA_Handle handle);
2111 
2133 extern int32_t HWA_initializeRAM(HWA_Handle handle, uint32_t ramMemBankMask);
2134 
2147 extern DSSHWACCRegs *HWA_getCommonCtrlAddr(HWA_Handle handle);
2148 
2163 extern DSSHWACCPARAMRegs *HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx);
2164 
2179 extern int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig);
2180 
2200 extern int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig);
2201 
2224 extern int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig);
2225 
2245 extern int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2246 
2256 extern uint32_t HWA_getRamAddress(uint8_t ramType);
2257 
2278 extern int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx);
2279 
2298 extern int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx);
2299 
2317 extern int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig);
2318 
2335 extern int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray);
2336 
2351 extern int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex);
2352 
2370 extern int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void * callbackArg);
2371 
2387 extern int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag);
2388 
2402 extern int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx);
2403 
2418 extern int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis);
2419 
2433 extern int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis);
2434 
2449 extern int32_t HWA_setSoftwareTrigger(HWA_Handle handle);
2450 
2463 extern int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle);
2464 
2478 extern int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle,uint8_t idx);
2479 
2493 extern int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype);
2494 
2506 extern int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle);
2507 
2519 extern int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle);
2520 
2534 extern int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx);
2535 
2551 extern int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress);
2552 
2578 extern int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type);
2579 
2592 extern int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type);
2593 
2612 extern int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter);
2613 
2631 extern int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size);
2632 
2647 extern int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats);
2648 
2660 extern int32_t HWA_clearDebugReg(HWA_Handle handle);
2661 
2676 extern int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo);
2677 
2695 extern int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan);
2696 
2712 extern int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan);
2713 
2733 extern int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size);
2734 
2755 extern int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size);
2756 
2775 extern int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size);
2776 
2790 extern int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp);
2791 
2805 extern int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame);
2806 
2826 extern int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type);
2827 
2840 extern int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis);
2841 
2854 extern int32_t HWA_configureSingleStep(HWA_Handle handle, uint8_t flagEnDis);
2855 
2867 extern int32_t HWA_triggerSingleStep(HWA_Handle handle);
2868  /* end of addgroup HWA_DRIVER_EXTERNAL_FUNCTION*/
2870 
2871 #ifdef __cplusplus
2872 }
2873 #endif
2874 
2875 #endif /* HWA_H_ */
2876 
2877 
HWA_CHANCOMB_LENGTH_INWORDS
#define HWA_CHANCOMB_LENGTH_INWORDS
The length of channel combining vector in words.
Definition: hwa/v0/hwa.h:179
HWA_SourceConfig
HWA Paramset Config for Input Formatter/Source block.
Definition: hwa/v0/hwa.h:1124
HWA_AccmulatorVal
HWA Accumulator register value data structure.
Definition: hwa/v0/hwa.h:1808
HWA_readInterfThreshReg
int32_t HWA_readInterfThreshReg(HWA_Handle handle, uint32_t *pbuf, uint8_t startIdx, uint8_t size, uint8_t type)
Function to read the interference statistics INTF_LOC_THRESH_MAG_VAL or INTF_LOC_THRESH_MAG_VAL regis...
HWA_enable
int32_t HWA_enable(HWA_Handle handle, uint8_t flagEnDis)
Function to enable the state machine of the HWA. This should be called after paramset and RAM have be...
HWA_disableDoneInterrupt
int32_t HWA_disableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx)
Function to disable the CPU interrupt after all programmed paramSets have been completed.
HWA_reset
int32_t HWA_reset(HWA_Handle handle)
Function to reset the internal state machine of the HWA.
HWA_AccelModeFFT
HWA Paramset Config for FFT block.
Definition: hwa/v0/hwa.h:1528
HWA_setDMA2ACCManualTrig
int32_t HWA_setDMA2ACCManualTrig(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine waiting on DMA via software.
HWA_configureSingleStep
int32_t HWA_configureSingleStep(HWA_Handle handle, uint8_t flagEnDis)
Function to enable/disable single-stepping approach which pauses the HWA execution after each param-s...
HWA_clearDebugReg
int32_t HWA_clearDebugReg(HWA_Handle handle)
Function to clear the debug registers (acc_trig_in_clr)
HWA_MemInfo
HWA Local memory Information.
Definition: hwa/v0/hwa.h:1850
gHwaConfigNum
uint32_t gHwaConfigNum
Externally defined driver configuration array size.
HWA_paramSetDonePolling
int32_t HWA_paramSetDonePolling(HWA_Handle handle, uint8_t numParamSets, uint8_t *paramsetsArray)
Function to poll the PARAM_DONE_SET_STATUS_0 and PARAM_DONE_SET_STATUS_1 registers to check if the sp...
HWA_open
HWA_Handle HWA_open(uint32_t index, HWA_OpenConfig *hwaCfg, int32_t *errCode)
Function to initialize HWA specified by the particular index value.
HWA_getDMAChanIndex
int32_t HWA_getDMAChanIndex(HWA_Handle handle, uint8_t edmaChanId, uint8_t *hwaDestChan)
Function to get the dma destination index with a given EDMA channel number This function assumes the ...
HWA_enableParamSetInterrupt
int32_t HWA_enableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, HWA_InterruptConfig *intrConfig)
Function to enable the CPU and/or DMA interrupt after a paramSet completion. The CPU interrupt for ev...
HWA_ComplexMultiply
HWA Paramset Config for ComplexMultiply block.
Definition: hwa/v0/hwa.h:1340
HWA_ParamDone_IntHandlerFuncPTR
void(* HWA_ParamDone_IntHandlerFuncPTR)(uint32_t intrIdx, uint32_t paramSet, void *arg)
HWA Interrupt callback function after every paramset completion.
Definition: hwa/v0/hwa.h:779
HWA_AccelModeCFAR
HWA Paramset Config for CFAR block.
Definition: hwa/v0/hwa.h:1600
HWA_init
void HWA_init(void)
Function to initialize the HWA module.
gHwaAttrs
HWA_Attrs gHwaAttrs[]
Externally defined driver configuration array.
HWA_CMP_K_ARR_LEN
#define HWA_CMP_K_ARR_LEN
The length of EGE compression/decompression K-paramseters array.
Definition: hwa/v0/hwa.h:187
HWA_OpenConfig
HWA configuration structure, which describes the configuration information, needed for hwa handle ope...
Definition: hwa/v0/hwa.h:1889
HWA_softwareResetTwidIncrDeltaFrac
int32_t HWA_softwareResetTwidIncrDeltaFrac(HWA_Handle handle)
Function resets the execution counter if complex multiply is configured as frequency shifter mode wit...
HWA_setContextswitchDMAManualTrigger
int32_t HWA_setContextswitchDMAManualTrigger(HWA_Handle handle, uint8_t idx)
Function to manually trigger the execution of the state machine via DMA trigger in context switch.
HWA_ZEROINSERT_LENGTH_INWORDS
#define HWA_ZEROINSERT_LENGTH_INWORDS
The length of zero insert mask in words.
Definition: hwa/v0/hwa.h:181
HWA_getDMAconfig
int32_t HWA_getDMAconfig(HWA_Handle handle, uint8_t dmaTriggerSrc, HWA_SrcDMAConfig *dmaConfig)
Function to get the config to program the DMA for a given DMA Trigger channel. Application should use...
HWA_DebugStats
HWA Debug statistics.
Definition: hwa/v0/hwa.h:1819
HWA_readInterfFrameCountReg
int32_t HWA_readInterfFrameCountReg(HWA_Handle handle, uint32_t *numInterfSamplesFrame)
Function to read the number of samples that exceeded the threshold in a frame.
HWA_close
int32_t HWA_close(HWA_Handle handle)
Function to close a HWA peripheral specified by the HWA handle.
HWA_readHistThresholdRam
int32_t HWA_readHistThresholdRam(HWA_Handle handle, HWA_CdfThreshold *cdfThresholdResult, uint8_t numSampleIndices, uint8_t startSampleIdx)
Function to read the HWA HWA_RAM_TYPE_HIST_THRESH_RAM RAM.
HWA_enableContextSwitch
int32_t HWA_enableContextSwitch(HWA_Handle handle, uint8_t flagEnDis)
Function to enable or disable the context switching in hwa.
HWA_readCFARPeakCountReg
int32_t HWA_readCFARPeakCountReg(HWA_Handle handle, uint8_t *pbuf, uint8_t size)
Function to read the PEAKCNT register.
HWA_getParamSetAddr
DSSHWACCPARAMRegs * HWA_getParamSetAddr(HWA_Handle handle, uint8_t paramsetIdx)
Function to returns the HWA paramSet base address.
HWA_readDCAccReg
int32_t HWA_readDCAccReg(HWA_Handle handle, cmplx64ImRe_t *accbuf, uint8_t startIdx, uint8_t size)
Function to read the DC estimation accumulator register,.
HWA_BPMPATTERN_LENGTH_INWORDS
#define HWA_BPMPATTERN_LENGTH_INWORDS
The length of BPM Pattern sequence in words.
Definition: hwa/v0/hwa.h:177
HWA_getEDMAChanId
int32_t HWA_getEDMAChanId(HWA_Handle handle, uint8_t hwaDMAdestChan)
Function to get the edma EDMA channel number from a given HWA paramset destination channel....
HWA_enableDoneInterrupt
int32_t HWA_enableDoneInterrupt(HWA_Handle handle, uint8_t threadIdx, HWA_Done_IntHandlerFuncPTR callbackFn, void *callbackArg)
Function to enable the CPU interrupt after all programmed paramSets have been completed in the backgr...
HWA_setContextswitchSoftwareTrigger
int32_t HWA_setContextswitchSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software in context switch,...
HWA_getCommonCtrlAddr
DSSHWACCRegs * HWA_getCommonCtrlAddr(HWA_Handle handle)
Function to returns the HWA common control base address.
gHwaRamCfg
HWA_RAMAttrs gHwaRamCfg[HWA_NUM_RAMS]
Externally defined driver RAM configuration array.
HWA_Done_IntHandlerFuncPTR
void(* HWA_Done_IntHandlerFuncPTR)(uint32_t threadIdx, void *arg)
HWA Interrupt callback function after all paramsets completion.
Definition: hwa/v0/hwa.h:787
HWA_PreProcessing
HWA Paramset Config for pre-processing block.
Definition: hwa/v0/hwa.h:1445
HWA_initializeRAM
int32_t HWA_initializeRAM(HWA_Handle handle, uint32_t ramMemBankMask)
Function to initialize RAM memory banks in HWA.
HWA_getRamAddress
uint32_t HWA_getRamAddress(uint8_t ramType)
Function to get the RAM starting address for one specified RAM type.
HWA_configCommon
int32_t HWA_configCommon(HWA_Handle handle, HWA_CommonConfig *commonConfig)
Function to set the common HWA configuration parameters needed for the next operations/iterations/par...
HwiP.h
HWA_NUM_RXCHANNELS
#define HWA_NUM_RXCHANNELS
Number of RX channels in pre-processing block.
Definition: hwa/v0/hwa.h:173
HWA_getHWAMemInfo
int32_t HWA_getHWAMemInfo(HWA_Handle handle, HWA_MemInfo *memInfo)
Function to get HWA processing Memory information including address, size and number of banks.
gHwaObject
HWA_Object gHwaObject[]
Externally defined driver object.
HWA_configRam
int32_t HWA_configRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to set the HWA RAM : HWA_RAM_TYPE_WINDOW_RAM, HWA_RAM_TYPE_VECTORMULTIPLY_RAM,...
HWA_AccelModeLocalMax
HWA Paramset Config for Local maxima block.
Definition: hwa/v0/hwa.h:1665
HWA_InterruptPriority
HWA interrupt priority for HWA background thread done, ALT thread done, paramset done interrupt 1 and...
Definition: hwa/v0/hwa.h:1875
HWA_readClipStatus
int32_t HWA_readClipStatus(HWA_Handle handle, uint16_t *clipStatusResult, uint8_t type)
Function to read the Clip Status registers.
HWA_configParamSet
int32_t HWA_configParamSet(HWA_Handle handle, uint8_t paramsetIdx, HWA_ParamConfig *paramConfig, HWA_SrcDMAConfig *dmaConfig)
Function to set the HWA configuration parameters for a given paramSet.
HWA_InterruptConfig
HWA Interrupt Config.
Definition: hwa/v0/hwa.h:1772
HWA_SrcDMAConfig
Source trigger DMA parameters.
Definition: hwa/v0/hwa.h:837
HWA_DoneInterruptCtx
HWA Interrupt context structure for done interrupt.
Definition: hwa/v0/hwa.h:1933
HWA_CommonConfig
HWA Common Config.
Definition: hwa/v0/hwa.h:851
HWA_disableParamSetInterrupt
int32_t HWA_disableParamSetInterrupt(HWA_Handle handle, uint8_t paramsetIdx, uint8_t interruptTypeFlag)
Function to disable the CPU and/or DMA interrupt after a paramSet completion.
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
HWA_ParamConfig
HWA Paramset Config.
Definition: hwa/v0/hwa.h:1738
HWA_readDCEstimateReg
int32_t HWA_readDCEstimateReg(HWA_Handle handle, cmplx32ImRe_t *pbuf, uint8_t startIdx, uint8_t size)
Function to read the DC_EST_I/Q register.
HWA_AccelModeCompress
HWA Paramset Config for compression and decompression.
Definition: hwa/v0/hwa.h:1690
HWA_singleParamSetDonePolling
int32_t HWA_singleParamSetDonePolling(HWA_Handle handle, uint8_t paramsetIndex)
Function to poll the PARAM_DONE_SET_STATUS_0 or PARAM_DONE_SET_STATUS_1 registers to check if one sin...
HWA_NUM_RAMS
#define HWA_NUM_RAMS
The number of RAM types in HWA.
Definition: hwa/v0/hwa.h:183
HWA_CdfThreshold
HWA Histogram Threshold RAM data structure.
Definition: hwa/v0/hwa.h:1862
HWA_softwareResetRecursiveWinKvalue
int32_t HWA_softwareResetRecursiveWinKvalue(HWA_Handle handle)
Function resets the paramset counter used in recurise windowing mode with REC_WIN_MODE_SEL is set to ...
HWA_NUM_INTERFMITG_WINARRAY
#define HWA_NUM_INTERFMITG_WINARRAY
Number of programmable array of window parameters in interference mitigation block.
Definition: hwa/v0/hwa.h:175
HWA_triggerSingleStep
int32_t HWA_triggerSingleStep(HWA_Handle handle)
Function to Trigger single-step. This triggers state machine to execute one parameter-set at a time a...
HWA_InterruptCtx
HWA Interrupt context structure for paramset done interrupt.
Definition: hwa/v0/hwa.h:1920
HWA_clearClipStatus
int32_t HWA_clearClipStatus(HWA_Handle handle, uint8_t type)
Function to clear the Clip Status registers.
HWA_setSoftwareTrigger
int32_t HWA_setSoftwareTrigger(HWA_Handle handle)
Function to manually trigger the execution of the state machine via software, the software trigger th...
HWA_RAMAttrs
HWA RAM Parameters.
Definition: hwa/v0/hwa.h:821
HWA_readDebugReg
int32_t HWA_readDebugReg(HWA_Handle handle, HWA_DebugStats *pStats)
Function to read the debug registers (paramcurr, loopcou, acc_trig_in_stat)
HWA_PostProcStat
HWA Paramset Config for post-processing and the statistics control registers.
Definition: hwa/v0/hwa.h:1299
HWA_DestConfig
HWA Paramset Config for Output Formatter/Destination block.
Definition: hwa/v0/hwa.h:1235
HWA_readRam
int32_t HWA_readRam(HWA_Handle handle, uint8_t ramType, uint8_t *data, uint32_t dataSize, uint32_t startIdx)
Function to read the HWA 2D statistics output RAM, including HWA_RAM_TYPE_2DSTAT_ITER_VAL,...
HWA_controlPeripheralSuspendMode
int32_t HWA_controlPeripheralSuspendMode(HWA_Handle handle, uint8_t flagEnDis)
Function to control the suspend mode of the peripheral when the controlling processor (where this dri...
HWA_readInterfChirpCountReg
int32_t HWA_readInterfChirpCountReg(HWA_Handle handle, uint16_t *numInterfSamplesChirp)
Function to read the number of samples that exceeded the threshold in a chirp.
HWA_Handle
void * HWA_Handle
A handle that is returned from a HWA_open() call.
Definition: hwa/v0/hwa.h:771
HWA_Stats
HWA Statistics from the STATISTICS block.
Definition: hwa/v0/hwa.h:1795
HWA_setSourceAddress
int32_t HWA_setSourceAddress(HWA_Handle handle, uint16_t paramIdx, uint32_t sourceAddress)
Function to set the source address for one paramset.
HWA_deinit
void HWA_deinit(void)
Function to deinitialize the HWA module.
HWA_readStatsReg
int32_t HWA_readStatsReg(HWA_Handle handle, HWA_Stats *pStats, uint8_t numIter)
Function to read the 4 sets of 'MAX' statistics register.
HWA_Object
HWA driver internal Config.
Definition: hwa/v0/hwa.h:1942
HWA_Attrs
HWA H/W Parameters.
Definition: hwa/v0/hwa.h:795
HWA_readIntfAccReg
int32_t HWA_readIntfAccReg(HWA_Handle handle, uint64_t *accBuf, uint8_t type, uint8_t startIdx, uint8_t size)
Function to read the interference threshold MAG or MAGDIFF Accumulator register.
gHwaObjectPtr
HWA_Object * gHwaObjectPtr[]
Externally defined driver object pointer.
HWA_softwareResetAccumulators
int32_t HWA_softwareResetAccumulators(HWA_Handle handle, uint8_t accumulatortype)
Function for sofware to reset the DC accumulators or interference statistics accumulators.