Macros
#define	CSL_EPWM_PER_CNT (3U)
	Number of ePWM instances. More...

#define	CSL_MSS_UART_PER_CNT (2U)
	Number of UART instances. More...

#define	CSL_DSS_UART_PER_CNT (1U)

#define	CSL_RCSS_UART_PER_CNT (1U)

#define	CSL_MSS_MIBSPI_PER_CNT (2U)
	Number of MIBSPI instances. More...

#define	CSL_RCSS_MIBSPI_PER_CNT (2U)

#define	CSL_MSS_I2C_CNT (1U)
	Number of I2C instances. More...

#define	CSL_RCSS_I2C_CNT (2U)

#define	CSL_MSS_I2C_PER_CNT (CSL_MSS_I2C_CNT + CSL_RCSS_I2C_CNT)

#define	CSL_DSS_I2C_PER_CNT (CSL_RCSS_I2C_CNT)

#define	SOC_DSP_L1P_BASE (CSL_DSP_L1P_U_BASE)

#define	SOC_DSP_L1D_BASE (CSL_DSP_L1D_U_BASE)

#define	SOC_DSP_L2_BASE (CSL_DSP_L2_U_BASE)

#define	SOC_DSP_ICFG_BASE (CSL_DSP_ICFG_U_BASE - 0x800000U)

#define	SOC_EDMA_NUM_DMACH (64U)
	Number of DMA Channels. More...

#define	SOC_EDMA_NUM_QDMACH (8U)
	Number of QDMA Channels. More...

#define	SOC_EDMA_NUM_PARAMSETS (256U)
	Number of PaRAM Sets available. More...

#define	SOC_EDMA_NUM_EVQUE (2U)
	Number of Event Queues available. More...

#define	SOC_EDMA_CHMAPEXIST (1U)
	Support for Channel to PaRAM Set mapping. More...

#define	SOC_EDMA_NUM_REGIONS (8U)
	Number of EDMA Regions. More...

#define	SOC_EDMA_MEMPROTECT (1U)
	Support for Memory Protection. More...

#define	MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)

#define	ESM_NUM_GROUP_MAX (3U)

#define	ESM_NUM_INTR_PER_GROUP (128U)

#define	EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ0 0
	DSP TPCC A EVENT MAP. More...

#define	EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ1 1

#define	EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ2 2

#define	EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ3 3

#define	EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ0 4

#define	EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ1 5

#define	EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ2 6

#define	EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ3 7

#define	EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ0 8

#define	EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ1 9

#define	EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ2 10

#define	EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ3 11

#define	EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ0 12

#define	EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ1 13

#define	EDMA_DSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 14

#define	EDMA_DSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 15

#define	EDMA_DSS_TPCC_A_EVT_FREE_0 16

#define	EDMA_DSS_TPCC_A_EVT_FREE_1 17

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ0 18

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ1 19

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ2 20

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ3 21

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ4 22

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ5 23

#define	EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ6 24

#define	EDMA_DSS_TPCC_A_EVT_FREE_2 25

#define	EDMA_DSS_TPCC_A_EVT_FREE_3 26

#define	EDMA_DSS_TPCC_A_EVT_FREE_4 27

#define	EDMA_DSS_TPCC_A_EVT_FREE_5 28

#define	EDMA_DSS_TPCC_A_EVT_FREE_6 29

#define	EDMA_DSS_TPCC_A_EVT_FREE_7 30

#define	EDMA_DSS_TPCC_A_EVT_FREE_8 31

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ0 32

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ1 33

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ2 34

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ3 35

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ4 36

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ5 37

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ6 38

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ7 39

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ8 40

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ9 41

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ10 42

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ11 43

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ12 44

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ13 45

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ14 46

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ15 47

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ16 48

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ17 49

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ18 50

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ19 51

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ20 52

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ21 53

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ22 54

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ23 55

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ24 56

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ25 57

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ26 58

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ27 59

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ28 60

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ29 61

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ30 62

#define	EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ31 63

#define	EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ0 0
	DSP TPCC B EVENT MAP. More...

#define	EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ1 1

#define	EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ2 2

#define	EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ3 3

#define	EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ0 4

#define	EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ1 5

#define	EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ2 6

#define	EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ3 7

#define	EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ0 8

#define	EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ1 9

#define	EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ2 10

#define	EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ3 11

#define	EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ0 12

#define	EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ1 13

#define	EDMA_DSS_TPCC_B_EVT_SCIA_RX_DMA_REQ 14

#define	EDMA_DSS_TPCC_B_EVT_SCIA_TX_DMA_REQ 15

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOF_INT 16

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_INT 17

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ0 18

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ1 19

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ2 20

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ3 21

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ4 22

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ5 23

#define	EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ6 24

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT0 25

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT1 26

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX0 27

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX1 28

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX2 29

#define	EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX3 30

#define	EDMA_DSS_TPCC_B_EVT_FREE_0 31

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ0 32

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ1 33

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ2 34

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ3 35

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ4 36

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ5 37

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ6 38

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ7 39

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ8 40

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ9 41

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ10 42

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ11 43

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ12 44

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ13 45

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ14 46

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ15 47

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ16 48

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ17 49

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ18 50

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ19 51

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ20 52

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ21 53

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ22 54

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ23 55

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ24 56

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ25 57

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ26 58

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ27 59

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ28 60

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ29 61

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ30 62

#define	EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ31 63

#define	EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ0 0
	DSP TPCC C EVENT MAP. More...

#define	EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ1 1

#define	EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ2 2

#define	EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ3 3

#define	EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ0 4

#define	EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ1 5

#define	EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ2 6

#define	EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ3 7

#define	EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ0 8

#define	EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ1 9

#define	EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ2 10

#define	EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ3 11

#define	EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ0 12

#define	EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ1 13

#define	EDMA_DSS_TPCC_C_EVT_SCIA_RX_DMA_REQ 14

#define	EDMA_DSS_TPCC_C_EVT_SCIA_TX_DMA_REQ 15

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOF_INT 16

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_INT 17

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ0 18

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ1 19

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ2 20

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ3 21

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ4 22

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ5 23

#define	EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ6 24

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT0 25

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT1 26

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX0 27

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX1 28

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX2 29

#define	EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX3 30

#define	EDMA_DSS_TPCC_C_EVT_FREE_0 31

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ0 32

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ1 33

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ2 34

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ3 35

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ4 36

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ5 37

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ6 38

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ7 39

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ8 40

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ9 41

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ10 42

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ11 43

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ12 44

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ13 45

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ14 46

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ15 47

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ16 48

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ17 49

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ18 50

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ19 51

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ20 52

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ21 53

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ22 54

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ23 55

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ24 56

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ25 57

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ26 58

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ27 59

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ28 60

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ29 61

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ30 62

#define	EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ31 63

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ0 0
	MSS TPCC A EVENT MAP. More...

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ1 1

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ2 2

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ3 3

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ4 4

#define	EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ5 5

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ0 6

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ1 7

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ2 8

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ3 9

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ4 10

#define	EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ5 11

#define	EDMA_MSS_TPCC_A_EVT_QSPI_DMA_REQ0 12

#define	EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ0 13

#define	EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ1 14

#define	EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ0 15

#define	EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ1 16

#define	EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ2 17

#define	EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ3 18

#define	EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ0 19

#define	EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ1 20

#define	EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ0 21

#define	EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ1 22

#define	EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ0 23

#define	EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ1 24

#define	EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ2 25

#define	EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ3 26

#define	EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ0 27

#define	EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ1 28

#define	EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ0 29

#define	EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ1 30

#define	EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ0 31

#define	EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ1 32

#define	EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ0 33

#define	EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ1 34

#define	EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT1 35

#define	EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT2 36

#define	EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT4 37

#define	EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ0 38

#define	EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ1 39

#define	EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT1 40

#define	EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT2 41

#define	EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT4 42

#define	EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ2 43

#define	EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ3 44

#define	EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ2 45

#define	EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ3 46

#define	EDMA_MSS_TPCC_A_EVT_FREE_0 47

#define	EDMA_MSS_TPCC_A_EVT_FREE_1 48

#define	EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT0 49

#define	EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT1 50

#define	EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT2 51

#define	EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT3 52

#define	EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT4 53

#define	EDMA_MSS_TPCC_A_EVT_FREE_2 54

#define	EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ0 55

#define	EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ1 56

#define	EDMA_MSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 57

#define	EDMA_MSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 58

#define	EDMA_MSS_TPCC_A_EVT_SCIB_RX_DMA_REQ 59

#define	EDMA_MSS_TPCC_A_EVT_SCIB_TX_DMA_REQ 60

#define	EDMA_MSS_TPCC_A_EVT_FREE_3 61

#define	EDMA_MSS_TPCC_A_EVT_FREE_4 62

#define	EDMA_MSS_TPCC_A_EVT_CBUFF_DMA_REQ 63

#define	EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ0 0
	MSS TPCC B EVENT MAP. More...

#define	EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ1 1

#define	EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ0 2

#define	EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ1 3

#define	EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ0 4

#define	EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ1 5

#define	EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ0 6

#define	EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ1 7

#define	EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ0 8

#define	EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ1 9

#define	EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ0 10

#define	EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ1 11

#define	EDMA_MSS_TPCC_B_EVT_FREE_0 12

#define	EDMA_MSS_TPCC_B_EVT_FREE_1 13

#define	EDMA_MSS_TPCC_B_EVT_FREE_2 14

#define	EDMA_MSS_TPCC_B_EVT_FREE_3 15

#define	EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT0 16

#define	EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT1 17

#define	EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT2 18

#define	EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT3 19

#define	EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT4 20

#define	EDMA_MSS_TPCC_B_EVT_FREE_4 21

#define	EDMA_MSS_TPCC_B_EVT_FREE_5 22

#define	EDMA_MSS_TPCC_B_EVT_FREE_6 23

#define	EDMA_MSS_TPCC_B_EVT_FREE_7 24

#define	EDMA_MSS_TPCC_B_EVT_FREE_8 25

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ0 26

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ1 27

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ2 28

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ3 29

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ4 30

#define	EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ5 31

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ0 32

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ1 33

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ2 34

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ3 35

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ4 36

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ5 37

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ6 38

#define	EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ7 39

#define	EDMA_MSS_TPCC_B_EVT_FREE_9 40

#define	EDMA_MSS_TPCC_B_EVT_FREE_10 41

#define	EDMA_MSS_TPCC_B_EVT_FREE_11 42

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT1 43

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT2 44

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT3 45

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT4 46

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT5 47

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT6 48

#define	EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT7 49

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT1 50

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT2 51

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT3 52

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT4 53

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT5 54

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT6 55

#define	EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT7 56

#define	EDMA_MSS_TPCC_B_EVT_FREE_12 57

#define	EDMA_MSS_TPCC_B_EVT_FREE_13 58

#define	EDMA_MSS_TPCC_B_EVT_FREE_14 59

#define	EDMA_MSS_TPCC_B_EVT_FREE_15 60

#define	EDMA_MSS_TPCC_B_EVT_FREE_16 61

#define	EDMA_MSS_TPCC_B_EVT_FREE_17 62

#define	EDMA_MSS_TPCC_B_EVT_FREE_18 63

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ0 0
	RCSS TPCC A EVENT MAP. More...

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ1 1

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ2 2

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ3 3

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ4 4

#define	EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ5 5

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ0 6

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ1 7

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ2 8

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ3 9

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ4 10

#define	EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ5 11

#define	EDMA_RCSS_TPCC_A_EVT_ECAP_DMA_REQ 12

#define	EDMA_RCSS_TPCC_A_EVT_FREE_0 13

#define	EDMA_RCSS_TPCC_A_EVT_FREE_1 14

#define	EDMA_RCSS_TPCC_A_EVT_FREE_2 15

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOF_INT 16

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_INT 17

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX0_INT 18

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX1_INT 19

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX2_INT 20

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX3_INT 21

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX4_INT 22

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX5_INT 23

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX6_INT 24

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX7_INT 25

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG0_INT 26

#define	EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG1_INT 27

#define	EDMA_RCSS_TPCC_A_EVT_FREE_3 28

#define	EDMA_RCSS_TPCC_A_EVT_FREE_4 29

#define	EDMA_RCSS_TPCC_A_EVT_FREE_5 30

#define	EDMA_RCSS_TPCC_A_EVT_FREE_6 31

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOF_INT 32

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_INT 33

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX0_INT 34

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX1_INT 35

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX2_INT 36

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX3_INT 37

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX4_INT 38

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX5_INT 39

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX6_INT 40

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX7_INT 41

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG0_INT 42

#define	EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG1_INT 43

#define	EDMA_RCSS_TPCC_A_EVT_SCIA_TX_SINGLE_REQ 44

#define	EDMA_RCSS_TPCC_A_EVT_SCIA_TX_BURST_REQ 45

#define	EDMA_RCSS_TPCC_A_EVT_FREE_7 46

#define	EDMA_RCSS_TPCC_A_EVT_FREE_8 47

#define	EDMA_RCSS_TPCC_A_EVT_MCASPA_TX_REQ 48

#define	EDMA_RCSS_TPCC_A_EVT_MCASPB_TX_REQ 49

#define	EDMA_RCSS_TPCC_A_EVT_MCASPC_TX_REQ 50

#define	EDMA_RCSS_TPCC_A_EVT_MCASPA_RX_REQ 51

#define	EDMA_RCSS_TPCC_A_EVT_MCASPB_RX_REQ 52

#define	EDMA_RCSS_TPCC_A_EVT_MCASPC_RX_REQ 53

#define	EDMA_RCSS_TPCC_A_EVT_I2CA_TX_DMA_REQ 54

#define	EDMA_RCSS_TPCC_A_EVT_I2CA_RX_DMA_REQ 55

#define	EDMA_RCSS_TPCC_A_EVT_I2CB_TX_DMA_REQ 56

#define	EDMA_RCSS_TPCC_A_EVT_I2CB_RX_DMA_REQ 57

#define	EDMA_RCSS_TPCC_A_EVT_SCIA_RX_SINGLE_REQ 58

#define	EDMA_RCSS_TPCC_A_EVT_SCIA_RX_BURST_REQ 59

#define	EDMA_RCSS_TPCC_A_EVT_FREE_9 60

#define	EDMA_RCSS_TPCC_A_EVT_FREE_10 61

#define	EDMA_RCSS_TPCC_A_EVT_FREE_11 62

#define	EDMA_RCSS_TPCC_A_EVT_FREE_12 63

#define	EDMA_DSS_TPCC_A_NUM_PARAM_SETS (128U)

#define	EDMA_DSS_TPCC_A_NUM_DMA_CHANS (64U)

#define	EDMA_DSS_TPCC_A_NUM_TC (2U)

#define	EDMA_DSS_TPCC_B_NUM_PARAM_SETS (128U)

#define	EDMA_DSS_TPCC_B_NUM_DMA_CHANS (64U)

#define	EDMA_DSS_TPCC_B_NUM_TC (2U)

#define	EDMA_DSS_TPCC_C_NUM_PARAM_SETS (256U)

#define	EDMA_DSS_TPCC_C_NUM_DMA_CHANS (64U)

#define	EDMA_DSS_TPCC_C_NUM_TC (2U)

#define	EDMA_RCSS_TPCC_A_NUM_PARAM_SETS (128U)

#define	EDMA_RDSS_TPCC_A_NUM_DMA_CHANS (64U)

#define	EDMA_RCSS_TPCC_A_NUM_TC (2U)

#define	EDMA_MSS_TPCC_A_NUM_PARAM_SETS (128U)

#define	EDMA_MSS_TPCC_A_NUM_DMA_CHANS (64U)

#define	EDMA_MSS_TPCC_A_NUM_TC (2U)

#define	EDMA_MSS_TPCC_B_NUM_PARAM_SETS (128U)

#define	EDMA_MSS_TPCC_B_NUM_DMA_CHANS (64U)

#define	EDMA_MSS_TPCC_B_NUM_TC (1U)

#define	EDMA_HSM_TPCC_A_NUM_PARAM_SETS (128U)

#define	EDMA_HSM_TPCC_A_NUM_TC (2U)

#define	EDMA_TPCC_ERRAGG_TPCC_EERINT__POS (0U)

#define	EDMA_TPCC_INTAGG_TPCC_INTG__POS (0U)

#define	EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS (2U) /* position of the lowest TC Id, others are higher */

#define	EDMA_DSS_NUM_CC 4

#define	EDMA_DSS_MAX_NUM_TC

#define	EDMA_MSS_NUM_CC 6

#define	EDMA_MSS_MAX_NUM_TC

#define	HWA_NUM_INSTANCES (1U)

#define	SOC_HWA_NUM_MEM_BANKS (8U)
	number of HWA memory banks More...

#define	SOC_HWA_NUM_PARAM_SETS (64U)
	number of HWA parameter sets More...

#define	SOC_HWA_NUM_DMA_CHANNEL (32U)
	number of HWA MDA channels More...

#define	SOC_HWA_NUM_CSIRX_IRQS (20U)
	number of csirx IRQs More...

#define	SOC_HWA_MEM_SIZE (CSL_DSS_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)
	number of HWA memory size in bytes More...

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END (0U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END (1U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END (2U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END (3U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END (4U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END (5U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END (6U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END (7U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0 (8U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1 (9U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END (10U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END (11U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END (12U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END (13U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END (14U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END (15U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END (16U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END (17U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0 (18U)

#define	HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1 (19U)

#define	MSS_SYS_VCLK 200000000U

#define	R5F_CLOCK_MHZ 400U

Core ID's of core or CPUs present on this SOC

#define	CSL_CORE_ID_R5FSS0_0 (0U)

#define	CSL_CORE_ID_R5FSS0_1 (1U)

#define	CSL_CORE_ID_C66SS0 (2U)

#define	CSL_CORE_ID_MAX (3U)

Priv ID's of core or CPUs present on this SOC

#define	PRIV_ID_HSMM4 (1U)

#define	PRIV_ID_R5FSS (2U)

#define	PRIV_ID_R5FSSI (3U)

#define	PRIV_ID_DSSTPTC (5U)

R5 Cluster Group IDs

#define	CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
	R5 Cluster Group ID0. More...

R5 Core IDs

#define	CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
	R5 Core ID0. More...

#define	CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
	R5 Core ID1. More...

Macro Definition Documentation

◆ CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0 (0U)

◆ CSL_CORE_ID_R5FSS0_1

#define CSL_CORE_ID_R5FSS0_1 (1U)

◆ CSL_CORE_ID_C66SS0

#define CSL_CORE_ID_C66SS0 (2U)

◆ CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX (3U)

◆ PRIV_ID_HSMM4

#define PRIV_ID_HSMM4 (1U)

◆ PRIV_ID_R5FSS

#define PRIV_ID_R5FSS (2U)

◆ PRIV_ID_R5FSSI

#define PRIV_ID_R5FSSI (3U)

◆ PRIV_ID_DSSTPTC

#define PRIV_ID_DSSTPTC (5U)

◆ CSL_EPWM_PER_CNT

#define CSL_EPWM_PER_CNT (3U)

Number of ePWM instances.

◆ CSL_MSS_UART_PER_CNT

#define CSL_MSS_UART_PER_CNT (2U)

Number of UART instances.

◆ CSL_DSS_UART_PER_CNT

#define CSL_DSS_UART_PER_CNT (1U)

◆ CSL_RCSS_UART_PER_CNT

#define CSL_RCSS_UART_PER_CNT (1U)

◆ CSL_MSS_MIBSPI_PER_CNT

#define CSL_MSS_MIBSPI_PER_CNT (2U)

Number of MIBSPI instances.

◆ CSL_RCSS_MIBSPI_PER_CNT

#define CSL_RCSS_MIBSPI_PER_CNT (2U)

◆ CSL_MSS_I2C_CNT

#define CSL_MSS_I2C_CNT (1U)

Number of I2C instances.

◆ CSL_RCSS_I2C_CNT

#define CSL_RCSS_I2C_CNT (2U)

◆ CSL_MSS_I2C_PER_CNT

#define CSL_MSS_I2C_PER_CNT (CSL_MSS_I2C_CNT + CSL_RCSS_I2C_CNT)

◆ CSL_DSS_I2C_PER_CNT

#define CSL_DSS_I2C_PER_CNT (CSL_RCSS_I2C_CNT)

◆ SOC_DSP_L1P_BASE

#define SOC_DSP_L1P_BASE (CSL_DSP_L1P_U_BASE)

◆ SOC_DSP_L1D_BASE

#define SOC_DSP_L1D_BASE (CSL_DSP_L1D_U_BASE)

◆ SOC_DSP_L2_BASE

#define SOC_DSP_L2_BASE (CSL_DSP_L2_U_BASE)

◆ SOC_DSP_ICFG_BASE

#define SOC_DSP_ICFG_BASE (CSL_DSP_ICFG_U_BASE - 0x800000U)

◆ SOC_EDMA_NUM_DMACH

#define SOC_EDMA_NUM_DMACH (64U)

Number of DMA Channels.

◆ SOC_EDMA_NUM_QDMACH

#define SOC_EDMA_NUM_QDMACH (8U)

Number of QDMA Channels.

◆ SOC_EDMA_NUM_PARAMSETS

#define SOC_EDMA_NUM_PARAMSETS (256U)

Number of PaRAM Sets available.

◆ SOC_EDMA_NUM_EVQUE

#define SOC_EDMA_NUM_EVQUE (2U)

Number of Event Queues available.

◆ SOC_EDMA_CHMAPEXIST

#define SOC_EDMA_CHMAPEXIST (1U)

Support for Channel to PaRAM Set mapping.

◆ SOC_EDMA_NUM_REGIONS

#define SOC_EDMA_NUM_REGIONS (8U)

Number of EDMA Regions.

◆ SOC_EDMA_MEMPROTECT

#define SOC_EDMA_MEMPROTECT (1U)

Support for Memory Protection.

◆ MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)

◆ ESM_NUM_GROUP_MAX

#define ESM_NUM_GROUP_MAX (3U)

◆ ESM_NUM_INTR_PER_GROUP

#define ESM_NUM_INTR_PER_GROUP (128U)

◆ EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ0 0

DSP TPCC A EVENT MAP.

◆ EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ1 1

◆ EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ2 2

◆ EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_RTIA_DMA_REQ3 3

◆ EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ0 4

◆ EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ1 5

◆ EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ2 6

◆ EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_RTIB_DMA_REQ3 7

◆ EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ0 8

◆ EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ1 9

◆ EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ2 10

◆ EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_WDT_DMA_REQ3 11

◆ EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ0 12

◆ EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_MCRC_DMA_REQ1 13

◆ EDMA_DSS_TPCC_A_EVT_SCIA_RX_DMA_REQ

#define EDMA_DSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 14

◆ EDMA_DSS_TPCC_A_EVT_SCIA_TX_DMA_REQ

#define EDMA_DSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 15

◆ EDMA_DSS_TPCC_A_EVT_FREE_0

#define EDMA_DSS_TPCC_A_EVT_FREE_0 16

◆ EDMA_DSS_TPCC_A_EVT_FREE_1

#define EDMA_DSS_TPCC_A_EVT_FREE_1 17

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ0 18

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ1 19

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ2 20

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ3 21

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ4

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ4 22

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ5

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ5 23

◆ EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ6

#define EDMA_DSS_TPCC_A_EVT_CBUFF_DMA_REQ6 24

◆ EDMA_DSS_TPCC_A_EVT_FREE_2

#define EDMA_DSS_TPCC_A_EVT_FREE_2 25

◆ EDMA_DSS_TPCC_A_EVT_FREE_3

#define EDMA_DSS_TPCC_A_EVT_FREE_3 26

◆ EDMA_DSS_TPCC_A_EVT_FREE_4

#define EDMA_DSS_TPCC_A_EVT_FREE_4 27

◆ EDMA_DSS_TPCC_A_EVT_FREE_5

#define EDMA_DSS_TPCC_A_EVT_FREE_5 28

◆ EDMA_DSS_TPCC_A_EVT_FREE_6

#define EDMA_DSS_TPCC_A_EVT_FREE_6 29

◆ EDMA_DSS_TPCC_A_EVT_FREE_7

#define EDMA_DSS_TPCC_A_EVT_FREE_7 30

◆ EDMA_DSS_TPCC_A_EVT_FREE_8

#define EDMA_DSS_TPCC_A_EVT_FREE_8 31

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ0

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ0 32

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ1

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ1 33

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ2

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ2 34

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ3

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ3 35

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ4

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ4 36

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ5

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ5 37

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ6

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ6 38

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ7

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ7 39

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ8

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ8 40

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ9

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ9 41

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ10

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ10 42

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ11

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ11 43

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ12

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ12 44

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ13

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ13 45

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ14

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ14 46

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ15

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ15 47

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ16

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ16 48

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ17

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ17 49

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ18

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ18 50

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ19

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ19 51

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ20

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ20 52

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ21

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ21 53

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ22

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ22 54

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ23

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ23 55

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ24

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ24 56

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ25

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ25 57

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ26

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ26 58

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ27

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ27 59

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ28

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ28 60

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ29

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ29 61

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ30

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ30 62

◆ EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ31

#define EDMA_DSS_TPCC_A_EVT_HWA_DMA_REQ31 63

◆ EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ0 0

DSP TPCC B EVENT MAP.

◆ EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ1 1

◆ EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ2 2

◆ EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_RTIA_DMA_REQ3 3

◆ EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ0 4

◆ EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ1 5

◆ EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ2 6

◆ EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_RTIB_DMA_REQ3 7

◆ EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ0 8

◆ EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ1 9

◆ EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ2 10

◆ EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_WDT_DMA_REQ3 11

◆ EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ0 12

◆ EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_MCRC_DMA_REQ1 13

◆ EDMA_DSS_TPCC_B_EVT_SCIA_RX_DMA_REQ

#define EDMA_DSS_TPCC_B_EVT_SCIA_RX_DMA_REQ 14

◆ EDMA_DSS_TPCC_B_EVT_SCIA_TX_DMA_REQ

#define EDMA_DSS_TPCC_B_EVT_SCIA_TX_DMA_REQ 15

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOF_INT

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOF_INT 16

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_INT

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_INT 17

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ0 18

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ1 19

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ2 20

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ3 21

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ4

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ4 22

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ5

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ5 23

◆ EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ6

#define EDMA_DSS_TPCC_B_EVT_CBUFF_DMA_REQ6 24

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT0

#define EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT0 25

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT1

#define EDMA_DSS_TPCC_B_EVT_CSI2A_SOF_INT1 26

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX0

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX0 27

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX1

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX1 28

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX2

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX2 29

◆ EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX3

#define EDMA_DSS_TPCC_B_EVT_CSI2A_EOL_CNTX3 30

◆ EDMA_DSS_TPCC_B_EVT_FREE_0

#define EDMA_DSS_TPCC_B_EVT_FREE_0 31

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ0

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ0 32

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ1

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ1 33

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ2

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ2 34

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ3

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ3 35

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ4

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ4 36

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ5

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ5 37

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ6

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ6 38

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ7

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ7 39

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ8

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ8 40

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ9

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ9 41

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ10

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ10 42

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ11

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ11 43

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ12

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ12 44

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ13

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ13 45

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ14

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ14 46

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ15

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ15 47

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ16

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ16 48

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ17

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ17 49

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ18

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ18 50

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ19

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ19 51

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ20

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ20 52

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ21

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ21 53

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ22

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ22 54

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ23

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ23 55

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ24

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ24 56

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ25

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ25 57

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ26

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ26 58

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ27

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ27 59

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ28

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ28 60

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ29

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ29 61

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ30

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ30 62

◆ EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ31

#define EDMA_DSS_TPCC_B_EVT_HWA_DMA_REQ31 63

◆ EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ0 0

DSP TPCC C EVENT MAP.

◆ EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ1 1

◆ EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ2

#define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ2 2

◆ EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ3

#define EDMA_DSS_TPCC_C_EVT_RTIA_DMA_REQ3 3

◆ EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ0 4

◆ EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ1 5

◆ EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ2

#define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ2 6

◆ EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ3

#define EDMA_DSS_TPCC_C_EVT_RTIB_DMA_REQ3 7

◆ EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ0 8

◆ EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ1 9

◆ EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ2

#define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ2 10

◆ EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ3

#define EDMA_DSS_TPCC_C_EVT_WDT_DMA_REQ3 11

◆ EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ0 12

◆ EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_MCRC_DMA_REQ1 13

◆ EDMA_DSS_TPCC_C_EVT_SCIA_RX_DMA_REQ

#define EDMA_DSS_TPCC_C_EVT_SCIA_RX_DMA_REQ 14

◆ EDMA_DSS_TPCC_C_EVT_SCIA_TX_DMA_REQ

#define EDMA_DSS_TPCC_C_EVT_SCIA_TX_DMA_REQ 15

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOF_INT

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOF_INT 16

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_INT

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_INT 17

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ0 18

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ1 19

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ2

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ2 20

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ3

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ3 21

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ4

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ4 22

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ5

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ5 23

◆ EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ6

#define EDMA_DSS_TPCC_C_EVT_CBUFF_DMA_REQ6 24

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT0

#define EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT0 25

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT1

#define EDMA_DSS_TPCC_C_EVT_CSI2B_SOF_INT1 26

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX0

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX0 27

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX1

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX1 28

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX2

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX2 29

◆ EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX3

#define EDMA_DSS_TPCC_C_EVT_CSI2B_EOL_CNTX3 30

◆ EDMA_DSS_TPCC_C_EVT_FREE_0

#define EDMA_DSS_TPCC_C_EVT_FREE_0 31

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ0

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ0 32

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ1

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ1 33

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ2

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ2 34

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ3

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ3 35

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ4

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ4 36

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ5

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ5 37

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ6

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ6 38

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ7

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ7 39

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ8

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ8 40

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ9

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ9 41

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ10

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ10 42

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ11

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ11 43

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ12

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ12 44

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ13

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ13 45

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ14

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ14 46

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ15

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ15 47

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ16

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ16 48

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ17

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ17 49

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ18

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ18 50

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ19

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ19 51

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ20

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ20 52

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ21

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ21 53

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ22

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ22 54

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ23

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ23 55

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ24

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ24 56

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ25

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ25 57

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ26

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ26 58

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ27

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ27 59

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ28

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ28 60

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ29

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ29 61

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ30

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ30 62

◆ EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ31

#define EDMA_DSS_TPCC_C_EVT_HWA_DMA_REQ31 63

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ0 0

MSS TPCC A EVENT MAP.

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ1 1

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ2 2

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ3 3

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ4

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ4 4

◆ EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ5

#define EDMA_MSS_TPCC_A_EVT_SPIA_DMA_REQ5 5

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ0 6

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ1 7

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ2 8

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ3 9

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ4

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ4 10

◆ EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ5

#define EDMA_MSS_TPCC_A_EVT_SPIB_DMA_REQ5 11

◆ EDMA_MSS_TPCC_A_EVT_QSPI_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_QSPI_DMA_REQ0 12

◆ EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ0 13

◆ EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_MCRC_DMA_REQ1 14

◆ EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ0 15

◆ EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ1 16

◆ EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ2 17

◆ EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_RTIA_DMA_REQ3 18

◆ EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ0 19

◆ EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ1 20

◆ EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ0 21

◆ EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ1 22

◆ EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ0 23

◆ EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ1 24

◆ EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ2 25

◆ EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_WDT_DMA_REQ3 26

◆ EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ0 27

◆ EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_ETPWMA_DMA_REQ1 28

◆ EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ0 29

◆ EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_ETPWMB_DMA_REQ1 30

◆ EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ0 31

◆ EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_ETPWMC_DMA_REQ1 32

◆ EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ0 33

◆ EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_MCANA_DMA_REQ1 34

◆ EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT1

#define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT1 35

◆ EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT2

#define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT2 36

◆ EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT4

#define EDMA_MSS_TPCC_A_EVT_MCANA_FE_INT4 37

◆ EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ0 38

◆ EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_MCANB_DMA_REQ1 39

◆ EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT1

#define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT1 40

◆ EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT2

#define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT2 41

◆ EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT4

#define EDMA_MSS_TPCC_A_EVT_MCANB_FE_INT4 42

◆ EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ2 43

◆ EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_RTIB_DMA_REQ3 44

◆ EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ2

#define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ2 45

◆ EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ3

#define EDMA_MSS_TPCC_A_EVT_RTIC_DMA_REQ3 46

◆ EDMA_MSS_TPCC_A_EVT_FREE_0

#define EDMA_MSS_TPCC_A_EVT_FREE_0 47

◆ EDMA_MSS_TPCC_A_EVT_FREE_1

#define EDMA_MSS_TPCC_A_EVT_FREE_1 48

◆ EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT0

#define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT0 49

◆ EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT1

#define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT1 50

◆ EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT2

#define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT2 51

◆ EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT3

#define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT3 52

◆ EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT4

#define EDMA_MSS_TPCC_A_EVT_GIO_PAD_INT4 53

◆ EDMA_MSS_TPCC_A_EVT_FREE_2

#define EDMA_MSS_TPCC_A_EVT_FREE_2 54

◆ EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ0

#define EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ0 55

◆ EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ1

#define EDMA_MSS_TPCC_A_EVT_I2C_DMA_REQ1 56

◆ EDMA_MSS_TPCC_A_EVT_SCIA_RX_DMA_REQ

#define EDMA_MSS_TPCC_A_EVT_SCIA_RX_DMA_REQ 57

◆ EDMA_MSS_TPCC_A_EVT_SCIA_TX_DMA_REQ

#define EDMA_MSS_TPCC_A_EVT_SCIA_TX_DMA_REQ 58

◆ EDMA_MSS_TPCC_A_EVT_SCIB_RX_DMA_REQ

#define EDMA_MSS_TPCC_A_EVT_SCIB_RX_DMA_REQ 59

◆ EDMA_MSS_TPCC_A_EVT_SCIB_TX_DMA_REQ

#define EDMA_MSS_TPCC_A_EVT_SCIB_TX_DMA_REQ 60

◆ EDMA_MSS_TPCC_A_EVT_FREE_3

#define EDMA_MSS_TPCC_A_EVT_FREE_3 61

◆ EDMA_MSS_TPCC_A_EVT_FREE_4

#define EDMA_MSS_TPCC_A_EVT_FREE_4 62

◆ EDMA_MSS_TPCC_A_EVT_CBUFF_DMA_REQ

#define EDMA_MSS_TPCC_A_EVT_CBUFF_DMA_REQ 63

◆ EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ0 0

MSS TPCC B EVENT MAP.

◆ EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_MCRC_DMA_REQ1 1

◆ EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ0 2

◆ EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_ETPWMA_DMA_REQ1 3

◆ EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ0 4

◆ EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_ETPWMB_DMA_REQ1 5

◆ EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ0 6

◆ EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_ETPWMC_DMA_REQ1 7

◆ EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ0 8

◆ EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_MCANA_DMA_REQ1 9

◆ EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ0 10

◆ EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_MCANB_DMA_REQ1 11

◆ EDMA_MSS_TPCC_B_EVT_FREE_0

#define EDMA_MSS_TPCC_B_EVT_FREE_0 12

◆ EDMA_MSS_TPCC_B_EVT_FREE_1

#define EDMA_MSS_TPCC_B_EVT_FREE_1 13

◆ EDMA_MSS_TPCC_B_EVT_FREE_2

#define EDMA_MSS_TPCC_B_EVT_FREE_2 14

◆ EDMA_MSS_TPCC_B_EVT_FREE_3

#define EDMA_MSS_TPCC_B_EVT_FREE_3 15

◆ EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT0

#define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT0 16

◆ EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT1

#define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT1 17

◆ EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT2

#define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT2 18

◆ EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT3

#define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT3 19

◆ EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT4

#define EDMA_MSS_TPCC_B_EVT_GIO_PAD_INT4 20

◆ EDMA_MSS_TPCC_B_EVT_FREE_4

#define EDMA_MSS_TPCC_B_EVT_FREE_4 21

◆ EDMA_MSS_TPCC_B_EVT_FREE_5

#define EDMA_MSS_TPCC_B_EVT_FREE_5 22

◆ EDMA_MSS_TPCC_B_EVT_FREE_6

#define EDMA_MSS_TPCC_B_EVT_FREE_6 23

◆ EDMA_MSS_TPCC_B_EVT_FREE_7

#define EDMA_MSS_TPCC_B_EVT_FREE_7 24

◆ EDMA_MSS_TPCC_B_EVT_FREE_8

#define EDMA_MSS_TPCC_B_EVT_FREE_8 25

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ0 26

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ1 27

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ2

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ2 28

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ3

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ3 29

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ4

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ4 30

◆ EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ5

#define EDMA_MSS_TPCC_B_EVT_DTHE_SHA_DMA_REQ5 31

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ0

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ0 32

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ1

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ1 33

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ2

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ2 34

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ3

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ3 35

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ4

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ4 36

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ5

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ5 37

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ6

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ6 38

◆ EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ7

#define EDMA_MSS_TPCC_B_EVT_DTHE_AES_DMA_REQ7 39

◆ EDMA_MSS_TPCC_B_EVT_FREE_9

#define EDMA_MSS_TPCC_B_EVT_FREE_9 40

◆ EDMA_MSS_TPCC_B_EVT_FREE_10

#define EDMA_MSS_TPCC_B_EVT_FREE_10 41

◆ EDMA_MSS_TPCC_B_EVT_FREE_11

#define EDMA_MSS_TPCC_B_EVT_FREE_11 42

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT1

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT1 43

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT2

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT2 44

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT3

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT3 45

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT4

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT4 46

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT5

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT5 47

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT6

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT6 48

◆ EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT7

#define EDMA_MSS_TPCC_B_EVT_MCANA_FE_INT7 49

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT1

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT1 50

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT2

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT2 51

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT3

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT3 52

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT4

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT4 53

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT5

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT5 54

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT6

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT6 55

◆ EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT7

#define EDMA_MSS_TPCC_B_EVT_MCANB_FE_INT7 56

◆ EDMA_MSS_TPCC_B_EVT_FREE_12

#define EDMA_MSS_TPCC_B_EVT_FREE_12 57

◆ EDMA_MSS_TPCC_B_EVT_FREE_13

#define EDMA_MSS_TPCC_B_EVT_FREE_13 58

◆ EDMA_MSS_TPCC_B_EVT_FREE_14

#define EDMA_MSS_TPCC_B_EVT_FREE_14 59

◆ EDMA_MSS_TPCC_B_EVT_FREE_15

#define EDMA_MSS_TPCC_B_EVT_FREE_15 60

◆ EDMA_MSS_TPCC_B_EVT_FREE_16

#define EDMA_MSS_TPCC_B_EVT_FREE_16 61

◆ EDMA_MSS_TPCC_B_EVT_FREE_17

#define EDMA_MSS_TPCC_B_EVT_FREE_17 62

◆ EDMA_MSS_TPCC_B_EVT_FREE_18

#define EDMA_MSS_TPCC_B_EVT_FREE_18 63

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ0

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ0 0

RCSS TPCC A EVENT MAP.

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ1

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ1 1

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ2

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ2 2

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ3

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ3 3

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ4

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ4 4

◆ EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ5

#define EDMA_RCSS_TPCC_A_EVT_SPIA_DMA_REQ5 5

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ0

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ0 6

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ1

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ1 7

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ2

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ2 8

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ3

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ3 9

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ4

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ4 10

◆ EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ5

#define EDMA_RCSS_TPCC_A_EVT_SPIB_DMA_REQ5 11

◆ EDMA_RCSS_TPCC_A_EVT_ECAP_DMA_REQ

#define EDMA_RCSS_TPCC_A_EVT_ECAP_DMA_REQ 12

◆ EDMA_RCSS_TPCC_A_EVT_FREE_0

#define EDMA_RCSS_TPCC_A_EVT_FREE_0 13

◆ EDMA_RCSS_TPCC_A_EVT_FREE_1

#define EDMA_RCSS_TPCC_A_EVT_FREE_1 14

◆ EDMA_RCSS_TPCC_A_EVT_FREE_2

#define EDMA_RCSS_TPCC_A_EVT_FREE_2 15

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOF_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOF_INT 16

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_INT 17

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX0_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX0_INT 18

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX1_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX1_INT 19

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX2_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX2_INT 20

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX3_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX3_INT 21

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX4_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX4_INT 22

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX5_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX5_INT 23

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX6_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX6_INT 24

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX7_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_EOL_CNTX7_INT 25

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG0_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG0_INT 26

◆ EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG1_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2A_SOF_TRIG1_INT 27

◆ EDMA_RCSS_TPCC_A_EVT_FREE_3

#define EDMA_RCSS_TPCC_A_EVT_FREE_3 28

◆ EDMA_RCSS_TPCC_A_EVT_FREE_4

#define EDMA_RCSS_TPCC_A_EVT_FREE_4 29

◆ EDMA_RCSS_TPCC_A_EVT_FREE_5

#define EDMA_RCSS_TPCC_A_EVT_FREE_5 30

◆ EDMA_RCSS_TPCC_A_EVT_FREE_6

#define EDMA_RCSS_TPCC_A_EVT_FREE_6 31

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOF_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOF_INT 32

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_INT 33

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX0_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX0_INT 34

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX1_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX1_INT 35

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX2_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX2_INT 36

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX3_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX3_INT 37

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX4_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX4_INT 38

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX5_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX5_INT 39

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX6_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX6_INT 40

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX7_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_EOL_CNTX7_INT 41

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG0_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG0_INT 42

◆ EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG1_INT

#define EDMA_RCSS_TPCC_A_EVT_CSI2B_SOF_TRIG1_INT 43

◆ EDMA_RCSS_TPCC_A_EVT_SCIA_TX_SINGLE_REQ

#define EDMA_RCSS_TPCC_A_EVT_SCIA_TX_SINGLE_REQ 44

◆ EDMA_RCSS_TPCC_A_EVT_SCIA_TX_BURST_REQ

#define EDMA_RCSS_TPCC_A_EVT_SCIA_TX_BURST_REQ 45

◆ EDMA_RCSS_TPCC_A_EVT_FREE_7

#define EDMA_RCSS_TPCC_A_EVT_FREE_7 46

◆ EDMA_RCSS_TPCC_A_EVT_FREE_8

#define EDMA_RCSS_TPCC_A_EVT_FREE_8 47

◆ EDMA_RCSS_TPCC_A_EVT_MCASPA_TX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPA_TX_REQ 48

◆ EDMA_RCSS_TPCC_A_EVT_MCASPB_TX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPB_TX_REQ 49

◆ EDMA_RCSS_TPCC_A_EVT_MCASPC_TX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPC_TX_REQ 50

◆ EDMA_RCSS_TPCC_A_EVT_MCASPA_RX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPA_RX_REQ 51

◆ EDMA_RCSS_TPCC_A_EVT_MCASPB_RX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPB_RX_REQ 52

◆ EDMA_RCSS_TPCC_A_EVT_MCASPC_RX_REQ

#define EDMA_RCSS_TPCC_A_EVT_MCASPC_RX_REQ 53

◆ EDMA_RCSS_TPCC_A_EVT_I2CA_TX_DMA_REQ

#define EDMA_RCSS_TPCC_A_EVT_I2CA_TX_DMA_REQ 54

◆ EDMA_RCSS_TPCC_A_EVT_I2CA_RX_DMA_REQ

#define EDMA_RCSS_TPCC_A_EVT_I2CA_RX_DMA_REQ 55

◆ EDMA_RCSS_TPCC_A_EVT_I2CB_TX_DMA_REQ

#define EDMA_RCSS_TPCC_A_EVT_I2CB_TX_DMA_REQ 56

◆ EDMA_RCSS_TPCC_A_EVT_I2CB_RX_DMA_REQ

#define EDMA_RCSS_TPCC_A_EVT_I2CB_RX_DMA_REQ 57

◆ EDMA_RCSS_TPCC_A_EVT_SCIA_RX_SINGLE_REQ

#define EDMA_RCSS_TPCC_A_EVT_SCIA_RX_SINGLE_REQ 58

◆ EDMA_RCSS_TPCC_A_EVT_SCIA_RX_BURST_REQ

#define EDMA_RCSS_TPCC_A_EVT_SCIA_RX_BURST_REQ 59

◆ EDMA_RCSS_TPCC_A_EVT_FREE_9

#define EDMA_RCSS_TPCC_A_EVT_FREE_9 60

◆ EDMA_RCSS_TPCC_A_EVT_FREE_10

#define EDMA_RCSS_TPCC_A_EVT_FREE_10 61

◆ EDMA_RCSS_TPCC_A_EVT_FREE_11

#define EDMA_RCSS_TPCC_A_EVT_FREE_11 62

◆ EDMA_RCSS_TPCC_A_EVT_FREE_12

#define EDMA_RCSS_TPCC_A_EVT_FREE_12 63

◆ EDMA_DSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_DSS_TPCC_A_NUM_PARAM_SETS (128U)

◆ EDMA_DSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_DSS_TPCC_A_NUM_DMA_CHANS (64U)

◆ EDMA_DSS_TPCC_A_NUM_TC

#define EDMA_DSS_TPCC_A_NUM_TC (2U)

◆ EDMA_DSS_TPCC_B_NUM_PARAM_SETS

#define EDMA_DSS_TPCC_B_NUM_PARAM_SETS (128U)

◆ EDMA_DSS_TPCC_B_NUM_DMA_CHANS

#define EDMA_DSS_TPCC_B_NUM_DMA_CHANS (64U)

◆ EDMA_DSS_TPCC_B_NUM_TC

#define EDMA_DSS_TPCC_B_NUM_TC (2U)

◆ EDMA_DSS_TPCC_C_NUM_PARAM_SETS

#define EDMA_DSS_TPCC_C_NUM_PARAM_SETS (256U)

◆ EDMA_DSS_TPCC_C_NUM_DMA_CHANS

#define EDMA_DSS_TPCC_C_NUM_DMA_CHANS (64U)

◆ EDMA_DSS_TPCC_C_NUM_TC

#define EDMA_DSS_TPCC_C_NUM_TC (2U)

Note even though EDMA's CCCFG register indicates 6 TCs for CC2, only first 2 are verified for radar processing flows, hence we limit to 2 TCs.

◆ EDMA_RCSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_RCSS_TPCC_A_NUM_PARAM_SETS (128U)

◆ EDMA_RDSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_RDSS_TPCC_A_NUM_DMA_CHANS (64U)

◆ EDMA_RCSS_TPCC_A_NUM_TC

#define EDMA_RCSS_TPCC_A_NUM_TC (2U)

◆ EDMA_MSS_TPCC_A_NUM_PARAM_SETS

#define EDMA_MSS_TPCC_A_NUM_PARAM_SETS (128U)

◆ EDMA_MSS_TPCC_A_NUM_DMA_CHANS

#define EDMA_MSS_TPCC_A_NUM_DMA_CHANS (64U)

◆ EDMA_MSS_TPCC_A_NUM_TC

#define EDMA_MSS_TPCC_A_NUM_TC (2U)

◆ EDMA_MSS_TPCC_B_NUM_PARAM_SETS

#define EDMA_MSS_TPCC_B_NUM_PARAM_SETS (128U)

◆ EDMA_MSS_TPCC_B_NUM_DMA_CHANS

#define EDMA_MSS_TPCC_B_NUM_DMA_CHANS (64U)

◆ EDMA_MSS_TPCC_B_NUM_TC

#define EDMA_MSS_TPCC_B_NUM_TC (1U)

◆ EDMA_HSM_TPCC_A_NUM_PARAM_SETS

#define EDMA_HSM_TPCC_A_NUM_PARAM_SETS (128U)

◆ EDMA_HSM_TPCC_A_NUM_TC

#define EDMA_HSM_TPCC_A_NUM_TC (2U)

◆ EDMA_TPCC_ERRAGG_TPCC_EERINT__POS

#define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS (0U)

◆ EDMA_TPCC_INTAGG_TPCC_INTG__POS

#define EDMA_TPCC_INTAGG_TPCC_INTG__POS (0U)

◆ EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS

#define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS (2U) /* position of the lowest TC Id, others are higher */

◆ EDMA_DSS_NUM_CC

#define EDMA_DSS_NUM_CC 4

◆ EDMA_DSS_MAX_NUM_TC

#define EDMA_DSS_MAX_NUM_TC

Value:

                                CSL_MAX(EDMA_DSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_DSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_DSS_TPCC_C_NUM_TC, \
                                EDMA_RCSS_TPCC_A_NUM_TC)))

◆ EDMA_MSS_NUM_CC

#define EDMA_MSS_NUM_CC 6

◆ EDMA_MSS_MAX_NUM_TC

#define EDMA_MSS_MAX_NUM_TC

Value:

                                CSL_MAX(EDMA_MSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_MSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_DSS_TPCC_A_NUM_TC, \
                                CSL_MAX(EDMA_DSS_TPCC_B_NUM_TC, \
                                CSL_MAX(EDMA_DSS_TPCC_C_NUM_TC, \
                                EDMA_RCSS_TPCC_A_NUM_TC)))))

◆ HWA_NUM_INSTANCES

#define HWA_NUM_INSTANCES (1U)

◆ SOC_HWA_NUM_MEM_BANKS

#define SOC_HWA_NUM_MEM_BANKS (8U)

number of HWA memory banks

◆ SOC_HWA_NUM_PARAM_SETS

#define SOC_HWA_NUM_PARAM_SETS (64U)

number of HWA parameter sets

◆ SOC_HWA_NUM_DMA_CHANNEL

#define SOC_HWA_NUM_DMA_CHANNEL (32U)

number of HWA MDA channels

◆ SOC_HWA_NUM_CSIRX_IRQS

#define SOC_HWA_NUM_CSIRX_IRQS (20U)

number of csirx IRQs

◆ SOC_HWA_MEM_SIZE

#define SOC_HWA_MEM_SIZE (CSL_DSS_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS)

number of HWA memory size in bytes

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END (0U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END (1U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END (2U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END (3U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END (4U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END (5U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END (6U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END (7U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0 (8U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1 (9U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END (10U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END (11U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END (12U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END (13U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END (14U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END (15U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END (16U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END (17U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0 (18U)

◆ HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1

#define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1 (19U)

◆ MSS_SYS_VCLK

#define MSS_SYS_VCLK 200000000U

◆ R5F_CLOCK_MHZ

#define R5F_CLOCK_MHZ 400U

◆ CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)

R5 Cluster Group ID0.

◆ CSL_ARM_R5_CPU_ID_0

#define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)

R5 Core ID0.

◆ CSL_ARM_R5_CPU_ID_1

#define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)

R5 Core ID1.

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