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AM273x MCU+ SDK
08.02.00
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33 #ifndef SOC_RCM_AM273X_H_
34 #define SOC_RCM_AM273X_H_
54 #define SOC_RCM_FREQ_HZ2MHZ(hz) ((hz)/(1000000U))
55 #define SOC_RCM_FREQ_MHZ2HZ(mhz) ((mhz)*(1000000U))
58 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 (1U << 0U)
60 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 (1U << 1U)
62 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 (1U << 2U)
64 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 (1U << 3U)
66 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 (1U << 4U)
68 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 (1U << 5U)
70 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 (1U << 6U)
72 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31 (1U << 7U)
74 #define SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL (SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 | \
75 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 | \
76 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 | \
77 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 | \
78 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 | \
79 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 | \
80 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 | \
81 SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31)
84 #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 (1U << 0U)
86 #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 (1U << 1U)
88 #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 (1U << 2U)
90 #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3 (1U << 3U)
92 #define SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL (SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 | \
93 SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 | \
94 SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 | \
95 SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3)
98 #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)
100 #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)
102 #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)
104 #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)
106 #define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0 | \
107 SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1 | \
108 SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2 | \
109 SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
112 #define SOC_RCM_PLL_HSDIV_OUTPUT_COUNT (4U)
117 typedef enum SOC_RcmResetCause_e
173 typedef enum SOC_RcmPeripheralId_e
297 typedef enum SOC_RcmPeripheralClockSource_e
337 typedef enum SOC_RcmDspClockSource_e
373 typedef enum SOC_RcmPllFoutFreqId_e
421 typedef enum SOC_RcmQspiClockFreqId_e {
444 typedef enum SOC_RcmEfuseFlashClkModeId_e {
463 typedef struct SOC_RcmPllHsDivOutConfig_s
472 typedef struct SOC_RcmEfuseQspiConfig_s
@ SOC_RcmEfuseFlashClkModeId_MAX_VALUE
max value
Definition: soc_rcm.h:457
@ SOC_RcmPeripheralId_DSS_RTIA
Value specifying DSS RTIA (Timer)
Definition: soc_rcm.h:238
@ SOC_RcmEfuseFlashClkModeId_0
Phase 0 : Polarity 0.
Definition: soc_rcm.h:449
@ SOC_RcmQspiClockFreqId_CLK_80MHZ
Value specifying QSPI clock of 80 Mhz.
Definition: soc_rcm.h:433
void SOC_rcmWaitMemInitTCMB(void)
Wait memory initialization to complete for R5 TCMB.
SOC_RcmQspiClockFreqId qspiClockFreqId
Efuse value for QSPI clock frequency.
Definition: soc_rcm.h:481
void SOC_rcmWaitMemInitDSSL2(uint32_t l2bankMask)
Wait memory initialization to complete for DSS L2.
@ SOC_RcmPeripheralId_DSS_RTIB
Value specifying DSS RTIB (Timer)
Definition: soc_rcm.h:242
@ SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
Value specifying R5 Core A Subsytem Reset.
Definition: soc_rcm.h:134
@ SOC_RcmPeripheralId_CSIRX
Value specifying CSI RX.
Definition: soc_rcm.h:178
SOC_RcmDspClockSource
DSP Clock Sources.
Definition: soc_rcm.h:338
@ SOC_RcmDspClockSource_DPLL_CORE_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1.
Definition: soc_rcm.h:350
@ SOC_RcmResetCause_MMR_CPU0_RESET
Value specifying R5 Core A (core only) Reset.
Definition: soc_rcm.h:142
SOC_RcmEfuseFlashClkModeId
Efuse value for flash clock mode.
Definition: soc_rcm.h:444
@ SOC_RcmPeripheralId_MSS_SPIB
Value specifying MSS SPI-B.
Definition: soc_rcm.h:214
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2 (96 Mhz)
Definition: soc_rcm.h:322
@ SOC_RcmPeripheralId_RCSS_SPIB
Value specifying RCSS SCIB.
Definition: soc_rcm.h:270
void SOC_rcmMemInitDssMailboxMemory(void)
Initialize the DSS mailbox memory.
SOC_RcmEfuseFlashClkModeId flashClockModeId
Efuse value for flash clock mode.
Definition: soc_rcm.h:477
void SOC_rcmStartMemInitMSSL2(void)
Start memory initialization for MSS L2.
@ SOC_RcmPeripheralId_MSS_MCANA
Value specifying MCANA.
Definition: soc_rcm.h:182
SOC_RcmPeripheralClockSource
Peripheral Clock Sources.
Definition: soc_rcm.h:298
@ SOC_RcmPllFoutFreqId_CLK_1800MHZ
Value specifying PLL Fout of 1800 Mhz.
Definition: soc_rcm.h:390
void SOC_rcmDspPllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Set DSP PLL Config.
void SOC_rcmGetEfuseQspiConfig(SOC_RcmEfuseQspiConfig *qspiEfuseCfg)
Get QSPI Efuse configuration.
void SOC_rcmDspPowerOnReset(void)
Reset Dsp Core.
@ SOC_RcmPeripheralId_RCSS_SPIA
Value specifying RCSS SPIA.
Definition: soc_rcm.h:266
@ SOC_RcmPeripheralId_MSS_RTIB
Value specifying MSS RTIB (Timer)
Definition: soc_rcm.h:198
@ SOC_RcmPllFoutFreqId_CLK_1966p08MHZ
Value specifying PLL Fout of 1966.08 Mhz.
Definition: soc_rcm.h:406
void SOC_rcmWaitMemInitTCMA(void)
Wait memory initialization to complete for R5 TCMA.
@ SOC_RcmPeripheralId_DSS_WDT
Value specifying DSS WatchDog.
Definition: soc_rcm.h:246
@ SOC_RcmPeripheralId_RCSS_I2CB
Value specifying RCSS I2CB.
Definition: soc_rcm.h:258
SOC_RcmQspiClockFreqId
QSPI frequency values.
Definition: soc_rcm.h:421
@ SOC_RcmPeripheralId_DSS_SCIA
Value specifying DSS SCI-A (UART)
Definition: soc_rcm.h:250
@ SOC_RcmPeripheralId_MSS_CPTS
Value specifying CPTS (Timesync module)
Definition: soc_rcm.h:230
SOC_RcmResetCause SOC_rcmGetResetCause(void)
Get SOC reset cause.
@ SOC_RcmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:122
void SOC_rcmMemInitMssMailboxMemory(void)
Initialize the MSS mailbox memory.
@ SOC_RcmPeripheralId_MSS_MCANB
Value specifying MCANB.
Definition: soc_rcm.h:186
SOC_RcmPeripheralId
Peripheral IDs.
Definition: soc_rcm.h:174
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3
Value specifying PLL Core Clock Out 3 (172.8 Mhz)
Definition: soc_rcm.h:326
@ SOC_RcmResetCause_RST_CAUSE_UNKNOWN
Value specifying R5 Reset due to Unknown reason.
Definition: soc_rcm.h:162
@ SOC_RcmPllFoutFreqId_CLK_2000MHZ
Value specifying PLL Fout of 2000 Mhz.
Definition: soc_rcm.h:386
@ SOC_RcmPeripheralId_MSS_SCIA
Value specifying MSS SCI-A (UART)
Definition: soc_rcm.h:222
void SOC_rcmWaitMemInitDSSL3(uint32_t l3bankMask)
Wait memory initialization to complete for DSS L3.
uint32_t SOC_rcmGetDspClock()
Get DSP frequency.
@ SOC_RcmPeripheralClockSource_SYS_CLK
Value specifying System Clock (200Mhz)
Definition: soc_rcm.h:306
Structure to specific PLL HS divider output frequencies.
Definition: soc_rcm.h:464
@ SOC_RcmPllFoutFreqId_CLK_900MHZ
Value specifying PLL Fout of 900 Mhz.
Definition: soc_rcm.h:382
@ SOC_RcmDspClockSource_MAX_VALUE
max value
Definition: soc_rcm.h:354
@ SOC_RcmPeripheralId_RCSS_MCASPC_AUX
Value specifying RCSS MCASPC AUX.
Definition: soc_rcm.h:286
@ SOC_RcmDspClockSource_DPLL_DSP_HSDIV0_CLKOUT1
Value specifying PLL DSP Clock Out 2 (450 Mhz)
Definition: soc_rcm.h:346
void SOC_rcmR5ConfigLockStep(void)
Configure R5 in lock step mode.
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
Set peripheral frequency.
void SOC_rcmStartMemInitTCMB(void)
Start memory initialization for R5 TCMB.
int32_t SOC_rcmSetDspClock(SOC_RcmDspClockSource clkSource, uint32_t freqHz)
Set DSP frequency.
void SOC_rcmPerPllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Set Peripheral PLL Config.
Efuse value for QSPI config.
Definition: soc_rcm.h:473
@ SOC_RcmPllFoutFreqId_MAX_VALUE
max value
Definition: soc_rcm.h:414
@ SOC_RcmPeripheralId_RCSS_I2CA
Value specifying RCSS I2CA.
Definition: soc_rcm.h:254
void SOC_rcmR5TriggerReset(void)
Trigger R5 core reset.
@ SOC_RcmPeripheralId_MAX_VALUE
max value
Definition: soc_rcm.h:290
@ SOC_RcmEfuseFlashClkModeId_3
Phase 1 : Polarity 1.
Definition: soc_rcm.h:453
@ SOC_RcmResetCause_FSM_TRIGGER_RESET
Value specifying R5 Reset due to FSM Trigger.
Definition: soc_rcm.h:158
SOC_RcmResetCause
Reset Causes.
Definition: soc_rcm.h:118
@ SOC_RcmResetCause_DBG_CPU1_RESET
Value specifying R5 Core B Debug Reset.
Definition: soc_rcm.h:154
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz)
Set R5 and SycClk frequency.
@ SOC_RcmPeripheralClockSource_MAX_VALUE
max value
Definition: soc_rcm.h:330
@ SOC_RcmResetCause_DBG_CPU0_RESET
Value specifying R5 Core A Debug Reset.
Definition: soc_rcm.h:150
void SOC_rcmWaitMemInitMSSL2(void)
Wait memory initialization to complete for MSS L2.
uint32_t hsdivOutEnMask
Definition: soc_rcm.h:465
@ SOC_RcmPeripheralId_RCSS_MCASPB_AUX
Value specifying RCSS MCASPB AUX.
Definition: soc_rcm.h:282
#define SOC_RCM_PLL_HSDIV_OUTPUT_COUNT
Definition: soc_rcm.h:112
@ SOC_RcmDspClockSource_XTAL_CLK
Value specifying Crystal Clock.
Definition: soc_rcm.h:342
@ SOC_RcmPllFoutFreqId_CLK_1699p21875MHZ
Value specifying PLL Fout of 1699.21875 Mhz.
Definition: soc_rcm.h:398
SOC_RcmR5ClockSource
R5 Clock Sources.
Definition: soc_rcm.h:362
void SOC_rcmC66xStart(void)
Unhalt C66x Core.
@ SOC_RcmPllFoutFreqId_CLK_1806p336MHZ
Value specifying PLL Fout of 1806.336 Mhz.
Definition: soc_rcm.h:410
@ SOC_RcmPeripheralId_MSS_WDT
Value specifying MSS WatchDog.
Definition: soc_rcm.h:206
@ SOC_RcmPeripheralId_MSS_CPSW
Value specifying CPSW (2 port ethernet switch)
Definition: soc_rcm.h:234
void SOC_rcmConfigEthMacIf(void)
RCM configuration for MAC interface.
void SOC_rcmCr5bUnhalt(void)
Unhalt R5 core 1.
void SOC_rcmStartMemInitTCMA(void)
Start memory initialization for R5 TCMA.
@ SOC_RcmPeripheralId_RCSS_MCASPA_AUX
Value specifying RCSS MCASPA AUX.
Definition: soc_rcm.h:278
@ SOC_RcmQspiClockFreqId_CLK_40MHZ
Value specifying QSPI clock of 40 Mhz.
Definition: soc_rcm.h:425
void SOC_rcmStartMemInitDSSL3(uint32_t l3bankMask)
Start memory initialization for DSS L3.
@ SOC_RcmPeripheralId_MSS_QSPI
Value specifying QSPI (Quad SPI)
Definition: soc_rcm.h:190
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (192 Mhz)
Definition: soc_rcm.h:318
@ SOC_RcmPeripheralId_MSS_SCIB
Value specifying MSS SCI-B (UART)
Definition: soc_rcm.h:226
void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllHsDivOutConfig *hsDivCfg)
Set CORE PLL Hs Div Config.
@ SOC_RcmPeripheralId_RCSS_SCIA
Value specifying RCSS SCIA.
Definition: soc_rcm.h:262
@ SOC_RcmR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2.
Definition: soc_rcm.h:366
@ SOC_RcmPeripheralId_RCSS_ATL
Value specifying RCSS ATL.
Definition: soc_rcm.h:274
@ SOC_RcmPeripheralId_MSS_I2C
Value specifying MSS I2C.
Definition: soc_rcm.h:218
@ SOC_RcmPllFoutFreqId_CLK_800MHZ
Value specifying PLL Fout of 800 Mhz.
Definition: soc_rcm.h:378
@ SOC_RcmResetCause_STC_RESET
Value specifying STC Reset.
Definition: soc_rcm.h:130
void SOC_rcmStartMemInitDSSL2(uint32_t l2bankMask)
Start memory initialization for DSS L2.
uint32_t SOC_rcmGetR5Clock(void)
Get R5 frequency.
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (400 Mhz)
Definition: soc_rcm.h:310
@ SOC_RcmPeripheralId_MSS_RTIA
Value specifying MSS RTIA (Timer)
Definition: soc_rcm.h:194
@ SOC_RcmPllFoutFreqId_CLK_1920MHZ
Value specifying PLL Fout of 1920 Mhz.
Definition: soc_rcm.h:394
@ SOC_RcmResetCause_WARM_RESET
Value specifying Warm Reset.
Definition: soc_rcm.h:126
@ SOC_RcmQspiClockFreqId_CLK_60MHZ
Value specifying QSPI clock of 60 Mhz.
Definition: soc_rcm.h:429
@ SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
Value specifying R5 Core B Subsytem Reset.
Definition: soc_rcm.h:138
uint32_t SOC_rcmGetPeripheralClock(SOC_RcmPeripheralId periphId)
Get peripheral frequency.
SOC_RcmPllFoutFreqId
PLL Fout values.
Definition: soc_rcm.h:374
@ SOC_RcmQspiClockFreqId_MAX_VALUE
max value
Definition: soc_rcm.h:437
@ SOC_RcmPeripheralId_MSS_RTIC
Value specifying MSS RTIC (Timer)
Definition: soc_rcm.h:202
@ SOC_RcmResetCause_MMR_CPU1_RESET
Value specifying R5 Core B (core only) Reset.
Definition: soc_rcm.h:146
@ SOC_RcmResetCause_MAX_VALUE
max value
Definition: soc_rcm.h:166
@ SOC_RcmPeripheralClockSource_XTAL_CLK
Value specifying Crystal Clock.
Definition: soc_rcm.h:302
@ SOC_RcmPllFoutFreqId_CLK_1728MHZ
Value specifying PLL Fout of 1728 Mhz.
Definition: soc_rcm.h:402
void SOC_rcmR5PowerOnReset(void)
Reset R5 Core.
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2 (400 Mhz)
Definition: soc_rcm.h:314
void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Set CORE PLL Config.
@ SOC_RcmPeripheralId_MSS_SPIA
Value specifying MSS SPI-A.
Definition: soc_rcm.h:210
void SOC_rcmR5ConfigDualCore(void)
Configure R5 in dual core mode.