APIs for SOC Reset and Clock Functions

Introduction

For more details and example usage, see SOC

Data Structures
struct	SOC_RcmPllHsDivOutConfig
	Structure to specific PLL HS divider output frequencies. More...
struct	SOC_RcmEfuseQspiConfig
	Efuse value for QSPI config. More...

Functions
void	SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set CORE PLL Config. More...
void	SOC_rcmCoreApllHSDivConfig (SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set CORE PLL Hs Div Config. More...
void	SOC_rcmDspPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set DSP PLL Config. More...
void	SOC_rcmPerPllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
	Set Peripheral PLL Config. More...
int32_t	SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz)
	Set R5 and SycClk frequency. More...
uint32_t	SOC_rcmGetR5Clock (void)
	Get R5 frequency. More...
int32_t	SOC_rcmSetDspClock (SOC_RcmDspClockSource clkSource, uint32_t freqHz)
	Set DSP frequency. More...
uint32_t	SOC_rcmGetDspClock ()
	Get DSP frequency. More...
int32_t	SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
	Set peripheral frequency. More...
uint32_t	SOC_rcmGetPeripheralClock (SOC_RcmPeripheralId periphId)
	Get peripheral frequency. More...
void	SOC_rcmDspPowerOnReset (void)
	Reset Dsp Core. More...
void	SOC_rcmR5PowerOnReset (void)
	Reset R5 Core. More...
void	SOC_rcmR5ConfigLockStep (void)
	Configure R5 in lock step mode. More...
void	SOC_rcmR5ConfigDualCore (void)
	Configure R5 in dual core mode. More...
void	SOC_rcmR5TriggerReset (void)
	Trigger R5 core reset. More...
void	SOC_rcmCr5bUnhalt (void)
	Unhalt R5 core 1. More...
void	SOC_rcmC66xStart (void)
	Unhalt C66x Core. More...
void	SOC_rcmGetEfuseQspiConfig (SOC_RcmEfuseQspiConfig *qspiEfuseCfg)
	Get QSPI Efuse configuration. More...
SOC_RcmResetCause	SOC_rcmGetResetCause (void)
	Get SOC reset cause. More...
void	SOC_rcmStartMemInitTCMA (void)
	Start memory initialization for R5 TCMA. More...
void	SOC_rcmWaitMemInitTCMA (void)
	Wait memory initialization to complete for R5 TCMA. More...
void	SOC_rcmStartMemInitTCMB (void)
	Start memory initialization for R5 TCMB. More...
void	SOC_rcmWaitMemInitTCMB (void)
	Wait memory initialization to complete for R5 TCMB. More...
void	SOC_rcmMemInitMssMailboxMemory (void)
	Initialize the MSS mailbox memory. More...
void	SOC_rcmMemInitDssMailboxMemory (void)
	Initialize the DSS mailbox memory. More...
void	SOC_rcmStartMemInitMSSL2 (void)
	Start memory initialization for MSS L2. More...
void	SOC_rcmWaitMemInitMSSL2 (void)
	Wait memory initialization to complete for MSS L2. More...
void	SOC_rcmStartMemInitDSSL2 (uint32_t l2bankMask)
	Start memory initialization for DSS L2. More...
void	SOC_rcmWaitMemInitDSSL2 (uint32_t l2bankMask)
	Wait memory initialization to complete for DSS L2. More...
void	SOC_rcmStartMemInitDSSL3 (uint32_t l3bankMask)
	Start memory initialization for DSS L3. More...
void	SOC_rcmWaitMemInitDSSL3 (uint32_t l3bankMask)
	Wait memory initialization to complete for DSS L3. More...
void	SOC_rcmConfigEthMacIf (void)
	RCM configuration for MAC interface. More...

Enumerations
enum	SOC_RcmResetCause {   SOC_RcmResetCause_POWER_ON_RESET = 0x0U, SOC_RcmResetCause_WARM_RESET = 0x1U, SOC_RcmResetCause_STC_RESET = 0x2U, SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,   SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U, SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U, SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U, SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,   SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U, SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U, SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xAU, SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu }
	Reset Causes. More...
enum	SOC_RcmPeripheralId {   SOC_RcmPeripheralId_CSIRX, SOC_RcmPeripheralId_MSS_MCANA, SOC_RcmPeripheralId_MSS_MCANB, SOC_RcmPeripheralId_MSS_QSPI,   SOC_RcmPeripheralId_MSS_RTIA, SOC_RcmPeripheralId_MSS_RTIB, SOC_RcmPeripheralId_MSS_RTIC, SOC_RcmPeripheralId_MSS_WDT,   SOC_RcmPeripheralId_MSS_SPIA, SOC_RcmPeripheralId_MSS_SPIB, SOC_RcmPeripheralId_MSS_I2C, SOC_RcmPeripheralId_MSS_SCIA,   SOC_RcmPeripheralId_MSS_SCIB, SOC_RcmPeripheralId_MSS_CPTS, SOC_RcmPeripheralId_MSS_CPSW, SOC_RcmPeripheralId_DSS_RTIA,   SOC_RcmPeripheralId_DSS_RTIB, SOC_RcmPeripheralId_DSS_WDT, SOC_RcmPeripheralId_DSS_SCIA, SOC_RcmPeripheralId_RCSS_I2CA,   SOC_RcmPeripheralId_RCSS_I2CB, SOC_RcmPeripheralId_RCSS_SCIA, SOC_RcmPeripheralId_RCSS_SPIA, SOC_RcmPeripheralId_RCSS_SPIB,   SOC_RcmPeripheralId_RCSS_ATL, SOC_RcmPeripheralId_RCSS_MCASPA_AUX, SOC_RcmPeripheralId_RCSS_MCASPB_AUX, SOC_RcmPeripheralId_RCSS_MCASPC_AUX,   SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral IDs. More...
enum	SOC_RcmPeripheralClockSource {   SOC_RcmPeripheralClockSource_XTAL_CLK, SOC_RcmPeripheralClockSource_SYS_CLK, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,   SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3, SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral Clock Sources. More...
enum	SOC_RcmDspClockSource { SOC_RcmDspClockSource_XTAL_CLK, SOC_RcmDspClockSource_DPLL_DSP_HSDIV0_CLKOUT1, SOC_RcmDspClockSource_DPLL_CORE_HSDIV0_CLKOUT1, SOC_RcmDspClockSource_MAX_VALUE = 0xFFFFFFFFu }
	DSP Clock Sources. More...
enum	SOC_RcmR5ClockSource { SOC_RcmR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2 }
	R5 Clock Sources. More...
enum	SOC_RcmPllFoutFreqId {   SOC_RcmPllFoutFreqId_CLK_800MHZ, SOC_RcmPllFoutFreqId_CLK_900MHZ, SOC_RcmPllFoutFreqId_CLK_2000MHZ, SOC_RcmPllFoutFreqId_CLK_1800MHZ,   SOC_RcmPllFoutFreqId_CLK_1920MHZ, SOC_RcmPllFoutFreqId_CLK_1699p21875MHZ, SOC_RcmPllFoutFreqId_CLK_1728MHZ, SOC_RcmPllFoutFreqId_CLK_1966p08MHZ,   SOC_RcmPllFoutFreqId_CLK_1806p336MHZ, SOC_RcmPllFoutFreqId_MAX_VALUE = 0xFFFFFFFFu }
	PLL Fout values. More...
enum	SOC_RcmQspiClockFreqId { SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0, SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1, SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2, SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu }
	QSPI frequency values. More...
enum	SOC_RcmEfuseFlashClkModeId { SOC_RcmEfuseFlashClkModeId_0 = 0x0, SOC_RcmEfuseFlashClkModeId_3 = 0x3, SOC_RcmEfuseFlashClkModeId_MAX_VALUE = 0xFFFFFFFFu }
	Efuse value for flash clock mode. More...

Macros
#define	SOC_RCM_FREQ_HZ2MHZ(hz)   ((hz)/(1000000U))
#define	SOC_RCM_FREQ_MHZ2HZ(mhz)   ((mhz)*(1000000U))
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00   (1U << 0U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01   (1U << 1U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10   (1U << 2U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11   (1U << 3U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20   (1U << 4U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21   (1U << 5U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30   (1U << 6U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31   (1U << 7U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0   (1U << 0U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1   (1U << 1U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2   (1U << 2U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3   (1U << 3U)
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL
	bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2 More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0   (1U << 0U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1   (1U << 1U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2   (1U << 2U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3   (1U << 3U)
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL
	HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig. More...
#define	SOC_RCM_PLL_HSDIV_OUTPUT_COUNT   (4U)

Macro Definition Documentation

SOC_RCM_FREQ_HZ2MHZ

#define SOC_RCM_FREQ_HZ2MHZ

(

hz

)

((hz)/(1000000U))

SOC_RCM_FREQ_MHZ2HZ

#define SOC_RCM_FREQ_MHZ2HZ

(

mhz

)

((mhz)*(1000000U))

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00   (1U << 0U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01   (1U << 1U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10   (1U << 2U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11   (1U << 3U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20   (1U << 4U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21   (1U << 5U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30   (1U << 6U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31   (1U << 7U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL

#define SOC_RCM_MEMINIT_DSSL2_MEMBANK_ALL

Value:

                                               (SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB00 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB01 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB10 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB11 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB20 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB21 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB30 | \
                                               SOC_RCM_MEMINIT_DSSL2_MEMBANK_VB31)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL2(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0

#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0   (1U << 0U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1

#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1   (1U << 1U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2

#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2   (1U << 2U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3

#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3   (1U << 3U)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL

#define SOC_RCM_MEMINIT_DSSL3_MEMBANK_ALL

Value:

                                               (SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM0 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM1 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM2 | \
                                               SOC_RCM_MEMINIT_DSSL3_MEMBANK_RAM3)

bit mask to specify DSS L2 MEM BANKs, used with SOC_rcmStartMemInitDSSL3(), SOC_rcmWaitMemInitDSSL2

SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0

#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0   (1U << 0U)

HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.

SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1

#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1   (1U << 1U)

HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.

SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2

#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2   (1U << 2U)

HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.

SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3

#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3   (1U << 3U)

HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.

SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

#define SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL

Value:

                                                (SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_0   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_1   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_2   | \
                                                SOC_RCM_PLL_HSDIV_OUTPUT_ENABLE_3)

HSDIV output enable bitmask, used with SOC_RcmPllHsDivOutConfig.

SOC_RCM_PLL_HSDIV_OUTPUT_COUNT

#define SOC_RCM_PLL_HSDIV_OUTPUT_COUNT   (4U)

Enumeration Type Documentation

SOC_RcmResetCause

enum SOC_RcmResetCause

Reset Causes.

Enumerator
SOC_RcmResetCause_POWER_ON_RESET	Value specifying Power ON Reset.
SOC_RcmResetCause_WARM_RESET	Value specifying Warm Reset.
SOC_RcmResetCause_STC_RESET	Value specifying STC Reset.
SOC_RcmResetCause_MMR_CPU0_VIM0_RESET	Value specifying R5 Core A Subsytem Reset.
SOC_RcmResetCause_MMR_CPU1_VIM1_RESET	Value specifying R5 Core B Subsytem Reset.
SOC_RcmResetCause_MMR_CPU0_RESET	Value specifying R5 Core A (core only) Reset.
SOC_RcmResetCause_MMR_CPU1_RESET	Value specifying R5 Core B (core only) Reset.
SOC_RcmResetCause_DBG_CPU0_RESET	Value specifying R5 Core A Debug Reset.
SOC_RcmResetCause_DBG_CPU1_RESET	Value specifying R5 Core B Debug Reset.
SOC_RcmResetCause_FSM_TRIGGER_RESET	Value specifying R5 Reset due to FSM Trigger.
SOC_RcmResetCause_RST_CAUSE_UNKNOWN	Value specifying R5 Reset due to Unknown reason.
SOC_RcmResetCause_MAX_VALUE	max value

SOC_RcmPeripheralId

enum SOC_RcmPeripheralId

Peripheral IDs.

Enumerator
SOC_RcmPeripheralId_CSIRX	Value specifying CSI RX.
SOC_RcmPeripheralId_MSS_MCANA	Value specifying MCANA.
SOC_RcmPeripheralId_MSS_MCANB	Value specifying MCANB.
SOC_RcmPeripheralId_MSS_QSPI	Value specifying QSPI (Quad SPI)
SOC_RcmPeripheralId_MSS_RTIA	Value specifying MSS RTIA (Timer)
SOC_RcmPeripheralId_MSS_RTIB	Value specifying MSS RTIB (Timer)
SOC_RcmPeripheralId_MSS_RTIC	Value specifying MSS RTIC (Timer)
SOC_RcmPeripheralId_MSS_WDT	Value specifying MSS WatchDog.
SOC_RcmPeripheralId_MSS_SPIA	Value specifying MSS SPI-A.
SOC_RcmPeripheralId_MSS_SPIB	Value specifying MSS SPI-B.
SOC_RcmPeripheralId_MSS_I2C	Value specifying MSS I2C.
SOC_RcmPeripheralId_MSS_SCIA	Value specifying MSS SCI-A (UART)
SOC_RcmPeripheralId_MSS_SCIB	Value specifying MSS SCI-B (UART)
SOC_RcmPeripheralId_MSS_CPTS	Value specifying CPTS (Timesync module)
SOC_RcmPeripheralId_MSS_CPSW	Value specifying CPSW (2 port ethernet switch)
SOC_RcmPeripheralId_DSS_RTIA	Value specifying DSS RTIA (Timer)
SOC_RcmPeripheralId_DSS_RTIB	Value specifying DSS RTIB (Timer)
SOC_RcmPeripheralId_DSS_WDT	Value specifying DSS WatchDog.
SOC_RcmPeripheralId_DSS_SCIA	Value specifying DSS SCI-A (UART)
SOC_RcmPeripheralId_RCSS_I2CA	Value specifying RCSS I2CA.
SOC_RcmPeripheralId_RCSS_I2CB	Value specifying RCSS I2CB.
SOC_RcmPeripheralId_RCSS_SCIA	Value specifying RCSS SCIA.
SOC_RcmPeripheralId_RCSS_SPIA	Value specifying RCSS SPIA.
SOC_RcmPeripheralId_RCSS_SPIB	Value specifying RCSS SCIB.
SOC_RcmPeripheralId_RCSS_ATL	Value specifying RCSS ATL.
SOC_RcmPeripheralId_RCSS_MCASPA_AUX	Value specifying RCSS MCASPA AUX.
SOC_RcmPeripheralId_RCSS_MCASPB_AUX	Value specifying RCSS MCASPB AUX.
SOC_RcmPeripheralId_RCSS_MCASPC_AUX	Value specifying RCSS MCASPC AUX.
SOC_RcmPeripheralId_MAX_VALUE	max value

SOC_RcmPeripheralClockSource

enum SOC_RcmPeripheralClockSource

Peripheral Clock Sources.

Enumerator
SOC_RcmPeripheralClockSource_XTAL_CLK	Value specifying Crystal Clock.
SOC_RcmPeripheralClockSource_SYS_CLK	Value specifying System Clock (200Mhz)
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1	Value specifying PLL Core Clock Out 1 (400 Mhz)
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2	Value specifying PLL Core Clock Out 2 (400 Mhz)
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1	Value specifying PLL Core Clock Out 1 (192 Mhz)
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2	Value specifying PLL Core Clock Out 2 (96 Mhz)
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3	Value specifying PLL Core Clock Out 3 (172.8 Mhz)
SOC_RcmPeripheralClockSource_MAX_VALUE	max value

SOC_RcmDspClockSource

enum SOC_RcmDspClockSource

DSP Clock Sources.

Enumerator
SOC_RcmDspClockSource_XTAL_CLK	Value specifying Crystal Clock.
SOC_RcmDspClockSource_DPLL_DSP_HSDIV0_CLKOUT1	Value specifying PLL DSP Clock Out 2 (450 Mhz)
SOC_RcmDspClockSource_DPLL_CORE_HSDIV0_CLKOUT1	Value specifying PLL Core Clock Out 1.
SOC_RcmDspClockSource_MAX_VALUE	max value

SOC_RcmR5ClockSource

enum SOC_RcmR5ClockSource

R5 Clock Sources.

Enumerator
SOC_RcmR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2	Value specifying PLL Core Clock Out 2.

SOC_RcmPllFoutFreqId

enum SOC_RcmPllFoutFreqId

PLL Fout values.

Enumerator
SOC_RcmPllFoutFreqId_CLK_800MHZ	Value specifying PLL Fout of 800 Mhz.
SOC_RcmPllFoutFreqId_CLK_900MHZ	Value specifying PLL Fout of 900 Mhz.
SOC_RcmPllFoutFreqId_CLK_2000MHZ	Value specifying PLL Fout of 2000 Mhz.
SOC_RcmPllFoutFreqId_CLK_1800MHZ	Value specifying PLL Fout of 1800 Mhz.
SOC_RcmPllFoutFreqId_CLK_1920MHZ	Value specifying PLL Fout of 1920 Mhz.
SOC_RcmPllFoutFreqId_CLK_1699p21875MHZ	Value specifying PLL Fout of 1699.21875 Mhz.
SOC_RcmPllFoutFreqId_CLK_1728MHZ	Value specifying PLL Fout of 1728 Mhz.
SOC_RcmPllFoutFreqId_CLK_1966p08MHZ	Value specifying PLL Fout of 1966.08 Mhz.
SOC_RcmPllFoutFreqId_CLK_1806p336MHZ	Value specifying PLL Fout of 1806.336 Mhz.
SOC_RcmPllFoutFreqId_MAX_VALUE	max value

SOC_RcmQspiClockFreqId

enum SOC_RcmQspiClockFreqId

QSPI frequency values.

Enumerator
SOC_RcmQspiClockFreqId_CLK_40MHZ	Value specifying QSPI clock of 40 Mhz.
SOC_RcmQspiClockFreqId_CLK_60MHZ	Value specifying QSPI clock of 60 Mhz.
SOC_RcmQspiClockFreqId_CLK_80MHZ	Value specifying QSPI clock of 80 Mhz.
SOC_RcmQspiClockFreqId_MAX_VALUE	max value

SOC_RcmEfuseFlashClkModeId

enum SOC_RcmEfuseFlashClkModeId

Efuse value for flash clock mode.

Enumerator
SOC_RcmEfuseFlashClkModeId_0	Phase 0 : Polarity 0.
SOC_RcmEfuseFlashClkModeId_3	Phase 1 : Polarity 1.
SOC_RcmEfuseFlashClkModeId_MAX_VALUE	max value

Function Documentation

SOC_rcmCoreApllConfig()

void SOC_rcmCoreApllConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Set CORE PLL Config.

Parameters

outFreqId	[in] Output frequency form the PLL
hsDivCfg	[in] Set HS divider output frequencies

SOC_rcmCoreApllHSDivConfig()

void SOC_rcmCoreApllHSDivConfig

(

SOC_RcmPllHsDivOutConfig *

hsDivCfg

)

Set CORE PLL Hs Div Config.

Parameters

hsDivCfg

[in] Set HS divider output frequencies

SOC_rcmDspPllConfig()

void SOC_rcmDspPllConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Set DSP PLL Config.

Parameters

outFreqId	[in] Output frequency form the PLL
hsDivCfg	[in] Set HS divider output frequencies

SOC_rcmPerPllConfig()

void SOC_rcmPerPllConfig	(	SOC_RcmPllFoutFreqId	outFreqId,
		SOC_RcmPllHsDivOutConfig *	hsDivCfg
	)

Set Peripheral PLL Config.

Parameters

outFreqId	[in] Output frequency form the PLL
hsDivCfg	[in] Set HS divider output frequencies

SOC_rcmSetR5Clock()

int32_t SOC_rcmSetR5Clock	(	uint32_t	r5FreqHz,
		uint32_t	sysClkFreqHz
	)

Set R5 and SycClk frequency.

Parameters

r5FreqHz	[in] R5 frequency, in Hz
sysClkFreqHz	[in] SysClk frequency, in Hz

Returns

SystemP_SUCCESS on success, else failure

SOC_rcmGetR5Clock()

uint32_t SOC_rcmGetR5Clock

(

void

)

Get R5 frequency.

Returns

R5 frequency, in Hz

SOC_rcmSetDspClock()

int32_t SOC_rcmSetDspClock	(	SOC_RcmDspClockSource	clkSource,
		uint32_t	freqHz
	)

Set DSP frequency.

Parameters

clkSource	[in] DSP clock source to use
freqHz	[in] DSP frequency, in Hz

Returns

SystemP_SUCCESS on success, else failure

SOC_rcmGetDspClock()

uint32_t SOC_rcmGetDspClock

(

)

Get DSP frequency.

Returns

DSP frequency, in Hz

SOC_rcmSetPeripheralClock()

int32_t SOC_rcmSetPeripheralClock	(	SOC_RcmPeripheralId	periphId,
		SOC_RcmPeripheralClockSource	clkSource,
		uint32_t	freqHz
	)

Set peripheral frequency.

Parameters

periphId	[in] Peripheral ID
clkSource	[in] Peripheral clock source to use
freqHz	[in] Peripheral frequency, in Hz

Returns

SystemP_SUCCESS on success, else failure

SOC_rcmGetPeripheralClock()

uint32_t SOC_rcmGetPeripheralClock

(

SOC_RcmPeripheralId

periphId

)

Get peripheral frequency.

Parameters

periphId

[in] Peripheral ID

Returns

Peripheral frequency, in Hz

SOC_rcmDspPowerOnReset()

void SOC_rcmDspPowerOnReset

(

void

)

Reset Dsp Core.

SOC_rcmR5PowerOnReset()

void SOC_rcmR5PowerOnReset

(

void

)

Reset R5 Core.

SOC_rcmR5ConfigLockStep()

void SOC_rcmR5ConfigLockStep

(

void

)

Configure R5 in lock step mode.

SOC_rcmR5ConfigDualCore()

void SOC_rcmR5ConfigDualCore

(

void

)

Configure R5 in dual core mode.

SOC_rcmR5TriggerReset()

void SOC_rcmR5TriggerReset

(

void

)

Trigger R5 core reset.

SOC_rcmCr5bUnhalt()

void SOC_rcmCr5bUnhalt

(

void

)

Unhalt R5 core 1.

SOC_rcmC66xStart()

void SOC_rcmC66xStart

(

void

)

Unhalt C66x Core.

SOC_rcmGetEfuseQspiConfig()

void SOC_rcmGetEfuseQspiConfig

(

SOC_RcmEfuseQspiConfig *

qspiEfuseCfg

)

Get QSPI Efuse configuration.

Parameters

qspiEfuseCfg

[out] QSPI Efuse configuration

SOC_rcmGetResetCause()

SOC_RcmResetCause SOC_rcmGetResetCause

(

void

)

Get SOC reset cause.

Returns

SOC reset cause

SOC_rcmStartMemInitTCMA()

void SOC_rcmStartMemInitTCMA

(

void

)

Start memory initialization for R5 TCMA.

SOC_rcmWaitMemInitTCMA()

void SOC_rcmWaitMemInitTCMA

(

void

)

Wait memory initialization to complete for R5 TCMA.

SOC_rcmStartMemInitTCMB()

void SOC_rcmStartMemInitTCMB

(

void

)

Start memory initialization for R5 TCMB.

SOC_rcmWaitMemInitTCMB()

void SOC_rcmWaitMemInitTCMB

(

void

)

Wait memory initialization to complete for R5 TCMB.

SOC_rcmMemInitMssMailboxMemory()

void SOC_rcmMemInitMssMailboxMemory

(

void

)

Initialize the MSS mailbox memory.

SOC_rcmMemInitDssMailboxMemory()

void SOC_rcmMemInitDssMailboxMemory

(

void

)

Initialize the DSS mailbox memory.

SOC_rcmStartMemInitMSSL2()

void SOC_rcmStartMemInitMSSL2

(

void

)

Start memory initialization for MSS L2.

SOC_rcmWaitMemInitMSSL2()

void SOC_rcmWaitMemInitMSSL2

(

void

)

Wait memory initialization to complete for MSS L2.

SOC_rcmStartMemInitDSSL2()

void SOC_rcmStartMemInitDSSL2

(

uint32_t

l2bankMask

)

Start memory initialization for DSS L2.

SOC_rcmWaitMemInitDSSL2()

void SOC_rcmWaitMemInitDSSL2

(

uint32_t

l2bankMask

)

Wait memory initialization to complete for DSS L2.

SOC_rcmStartMemInitDSSL3()

void SOC_rcmStartMemInitDSSL3

(

uint32_t

l3bankMask

)

Start memory initialization for DSS L3.

SOC_rcmWaitMemInitDSSL3()

void SOC_rcmWaitMemInitDSSL3

(

uint32_t

l3bankMask

)

Wait memory initialization to complete for DSS L3.

SOC_rcmConfigEthMacIf()

void SOC_rcmConfigEthMacIf

(

void

)

RCM configuration for MAC interface.