qspi_lld.h

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/*
 *  Copyright (C) 2024 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef QSPI_LLD_H_
#define QSPI_LLD_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <drivers/hw_include/cslr_qspi.h>
#include <drivers/edma.h>
#include <stdbool.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
typedef EDMA_Handle QSPI_DmaHandle;
 
typedef struct QSPI_EdmaParams_s *QSPI_DmaChConfig;
 
#define QSPI_CS0  (0U)
#define QSPI_CS1  (1U)
#define QSPI_CS2  (2U)
#define QSPI_CS3  (3U)
 
#define QSPI_NOT_IN_USE(x) (void) 0
 
#define QSPI_LLD_CMD_INVALID_ADDR    (0xFFFFFFFFU)
 
#define QSPI_RX_LINES_SINGLE    (0U)
#define QSPI_RX_LINES_DUAL      (1U)
#define QSPI_RX_LINES_QUAD      (2U)
 
#define QSPI_FF_POL0_PHA0   ((CSL_QSPI_SPI_DC_REG_CKPH0_CKP_0_SHIFT_OUT_FALLING_EDGE \
                            << CSL_QSPI_SPI_DC_REG_CKPH0_SHIFT) |                    \
                            (CSL_QSPI_SPI_DC_REG_CKP0_DATA_INACTIVE <<               \
                            CSL_QSPI_SPI_DC_REG_CKP0_SHIFT))
#define QSPI_FF_POL0_PHA1   ((CSL_QSPI_SPI_DC_REG_CKPH0_CKP_0_SHIFT_OUT_RISING_EDGE  \
                            << CSL_QSPI_SPI_DC_REG_CKPH0_SHIFT) |                    \
                            (CSL_QSPI_SPI_DC_REG_CKP0_DATA_INACTIVE <<               \
                            CSL_QSPI_SPI_DC_REG_CKP0_SHIFT))
#define QSPI_FF_POL1_PHA0   ((CSL_QSPI_SPI_DC_REG_CKPH0_CKP_1_SHIFT_OUT_RISING_EDGE  \
                            << CSL_QSPI_SPI_DC_REG_CKPH0_SHIFT) |                    \
                            (CSL_QSPI_SPI_DC_REG_CKP0_DATA_ACTIVE <<                 \
                            CSL_QSPI_SPI_DC_REG_CKP0_SHIFT))
#define QSPI_FF_POL1_PHA1   ((CSL_QSPI_SPI_DC_REG_CKPH0_CKP_1_SHIFT_OUT_FALLING_EDGE \
                            << CSL_QSPI_SPI_DC_REG_CKPH0_SHIFT) |                    \
                            (CSL_QSPI_SPI_DC_REG_CKP0_DATA_ACTIVE <<                 \
                            CSL_QSPI_SPI_DC_REG_CKP0_SHIFT))
 
#define QSPI_CS_POL_ACTIVE_LOW    (CSL_QSPI_SPI_DC_REG_CSP0_ACTIVE_LOW)
#define QSPI_CS_POL_ACTIVE_HIGH   (CSL_QSPI_SPI_DC_REG_CSP0_ACTIVE_HIGH)
 
#define QSPI_DATA_DELAY_0   (CSL_QSPI_SPI_DC_REG_DD0_CS_TO_DATA_DELAY_0)
#define QSPI_DATA_DELAY_1   (CSL_QSPI_SPI_DC_REG_DD0_CS_TO_DATA_DELAY_1)
#define QSPI_DATA_DELAY_2   (CSL_QSPI_SPI_DC_REG_DD0_CS_TO_DATA_DELAY_2)
#define QSPI_DATA_DELAY_3   (CSL_QSPI_SPI_DC_REG_DD0_CS_TO_DATA_DELAY_3)
 
#define QSPI_MEM_MAP_PORT_SEL_CFG_PORT          \
                                (CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_CFG_PORT)
#define QSPI_MEM_MAP_PORT_SEL_MEM_MAP_PORT      \
                                (CSL_QSPI_SPI_SWITCH_REG_MMPT_S_SEL_MM_PORT)
 
#define QSPI_MAX_WORD_LENGTH     (128U)
 
#define QSPI_SYSTEM_SUCCESS     ((int32_t )0)
 
#define QSPI_SYSTEM_FAILURE     ((int32_t)-1)
 
#define QSPI_TIMEOUT            ((int32_t)-2)
 
#define QSPI_LLD_INVALID_PARAM  ((int32_t)-3)
 
#define QSPI_BUSY               ((int32_t)-4)
 
#define QSPI_INVALID_STATE      ((int32_t)-5)
 
#define QSPI_STATE_RESET        (0U)
 
#define QSPI_STATE_READY        (1U)
 
#define QSPI_STATE_BUSY         (2U)
 
#define QSPI_STATE_ERROR        (3U)
 
#define QSPI_STATE_IDLE                 (0U)
 
#define QSPI_STATE_ADDRESS_WRITE        (1U)
 
#define QSPI_STATE_DATA_WRITE           (2U)
 
#define QSPI_STATE_DATA_READ            (3U)
 
#define QSPI_STATE_BLOCK                (4U)
 
#define QSPI_STATE_NON_BLOCK            (5U)
 
/* ========================================================================== */
/*                      Function pointers Declarations                        */
/* ========================================================================== */
 
typedef uint32_t (*QSPI_Clock_getTicks)(void);
 
typedef uint32_t (*QSPI_Clock_usecToTicks)(uint64_t usecs);
 
/* Type definition for the callback function*/
typedef void (*QSPI_lld_InterruptCallback)(void* args);
 
typedef void (*QSPI_lld_dma_readCompleteCallback)(void* args);
 
/* ========================================================================== */
/*                             Structure Definitions                          */
/* ========================================================================== */
typedef struct
{
    uint32_t            count;
    uint32_t            dataLen;
    void                *buf;
    uint32_t            addrOffset;
    bool                status;
    bool                readWriteFlag;
    uint32_t            cmdRegVal;
    uint32_t            currentIndex;
    uint8_t             cmd;
    uint8_t             numAddrBytes;
    uint32_t            wlen;
    uint32_t            state;
} QSPILLD_Transaction,*QSPILLD_TransactionHandle;
 
typedef struct
{
    uint8_t             cmd;
    uint32_t            cmdAddr;
    uint8_t             numAddrBytes;
    void                *dataBuf;
    uint32_t            dataLen;
} QSPILLD_WriteCmdParams;
 
typedef struct
{
    uint32_t            memMapBaseAddr;
    uint32_t            inputClkFreq;
    uint32_t            qspiClockDiv;
    uint32_t            chipSelect;
    uint32_t            csPol;
    uint32_t            frmFmt;
    uint32_t            dataDelay;
    uint32_t            wrdLen;
    uint32_t            rxLines;
    QSPI_DmaHandle      qspiDmaHandle;
    QSPI_DmaChConfig    qspiDmaChConfig;
    uint32_t            intrNum;
    bool                intrEnable;
    bool                wordIntr;
    bool                frameIntr;
    uint8_t             intrPriority;
    bool                dmaEnable;
    QSPI_Clock_getTicks Clock_getTicks;
    QSPI_Clock_usecToTicks Clock_usecToTicks;
} QSPILLD_InitObject, *QSPILLD_InitHandle;
 
typedef struct
{
    /*
     * SOC configuration
     */
    uint32_t            baseAddr;
    uint8_t             readCmd;
    uint8_t             writeCmd;
    uint32_t            frmLength;
    uint32_t            numAddrBytes;
    uint32_t            numDummyBits;
    QSPILLD_InitHandle  hQspiInit;
    uint32_t            state;
    void*               args;
    QSPILLD_Transaction        *transaction;
    QSPILLD_Transaction        trans;
    QSPI_lld_InterruptCallback interruptCallback;
    /* Interrupt Callback to be registered by the application*/
    QSPI_lld_dma_readCompleteCallback readCompleteCallback;
    /* DMA Readcallback function*/
} QSPILLD_Object, *QSPILLD_Handle;
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
int32_t QSPI_lld_init(QSPILLD_Handle hQspi);
 
int32_t QSPI_lld_initDma(QSPILLD_Handle hQspi);
 
int32_t QSPI_lld_deInit(QSPILLD_Handle hQspi);
 
int32_t QSPI_lld_deInitDma(QSPILLD_Handle hQspi);
 
int32_t QSPI_lld_readCmd(QSPILLD_Handle hQspi, QSPILLD_WriteCmdParams *writeMsg);
 
int32_t QSPI_lld_readCmdIntr(QSPILLD_Handle hQspi,const QSPILLD_WriteCmdParams *msg);
 
int32_t QSPI_lld_writeCmd(QSPILLD_Handle hQspi, QSPILLD_WriteCmdParams *writeMsg);
 
int32_t QSPI_lld_writeCmdIntr(QSPILLD_Handle hQspi, const QSPILLD_WriteCmdParams *msg);
 
int32_t QSPI_lld_read(QSPILLD_Handle hQspi, uint32_t count, void* rxBuf, uint32_t addrOffset, uint32_t timeout);
 
int32_t QSPI_lld_readDma(QSPILLD_Handle hQspi, uint32_t count, void* rxBuf, uint32_t addrOffset, uint32_t timeout);
 
/* API's used by flash driver */
 
int32_t QSPI_lld_setWriteCmd(QSPILLD_Handle hQspi, uint8_t command);
 
int32_t QSPI_lld_setReadCmd(QSPILLD_Handle hQspi, uint8_t command);
 
int32_t QSPI_lld_setAddressByteCount(QSPILLD_Handle hQspi, uint32_t count);
 
int32_t QSPI_lld_setDummyBitCount(QSPILLD_Handle hQspi, uint32_t count);
 
int32_t QSPI_lld_setMemAddrSpace(QSPILLD_Handle hQspi, uint32_t memMappedPortSwitch);
 
int32_t QSPI_lld_setRxLines(QSPILLD_Handle hQspi, uint32_t rxLines);
 
int32_t QSPI_lld_setPreScaler(QSPILLD_Handle hQspi, uint32_t clkDividerVal);
 
int32_t QSPI_lld_getInputClk(QSPILLD_Handle hQspi, uint32_t* inputClk);
 
uint32_t QSPI_lld_getRxLines(QSPILLD_Handle hQspi);
 
void QSPI_lld_isr(void* args);
 
void QSPI_lld_readCompleteCallback(void* args);
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* #ifndef QSPI_LLD_H_ */