For more details and example usage, see SOC
Sub Modules | |
| APIs for SOC Reset and Clock Functions | |
| APIs for SOC Xbars | |
Functions | |
| static int32_t | MCSPI_lld_isBaseAddrValid (uint32_t baseAddr) | 
| API to validate MCSPI base address.  More... | |
| static int32_t | MMCSD_lld_isBaseAddrValid (uint32_t baseAddr) | 
| API to validate MMCSD base addresses.  More... | |
| int32_t | SOC_moduleClockEnable (uint32_t moduleId, uint32_t enable) | 
| Enable clock to specified module.  More... | |
| int32_t | SOC_moduleSetClockFrequency (uint32_t moduleId, uint32_t clkId, uint64_t clkRate) | 
| Set module clock to specified frequency.  More... | |
| const char * | SOC_getCoreName (uint16_t coreId) | 
| Convert a core ID to a user readable name.  More... | |
| uint64_t | SOC_getSelfCpuClk (void) | 
| Get the clock frequency in Hz of the CPU on which the driver is running.  More... | |
| void | SOC_controlModuleLockMMR (uint32_t domainId, uint32_t partition) | 
| Lock control module partition to prevent writes into control MMRs.  More... | |
| void | SOC_controlModuleUnlockMMR (uint32_t domainId, uint32_t partition) | 
| Unlock control module partition to allow writes into control MMRs.  More... | |
| void | SOC_setEpwmTbClk (uint32_t epwmInstance, uint32_t enable) | 
| Enable or disable ePWM time base clock from Control MMR.  More... | |
| void | SOC_setMultipleEpwmTbClk (uint32_t epwmMask, uint32_t enable) | 
| Enable or disable Multiple ePWM time base clock from Control MMR.  More... | |
| void | SOC_enableAdcReference (uint32_t adcInstance) | 
| Enable ADC references by writing to Control MMR.  More... | |
| void | SOC_enableAdcInternalReference (uint32_t adcInstance, uint32_t enable) | 
| Enables the ADC internal reference.  More... | |
| void | SOC_enableAdcReferenceMonitor (uint32_t adcInstance, uint32_t enable) | 
| Enable ADC reference Monitors by writing to Control MMR.  More... | |
| uint32_t | SOC_getAdcReferenceStatus (uint32_t adcInstance) | 
| Gets the Reference status.  More... | |
| void | SOC_setEpwmGroup (uint32_t epwmInstance, uint32_t group) | 
| Configure the ePWM group.  More... | |
| void | SOC_selectSdfm1Clk0Source (uint8_t source) | 
| Select the SDFM1 CLK0 source.  More... | |
| void | SOC_gateEpwmClock (uint32_t epwmInstance) | 
| Gate the ePWM clock.  More... | |
| void | SOC_ungateEpwmClock (uint32_t epwmInstance) | 
| Ungate the ePWM clock.  More... | |
| void | SOC_gateFsitxClock (uint32_t fsitxInstance) | 
| Gate the FSI-TX clock.  More... | |
| void | SOC_gateFsirxClock (uint32_t fsirxInstance) | 
| Gate the FSI-RX clock.  More... | |
| void | SOC_gateCmpssaClock (uint32_t cmpssaInstance) | 
| Gate the CMPSS-A clock.  More... | |
| void | SOC_ungateCmpssaClock (uint32_t cmpssaInstance) | 
| Ungate the CMPSS-A clock.  More... | |
| void | SOC_gateCmpssbClock (uint32_t cmpssbInstance) | 
| Gate the CMPSS-B clock.  More... | |
| void | SOC_ungateCmpssbClock (uint32_t cmpssbInstance) | 
| Ungate the CMPSS-B clock.  More... | |
| void | SOC_gateEcapClock (uint32_t ecapInstance) | 
| Gate the ECAP clock.  More... | |
| void | SOC_ungateEcapClock (uint32_t ecapInstance) | 
| Ungate the ECAP clock.  More... | |
| void | SOC_gateEqepClock (uint32_t eqepInstance) | 
| Gate the EQEP clock.  More... | |
| void | SOC_ungateEqepClock (uint32_t eqepInstance) | 
| Ungate the EQEP clock.  More... | |
| void | SOC_gateSdfmClock (uint32_t sdfmInstance) | 
| Gate the SDFM clock.  More... | |
| void | SOC_ungateSdfmClock (uint32_t sdfmInstance) | 
| Ungate the SDFM clock.  More... | |
| void | SOC_gateDacClock (void) | 
| Gate the DAC clock.  More... | |
| void | SOC_ungateDacClock (void) | 
| Ungate the DAC clock.  More... | |
| void | SOC_gateAdcClock (uint32_t adcInstance) | 
| Gate the ADC clock.  More... | |
| void | SOC_ungateAdcClock (uint32_t adcInstance) | 
| ungate the ADC clock  More... | |
| void | SOC_gateOttoClock (uint32_t ottoInstance) | 
| Gate the OTTO clock.  More... | |
| void | SOC_ungateOttoClock (uint32_t ottoInstance) | 
| Ungate the OTTO clock.  More... | |
| void | SOC_gateSdfmPllClock (uint32_t sdfmInstance) | 
| Gate the SDFM PLL clock.  More... | |
| void | SOC_ungateSdfmPllClock (uint32_t sdfmInstance) | 
| Ungate the SDFM PLL clock.  More... | |
| void | SOC_gateFsiPllClock (uint32_t fsiInstance) | 
| Gate the FSI-TX PLL clock.  More... | |
| void | SOC_generateEpwmReset (uint32_t ePWMInstance) | 
| Generate ePWM reset.  More... | |
| void | SOC_generateFsiTxReset (uint32_t fsitxInstance) | 
| Generate FSI-TX reset.  More... | |
| void | SOC_generateFsiRxReset (uint32_t fsirxInstance) | 
| Generate FSI-RX reset.  More... | |
| void | SOC_generateCmpssaReset (uint32_t cmpssaInstance) | 
| Generate CMPSS-A reset.  More... | |
| void | SOC_generateCmpssbReset (uint32_t cmpssbInstance) | 
| Generate CMPSS-B reset.  More... | |
| void | SOC_generateEcapReset (uint32_t ecapInstance) | 
| Generate ECAP reset.  More... | |
| void | SOC_generateEqepReset (uint32_t eqepInstance) | 
| Generate EQEP reset.  More... | |
| void | SOC_generateSdfmReset (uint32_t sdfmInstance) | 
| Generate SDFM reset.  More... | |
| void | SOC_generateDacReset (void) | 
| Generate DAC reset.  More... | |
| void | SOC_generateAdcReset (uint32_t adcInstance) | 
| Generate ADC reset.  More... | |
| void | Soc_enableEPWMHalt (uint32_t epwmInstance) | 
| Halt EPWM with corresponding cPU.  More... | |
| void | Soc_disableEPWMHalt (uint32_t epwmInstance) | 
| Halt EPWM with corresponding cPU.  More... | |
| void | Soc_enableECAPHalt (uint32_t ecapInstance) | 
| Halt ECAP with corresponding cPU.  More... | |
| void | Soc_disableECAPHalt (uint32_t ecapInstance) | 
| Halt ECAP with corresponding cPU.  More... | |
| void | SOC_generateOttoReset (uint32_t ottoInstance) | 
| Generate OTTO reset.  More... | |
| void | SOC_selectIcssGpiMux (uint8_t pru_instance, uint32_t mask) | 
| Selection of ICSS GPI MUX.  More... | |
| void | SOC_setResetCPSWBit () | 
| Setting CPSW hard reset Bit.  More... | |
| void | SOC_clearResetCPSWBit () | 
| Clearing CPSW hard reset bit.  More... | |
| uint64_t | SOC_virtToPhy (void *virtAddr) | 
| SOC Virtual (CPU) to Physical address translation function.  More... | |
| void * | SOC_phyToVirt (uint64_t phyAddr) | 
| Physical to Virtual (CPU) address translation function.  More... | |
| void | SOC_configSlewRate (uint32_t baseAddr, uint32_t bankNum, uint32_t groupNum, uint32_t samplePeriod) | 
| Configure GPIO pin Slew rate.  More... | |
| static int32_t | UART_IsBaseAddrValid (uint32_t baseAddr) | 
| Macro to validate UART base address.  More... | |
| uint32_t | SOC_getFlashDataBaseAddr (void) | 
| This function gets the SOC mapped data base address of the flash.  More... | |
Macros | |
| #define | MSS_CTRL_PARTITION0 (1) | 
| #define | TOP_CTRL_PARTITION0 (2) | 
| #define | CONTROLSS_CTRL_PARTITION0 (3) | 
| #define | MSS_RCM_PARTITION0 (4) | 
| #define | TOP_RCM_PARTITION0 (5) | 
| #define | KICK_LOCK_VAL (0x00000000U) | 
| #define | KICK0_UNLOCK_VAL (0x01234567U) | 
| #define | KICK1_UNLOCK_VAL (0x0FEDCBA8U) | 
| #define | IS_I2C_BASE_ADDR_VALID(baseAddr) | 
| Macro to check if the I2C base address is valid.  More... | |
| #define | IS_QSPI_BASE_ADDR_VALID(baseAddr) (baseAddr == CSL_QSPI0_U_BASE) | 
| Macro to check if the QSPI base address is valid.  More... | |
| #define | IS_QSPI_MEMORY_MAP_ADDR_VALID(baseAddr) | 
| Macro to check if the QSPI Memory Mapped address is valid.  More... | |
SOC Domain ID | |
| #define | SOC_DOMAIN_ID_MAIN (0U) | 
| #define SOC_DOMAIN_ID_MAIN (0U) | 
| #define MSS_CTRL_PARTITION0 (1) | 
| #define TOP_CTRL_PARTITION0 (2) | 
| #define CONTROLSS_CTRL_PARTITION0 (3) | 
| #define MSS_RCM_PARTITION0 (4) | 
| #define TOP_RCM_PARTITION0 (5) | 
| #define KICK_LOCK_VAL (0x00000000U) | 
| #define KICK0_UNLOCK_VAL (0x01234567U) | 
| #define KICK1_UNLOCK_VAL (0x0FEDCBA8U) | 
| #define IS_I2C_BASE_ADDR_VALID | ( | baseAddr | ) | 
Macro to check if the I2C base address is valid.
| #define IS_QSPI_BASE_ADDR_VALID | ( | baseAddr | ) | (baseAddr == CSL_QSPI0_U_BASE) | 
Macro to check if the QSPI base address is valid.
| #define IS_QSPI_MEMORY_MAP_ADDR_VALID | ( | baseAddr | ) | 
Macro to check if the QSPI Memory Mapped address is valid.
      
  | 
  inlinestatic | 
API to validate MCSPI base address.
      
  | 
  inlinestatic | 
API to validate MMCSD base addresses.
| int32_t SOC_moduleClockEnable | ( | uint32_t | moduleId, | 
| uint32_t | enable | ||
| ) | 
Enable clock to specified module.
| moduleId | [in] see SOC_RcmPeripheralId for list of module ID's | 
| enable | [in] 1: enable clock to the module, 0: disable clock to the module | 
| int32_t SOC_moduleSetClockFrequency | ( | uint32_t | moduleId, | 
| uint32_t | clkId, | ||
| uint64_t | clkRate | ||
| ) | 
Set module clock to specified frequency.
| moduleId | [in] see SOC_RcmPeripheralId for list of module ID's | 
| clkId | [in] see SOC_RcmPeripheralClockSource for list of clocks | 
| clkRate | [in] Frequency to set in Hz | 
| const char* SOC_getCoreName | ( | uint16_t | coreId | ) | 
Convert a core ID to a user readable name.
| coreId | [in] see CSL_CoreID | 
| uint64_t SOC_getSelfCpuClk | ( | void | ) | 
Get the clock frequency in Hz of the CPU on which the driver is running.
| void SOC_controlModuleLockMMR | ( | uint32_t | domainId, | 
| uint32_t | partition | ||
| ) | 
Lock control module partition to prevent writes into control MMRs.
| domainId | [in] See SOC_DomainId_t | 
| partition | [in] Partition number to unlock | 
| void SOC_controlModuleUnlockMMR | ( | uint32_t | domainId, | 
| uint32_t | partition | ||
| ) | 
Unlock control module partition to allow writes into control MMRs.
| domainId | [in] See SOC_DomainId_t | 
| partition | [in] Partition number to unlock | 
| void SOC_setEpwmTbClk | ( | uint32_t | epwmInstance, | 
| uint32_t | enable | ||
| ) | 
Enable or disable ePWM time base clock from Control MMR.
| epwmInstance | [in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)] | 
| enable | [in] TRUE to enable and FALSE to disable | 
| void SOC_setMultipleEpwmTbClk | ( | uint32_t | epwmMask, | 
| uint32_t | enable | ||
| ) | 
Enable or disable Multiple ePWM time base clock from Control MMR.
| epwmMask | [in] ePWM instance Mask [1 - CSL_CONTROLSS_CTRL_EPWM_CLKSYNC_BIT_MAX] | 
| enable | [in] TRUE to enable and FALSE to disable | 
| void SOC_enableAdcReference | ( | uint32_t | adcInstance | ) | 
Enable ADC references by writing to Control MMR.
| adcInstance | [in] ADC instance number [0 - (CSL_ADC_PER_CNT-1)] | 
| void SOC_enableAdcInternalReference | ( | uint32_t | adcInstance, | 
| uint32_t | enable | ||
| ) | 
Enables the ADC internal reference.
| adcInstance | [in] ADC instance number [0 - (CSL_ADC_PER_CNT-1)] | 
| enable | [in] TRUE to enable internal reference - FALSE to disable. | 
| void SOC_enableAdcReferenceMonitor | ( | uint32_t | adcInstance, | 
| uint32_t | enable | ||
| ) | 
Enable ADC reference Monitors by writing to Control MMR.
| adcInstance | [in] ADC instance number [0 - (CSL_ADC_PER_CNT-1)] | 
| enable | [in] TRUE to enable internal reference Monitor - FALSE to disable. | 
| uint32_t SOC_getAdcReferenceStatus | ( | uint32_t | adcInstance | ) | 
Gets the Reference status.
| adcInstance | [in] ADC instance number [0 - (CSL_ADC_PER_CNT-1)] | 
| void SOC_setEpwmGroup | ( | uint32_t | epwmInstance, | 
| uint32_t | group | ||
| ) | 
Configure the ePWM group.
| epwmInstance | [in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)] | 
| group | [in] The group for this ePWM instance [0 - 3] | 
| void SOC_selectSdfm1Clk0Source | ( | uint8_t | source | ) | 
Select the SDFM1 CLK0 source.
| source | [in] Source of SDFM1 CLK0. 0: source is SDFM1 CK0 from Pinmux. 1: source is SDFM0 CK0 from Pinmux | 
| void SOC_gateEpwmClock | ( | uint32_t | epwmInstance | ) | 
Gate the ePWM clock.
| epwmInstance | [in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)] | 
| void SOC_ungateEpwmClock | ( | uint32_t | epwmInstance | ) | 
Ungate the ePWM clock.
| epwmInstance | [in] ePWM instance number [0 - (CSL_EPWM_PER_CNT-1)] | 
| void SOC_gateFsitxClock | ( | uint32_t | fsitxInstance | ) | 
Gate the FSI-TX clock.
| fsitxInstance | [in] FSITX instance number [0 - 3] | 
| void SOC_gateFsirxClock | ( | uint32_t | fsirxInstance | ) | 
Gate the FSI-RX clock.
| fsirxInstance | [in] FSIRX instance number [0 - 3] | 
| void SOC_gateCmpssaClock | ( | uint32_t | cmpssaInstance | ) | 
Gate the CMPSS-A clock.
| cmpssaInstance | [in] CMPSS-A instance number [0 - 9] | 
| void SOC_ungateCmpssaClock | ( | uint32_t | cmpssaInstance | ) | 
Ungate the CMPSS-A clock.
| cmpssaInstance | [in] CMPSS-A instance number [0 - 9] | 
| void SOC_gateCmpssbClock | ( | uint32_t | cmpssbInstance | ) | 
Gate the CMPSS-B clock.
| cmpssbInstance | [in] CMPSS-B instance number [0 - 9] | 
| void SOC_ungateCmpssbClock | ( | uint32_t | cmpssbInstance | ) | 
Ungate the CMPSS-B clock.
| cmpssbInstance | [in] CMPSS-B instance number [0 - 9] | 
| void SOC_gateEcapClock | ( | uint32_t | ecapInstance | ) | 
Gate the ECAP clock.
| ecapInstance | [in] ECAP instance number [0 - 9] | 
| void SOC_ungateEcapClock | ( | uint32_t | ecapInstance | ) | 
Ungate the ECAP clock.
| ecapInstance | [in] ECAP instance number [0 - 9] | 
| void SOC_gateEqepClock | ( | uint32_t | eqepInstance | ) | 
Gate the EQEP clock.
| eqepInstance | [in] EQEP instance number [0 - 2] | 
| void SOC_ungateEqepClock | ( | uint32_t | eqepInstance | ) | 
Ungate the EQEP clock.
| eqepInstance | [in] EQEP instance number [0 - 2] | 
| void SOC_gateSdfmClock | ( | uint32_t | sdfmInstance | ) | 
Gate the SDFM clock.
| sdfmInstance | [in] SDFM instance number [0 - 1] | 
| void SOC_ungateSdfmClock | ( | uint32_t | sdfmInstance | ) | 
Ungate the SDFM clock.
| sdfmInstance | [in] SDFM instance number [0 - 1] | 
| void SOC_gateDacClock | ( | void | ) | 
Gate the DAC clock.
| void SOC_ungateDacClock | ( | void | ) | 
Ungate the DAC clock.
| void SOC_gateAdcClock | ( | uint32_t | adcInstance | ) | 
Gate the ADC clock.
| adcInstance | [in] ADC instance number [0 - 4] | 
| void SOC_ungateAdcClock | ( | uint32_t | adcInstance | ) | 
ungate the ADC clock
| adcInstance | [in] ADC instance number [0 - 4] | 
| void SOC_gateOttoClock | ( | uint32_t | ottoInstance | ) | 
Gate the OTTO clock.
| ottoInstance | [in] OTTO instance number [0 - 3] | 
| void SOC_ungateOttoClock | ( | uint32_t | ottoInstance | ) | 
Ungate the OTTO clock.
| ottoInstance | [in] OTTO instance number [0 - 3] | 
| void SOC_gateSdfmPllClock | ( | uint32_t | sdfmInstance | ) | 
Gate the SDFM PLL clock.
| sdfmInstance | [in] SDFM instance number [0 - 1] | 
| void SOC_ungateSdfmPllClock | ( | uint32_t | sdfmInstance | ) | 
Ungate the SDFM PLL clock.
| sdfmInstance | [in] SDFM instance number [0 - 1] | 
| void SOC_gateFsiPllClock | ( | uint32_t | fsiInstance | ) | 
Gate the FSI-TX PLL clock.
| fsiInstance | [in] FSI instance number [0 - 3] | 
| void SOC_generateEpwmReset | ( | uint32_t | ePWMInstance | ) | 
Generate ePWM reset.
| ePWMInstance | [in] ePWM instance number [0 - 31] | 
| void SOC_generateFsiTxReset | ( | uint32_t | fsitxInstance | ) | 
Generate FSI-TX reset.
| fsitxInstance | [in] FSI instance number [0 - 3] | 
| void SOC_generateFsiRxReset | ( | uint32_t | fsirxInstance | ) | 
Generate FSI-RX reset.
| fsirxInstance | [in] FSI instance number [0 - 3] | 
| void SOC_generateCmpssaReset | ( | uint32_t | cmpssaInstance | ) | 
Generate CMPSS-A reset.
| cmpssaInstance | [in] CMPSS-A instance number [0 - 9] | 
| void SOC_generateCmpssbReset | ( | uint32_t | cmpssbInstance | ) | 
Generate CMPSS-B reset.
| cmpssbInstance | [in] CMPSS-B instance number [0 - 9] | 
| void SOC_generateEcapReset | ( | uint32_t | ecapInstance | ) | 
Generate ECAP reset.
| ecapInstance | [in] ECAP instance number [0 - 9] | 
| void SOC_generateEqepReset | ( | uint32_t | eqepInstance | ) | 
Generate EQEP reset.
| eqepInstance | [in] EQEP instance number [0 - 2] | 
| void SOC_generateSdfmReset | ( | uint32_t | sdfmInstance | ) | 
Generate SDFM reset.
| sdfmInstance | [in] SDFM instance number [0 - 1] | 
| void SOC_generateDacReset | ( | void | ) | 
Generate DAC reset.
| void SOC_generateAdcReset | ( | uint32_t | adcInstance | ) | 
Generate ADC reset.
| adcInstance | [in] ADC instance number [0 - 4] | 
| void Soc_enableEPWMHalt | ( | uint32_t | epwmInstance | ) | 
Halt EPWM with corresponding cPU.
| epwmInstance | [in] EPWM instance number [0 - 31] | 
| void Soc_disableEPWMHalt | ( | uint32_t | epwmInstance | ) | 
Halt EPWM with corresponding cPU.
| epwmInstance | [in] EPWM instance number [0 - 31] | 
| void Soc_enableECAPHalt | ( | uint32_t | ecapInstance | ) | 
Halt ECAP with corresponding cPU.
| ecapInstance | [in] ECAP instance number [0 - 10] | 
| void Soc_disableECAPHalt | ( | uint32_t | ecapInstance | ) | 
Halt ECAP with corresponding cPU.
| ecapInstance | [in] ECAP instance number [0 - 10] | 
| void SOC_generateOttoReset | ( | uint32_t | ottoInstance | ) | 
Generate OTTO reset.
| ottoInstance | [in] OTTO instance number [0 - 3] | 
| void SOC_selectIcssGpiMux | ( | uint8_t | pru_instance, | 
| uint32_t | mask | ||
| ) | 
Selection of ICSS GPI MUX.
| pru_instance | [in] PRU instance number [0 - 1] | 
| mask | [in] Bitwise selection of ICSSM GPI source. GPI or PWMXBar select for ICSSM port 0/1. 0-GPI, 1-PWMXBAR | 
| void SOC_setResetCPSWBit | ( | ) | 
Setting CPSW hard reset Bit.
| void SOC_clearResetCPSWBit | ( | ) | 
Clearing CPSW hard reset bit.
| uint64_t SOC_virtToPhy | ( | void * | virtAddr | ) | 
SOC Virtual (CPU) to Physical address translation function.
| virtAddr | [IN] Virtual/CPU address | 
| void* SOC_phyToVirt | ( | uint64_t | phyAddr | ) | 
Physical to Virtual (CPU) address translation function.
| phyAddr | [IN] Physical address | 
| void SOC_configSlewRate | ( | uint32_t | baseAddr, | 
| uint32_t | bankNum, | ||
| uint32_t | groupNum, | ||
| uint32_t | samplePeriod | ||
| ) | 
Configure GPIO pin Slew rate.
| baseAddr | Base Address of IOMUX registers (CSL_IOMUX_U_BASE) | 
| bankNum | Bank number of GPIO Pin | 
| groupNum | Group Number where one group register applies to 8 GPIO's. So, one bank will be in two groups. For lower half, pass group number as 0 and for upper half pass 1. | 
| samplePeriod | Sampling period in units of clock cycles. | 
      
  | 
  inlinestatic | 
Macro to validate UART base address.
API to validate UART base address
| uint32_t SOC_getFlashDataBaseAddr | ( | void | ) | 
This function gets the SOC mapped data base address of the flash.