SDL PBIST

Table of Contents

• Introduction
  • Use Cases
• Supported Combinations
• Steps to Run the Example
• See Also
• Sample Output

Introduction

This example demonstrates the usage of the PBIST module. The example shows how to setup and use the PBIST controller. The example configures the algorithm and memory group. Example also prints the time taken for test execution.

Use Cases

Use Case	Description
UC-1	Configure wrong combination of algorithm and memory group.
UC-2	Configure correct combination of algorithm and memory group.

Supported Combinations

Parameter	Value
CPU + OS	r5fss0-0 nortos
Toolchain	ti-arm-clang
Board	am263x-cc
Example folder	examples/sdl/pbist/pbist_mcu/

Steps to Run the Example

• When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

See Also

PBIST

Sample Output

Shown below is a sample output when the application is run,

[Cortex_R5_0]
PBIST Application
 
 Starting PBIST failure insertion test on TOP PBIST
 PBIST failure Insertion test complete for TOP BIST
PBIST Failure Insertion Test completed in 47 micro secs
 
 Starting PBIST test on TOP PBIST
 PBIST complete for R5 STC
 PBIST complete for R51 STC
 PBIST complete for PBISTROM
 PBIST complete for CPSW
 PBIST complete for ICSSM
 PBIST complete for MBOX
 PBIST complete for MCAN
 PBIST complete for TPCC
 PBIST complete for MSS_L2_1
 PBIST complete for MSS_L2_2
 PBIST complete for MSS_L2_3
 PBIST complete for VIM1 R5SS0
 PBIST complete for VIM0 R5SS1
 PBIST complete for VIM1 R5SS1
 PBIST complete for R5SS1 RAM
 PBIST complete for MSS CR5B ATCM0
 PBIST complete for MSS CR5B ATCM1
 PBIST complete for MSS CR5B BTCM0
 PBIST complete for MSS CR5B BTCM1
 
 All tests have passed.
 
 [Cortex_R5_2]
  PBIST Application
 
  Starting PBIST failure insertion test on TOP PBIST
  PBIST failure Insertion test complete for TOP BIST
 PBIST Failure Insertion Test completed in 0 micro secs
 
  Starting PBIST test on TOP PBIST
  PBIST complete for  VIM0 R5SS0
  PBIST complete for MSS_L2_0
  PBIST complete for R5SS0 RAM
  PBIST complete for CR5A ROM0
  PBIST complete for TRACE
  PBIST complete for MMCH0
  PBIST complete for MSS CR5A ATCM0
  PBIST complete for MSS CR5A ATCM1
  PBIST complete for MSS CR5A BTCM0
  PBIST complete for MSS CR5A BTCM1
 
  All tests have passed.