Introduction

This file containing the GPMC API.

The GPMC header file should be included in an application as follows:

#include <drivers/gpmc.h>

Data Structures
struct	GPMC_nandCmdParams
	Data structure to set NAND command parameters. More...

struct	GPMC_Transaction
	Data structure to set transaction type parameters. More...

struct	GPMC_Params
	GPMC driver instance parameters. More...

struct	GPMC_AddrRegion
	GPMC Address Region. More...

struct	GPMC_Object
	GPMC driver object. More...

struct	GPMC_timingParams
	GPMC timing parameters. More...

struct	GPMC_HwAttrs
	GPMC instance attributes. More...

struct	GPMC_Config
	GPMC Driver configuration structure. More...

Functions
static void	GPMC_Params_init (GPMC_Params *params)
	Function to initialize the GPMC_Params struct to its defaults. More...

void	GPMC_init (void)
	This function initializes the GPMC module. More...

void	GPMC_deinit (void)
	This function de-initializes the GPMC module. More...

GPMC_Handle	GPMC_open (uint32_t index, const GPMC_Params *prms)
	This function opens a given GPMC peripheral. More...

void	GPMC_close (GPMC_Handle handle)
	Function to close a GPMC peripheral specified by the GPMC handle. More...

uint32_t	GPMC_getInputClk (GPMC_Handle handle)
	This function returns the input clk frequency GPMC was programmed at. More...

GPMC_Handle	GPMC_getHandle (uint32_t driverInstanceIndex)
	This function returns the handle of an open GPMC Instance from the instance index. More...

void	GPMC_writeNandCommandParamsInit (GPMC_nandCmdParams *cmdParams)
	Function to initialise GPMC_nandCmdParams structure to default values. More...

int32_t	GPMC_writeNandCommand (GPMC_Handle handle, GPMC_nandCmdParams *cmdParams)
	Function to write NAND command parameters. More...

void	GPMC_transactionInit (GPMC_Transaction *trans)
	Function to initialise GPMC_Transaction structure to default values. More...

int32_t	GPMC_nandReadData (GPMC_Handle handle, GPMC_Transaction *trans)
	Function to read data from NAND flash using DMA or CPU prefetch/post write engine. More...

int32_t	GPMC_nandWriteData (GPMC_Handle handle, GPMC_Transaction *trans)
	Function to write data to NANDflash using CPU prefetch/post write engine. More...

int32_t	GPMC_setDeviceSize (GPMC_Handle handle)
	Function to set device width for GPMC instance connected to external device. More...

int32_t	GPMC_setDeviceType (GPMC_Handle handle)
	Function to set device type (NANDLIKE OR NORLIKE) for GPMC instance connected to external device. More...

int32_t	GPMC_configureTimingParameters (GPMC_Handle handle)
	Function to configure GPMC timing parameters. More...

int32_t	GPMC_configureTimingParametersPsram (GPMC_Handle handle)
	Function to configure GPMC timing parameters for PSRAM/NOR Devices. More...

int32_t	GPMC_eccValueSizeSet (GPMC_Handle handle, uint32_t eccSize, uint32_t eccSizeVal)
	Function to set ECC used and unused bytes size in nibbles. More...

int32_t	GPMC_eccBchConfigureElm (GPMC_Handle handle, uint8_t numSectors)
	Function to configure ELM module for error correction. More...

int32_t	GPMC_eccEngineBCHConfig (GPMC_Handle handle, uint32_t eccSteps)
	Function to configure GPMC ECC engine for BCH algorithm. More...

int32_t	GPMC_eccEngineEnable (GPMC_Handle handle)
	Function to enable GPMC ECC engine. More...

void	GPMC_eccResultRegisterClear (GPMC_Handle handle)
	Function to clear GPMC ECC result register. More...

int32_t	GPMC_eccBchFillSyndromeValue (GPMC_Handle handle, uint32_t sector, uint32_t *bchData)
	Function to fill BCH syndrome value per sector to ELM module. More...

int32_t	GPMC_eccBchStartErrorProcessing (GPMC_Handle handle, uint8_t sector)
	Function to start error processing for a sector by ELM module. More...

int32_t	GPMC_eccBchCheckErrorProcessingStatus (GPMC_Handle handle, uint32_t sector)
	Function to get error processing status for a sector by ELM module. More...

int32_t	GPMC_eccBchSectorGetError (GPMC_Handle handle, uint32_t sector, uint32_t errCount, uint32_t errLoc)
	Function to get number of errors per sector by ELM module. More...

int32_t	GPMC_eccCalculateBchSyndromePolynomial (GPMC_Handle handle, uint8_t *pEccdata, uint32_t sector)
	Function to compute BCH syndrome polynomial for NAND write operation. More...

int32_t	GPMC_eccGetBchSyndromePolynomial (GPMC_Handle handle, uint32_t sector, uint32_t *bchData)
	Function to get BCH syndrome polynomial per sector NAND read operation. More...

int32_t	GPMC_configurePrefetchPostWriteEngine (GPMC_Handle handle)
	Function to configure GPMC PREFETCH read and POST write engine. More...

int32_t	GPMC_disableFlashWriteProtect (GPMC_Handle handle)
	Function to disable WRITE protect line. More...

int32_t	GPMC_enableFlashWriteProtect (GPMC_Handle handle)
	Function to disable WRITE protect line. More...

Typedefs
typedef void *	GPMC_Handle
	A handle that is returned from a GPMC_open() call. More...

typedef void(*	GPMC_CallbackFxn) (GPMC_Handle handle, GPMC_Transaction *transaction)
	The definition of a callback function used by the GPMC driver when used in GPMC_OPERATING_MODE_CALLBACK mode. More...

Enumerations
enum	GPMC_nandEccAlgo { GPMC_NAND_ECC_ALGO_NONE = 0x00U, GPMC_NAND_ECC_ALGO_HAMMING_1BIT, GPMC_NAND_ECC_ALGO_BCH_4BIT, GPMC_NAND_ECC_ALGO_BCH_8BIT, GPMC_NAND_ECC_ALGO_BCH_16BIT }
	GPMC ECC engine algoritms. More...

enum	GPMC_OperatingMode { GPMC_OPERATING_MODE_BLOCKING = 0, GPMC_OPERATING_MODE_CALLBACK, GPMC_OPERATING_MODE_POLLING }
	GPMC driver operating modes. More...

enum	GPMC_TransferMode { GPMC_TRANSFER_MODE_BLOCKING = 0, GPMC_TRANSFER_MODE_CALLBACK }
	GPMC data transfer modes. More...

enum	GPMC_TransactionType { GPMC_TRANSACTION_TYPE_READ = 0, GPMC_TRANSACTION_TYPE_WRITE, GPMC_TRANSACTION_TYPE_READ_CMDREG, GPMC_TRANSACTION_TYPE_WRITE_CMDREG }
	Type of the GPMC transaction for read and write. More...

enum	GPMC_TransactionStatus { GPMC_TRANSFER_COMPLETED = 0, GPMC_TRANSFER_STARTED, GPMC_TRANSFER_CANCELED, GPMC_TRANSFER_FAILED, GPMC_TRANSFER_CSN_DEASSERT, GPMC_TRANSFER_TIMEOUT }
	Transaction status codes that are set by the GPMC driver. More...

Macros
#define	GPMC_CS_TIMING_CONFIG(CSWrOffTime, CSRdOffTime, CSExtDelayFlag, CSOnTime)
	This macro used to make the conf value which is used to configure the CS signal timing configuration. More...

#define	GPMC_ADV_TIMING_CONFIG(ADVAADMuxWrOffTime, ADVAADMuxRdOffTime, ADVWrOffTime, ADVRdOffTime, ADVExtDelayFlag, ADVAADMuxOnTime, ADVOnTime)
	This macro used to make the conf value which is used to configure the ADV# signal timing configuration. More...

#define	GPMC_WE_OE_TIMING_CONFIG(WEOffTime, WEExtDelayFlag, WEOnTime, OEAADMuxOffTime, OEOffTime, OEExtDelayFlag, OEAADMuxOnTime, OEOnTime)
	This macro used to make the conf value which is used to configure the WE# and OE# signal timing configuration. More...

#define	GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(rdCycleTime, wrCycleTime, rdAccessTime, pageBurstAccessTime)
	This macro used to make the conf value which is used to configure the read access and cycle time timing configuration. More...

#define	GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(cycle2CycleDelay, cycle2CycleDelaySameCSCfg, cycle2CycleDelayDiffCSCfg, busTAtime)
	This macro used to make the conf value which is used to configure the cycle to cycle and bus turn around time timing configuration. More...

#define	GPMC_DMA_COPY_LOWER_LIMIT (512U)
	size in bytes More...

#define	GPMC_CS_BASE_ADDR_SHIFT (24U)
	GPMC CHIP select base address shift value. More...

#define	GPMC_ECC_WRAP_MODE1 (1)
	GPMC ECC Wrap mode for ECC value computation. More...

#define	GPMC_CMD_INVALID (0xFFFFFFFFU)
	Invalid value for params initialisation. More...

#define	GPMC_MEM_TYPE_NAND (0)

#define	GPMC_MEM_TYPE_PSRAM (1)

#define	GPMC_CHIP_SELECT_CS0 (0U)

#define	GPMC_CHIP_SELECT_CS1 (1U)

#define	GPMC_CHIP_SELECT_CS2 (2U)

#define	GPMC_CHIP_SELECT_CS3 (3U)

#define	GPMC_FIFOEVENT_STATUS (0U)

#define	GPMC_TERMINALCOUNT_STATUS (1U)

#define	GPMC_WAIT0EDGEDETECTION_STATUS (2U)

#define	GPMC_WAIT1EDGEDETECTION_STATUS (3U)

#define	GPMC_FIFOEVENT_INT (0U)

#define	GPMC_TERMINALCOUNT_INT (1U)

#define	GPMC_WAIT0EDGEDETECTION_INT (2U)

#define	GPMC_WAIT1EDGEDETECTION_INT (3U)

#define	GPMC_PREFETCH_ACCESSMODE_READ (0U)

#define	GPMC_PREFETCH_ACCESSMODE_WRITE (1U)

#define	GPMC_ECC_ALGORITHM_HAMMINGCODE (0U)

#define	GPMC_ECC_ALGORITHM_BCH (1U)

#define	GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS (0U)

#define	GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS (1U)

#define	GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS (2U)

#define	GPMC_ECCPOINTER_RESULT_1 (1U)

#define	GPMC_ECCPOINTER_RESULT_2 (2U)

#define	GPMC_ECCPOINTER_RESULT_3 (3U)

#define	GPMC_ECCPOINTER_RESULT_4 (4U)

#define	GPMC_ECCPOINTER_RESULT_5 (5U)

#define	GPMC_ECCPOINTER_RESULT_6 (6U)

#define	GPMC_ECCPOINTER_RESULT_7 (7U)

#define	GPMC_ECCPOINTER_RESULT_8 (8U)

#define	GPMC_ECCPOINTER_RESULT_9 (9U)

#define	GPMC_ECC_SIZE_0 (0U)

#define	GPMC_ECC_SIZE_1 (1U)

#define	GPMC_ECC_RESULT_1 (1U)

#define	GPMC_ECC_RESULT_2 (2U)

#define	GPMC_ECC_RESULT_3 (3U)

#define	GPMC_ECC_RESULT_4 (4U)

#define	GPMC_ECC_RESULT_5 (5U)

#define	GPMC_ECC_RESULT_6 (6U)

#define	GPMC_ECC_RESULT_7 (7U)

#define	GPMC_ECC_RESULT_8 (8U)

#define	GPMC_ECC_RESULT_9 (9U)

#define	GPMC_BCH_RESULT0 (0U)

#define	GPMC_BCH_RESULT1 (1U)

#define	GPMC_BCH_RESULT2 (2U)

#define	GPMC_BCH_RESULT3 (3U)

#define	GPMC_BCH_RESULT4 (4U)

#define	GPMC_BCH_RESULT5 (5U)

#define	GPMC_BCH_RESULT6 (6U)

#define	GPMC_CS_MASK_ADDR_SIZE_256MB (0x00U)

#define	GPMC_CS_MASK_ADDR_SIZE_128MB (0x08U)

#define	GPMC_CS_MASK_ADDR_SIZE_64MB (0x0cU)

#define	GPMC_CS_MASK_ADDR_SIZE_32MB (0x0eU)

#define	GPMC_CS_MASK_ADDR_SIZE_16MB (0x0fU)

#define	GPMC_NAND_CS_ON_TIME 0U
	Chip select on time (FCLK periods) More...

#define	GPMC_NAND_WE_ON_TIME 0U
	Write enable on time (FCLK periods) More...

#define	GPMC_NAND_ADV_ON_TIME 0U
	Address valid on time (FCLK periods) More...

#define	GPMC_NAND_CS_WR_OFF_TIME 6U
	Chip select off time for write (FCLK periods) More...

#define	GPMC_NAND_WR_CYCLE_TIME 6U
	Write cycle time (FCLK periods) More...

#define	GPMC_NAND_ADV_WR_OFF_TIME 4U
	Address valid off time for write (FCLK periods) More...

#define	GPMC_NAND_CS_RD_OFF_TIME 6U
	Chip select off time for read (FCLK periods) More...

#define	GPMC_NAND_RD_CYCLE_TIME 6U
	Read cycle time (FCLK periods) More...

#define	GPMC_NAND_ADV_AADMUX_ON_TIME 0U
	Address valid on time when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_NAND_ADV_AADMUX_RD_OFF_TIME 0U
	Address valid on time for read when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_NAND_ADV_AADMUX_WR_OFF_TIME 0U
	Address valid on time for write when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_NAND_PAGEBURST_ACCESS_TIME 0U
	Delay between successive words in a multiple access. (FCLK periods) More...

#define	GPMC_NAND_OE_ON_TIME 1U
	Output enable on time (FCLK periods) More...

#define	GPMC_NAND_OE_OFF_TIME 4U
	Output enable off time (FCLK periods) More...

#define	GPMC_NAND_OE_AADMUX_ON_TIME 0U
	Output enable assertion time for the first address phase in an AAD-muxed protocol. (FCLK periods) More...

#define	GPMC_NAND_OE_AADMUX_OFF_TIME 0U
	Output enable deassertion time for the first address phase in an AAD-muxed protocol. (FCLK periods) More...

#define	GPMC_NAND_ADV_RD_OFF_TIME 4U
	Address valid off time for read (FCLK periods) More...

#define	GPMC_NAND_WE_OFF_TIME 3U
	Write enable off time (FCLK periods) More...

#define	GPMC_NAND_RD_ACCESS_TIME 4U
	Read access time (FCLK periods) More...

#define	GPMC_NAND_C2C_DELAY 0U
	CS high pulse delay (FCLK periods) More...

#define	GPMC_NAND_ADMUX_DATA_VALID 0U
	First data write cycle (FCLK) More...

#define	GPMC_NAND_WR_ACCESS_TIME 6U
	Write access time (FCLK periods) More...

#define	GPMC_NAND_BRST_TAROUND_TIME 0U
	Burst turnaround latency (FCLK periods) More...

#define	GPMC_PSRAM_CS_ON_TIME 3U
	Chip select on time (FCLK periods) More...

#define	GPMC_PSRAM_WE_ON_TIME 10U
	Write enable on time (FCLK periods) More...

#define	GPMC_PSRAM_ADV_ON_TIME 1U
	Address valid on time (FCLK periods) More...

#define	GPMC_PSRAM_CS_WR_OFF_TIME 21U
	Chip select off time for write (FCLK periods) More...

#define	GPMC_PSRAM_WR_CYCLE_TIME 23U
	Write cycle time (FCLK periods) More...

#define	GPMC_PSRAM_ADV_WR_OFF_TIME 3U
	Address valid off time for write (FCLK periods) More...

#define	GPMC_PSRAM_CS_RD_OFF_TIME 21U
	Chip select off time for read (FCLK periods) More...

#define	GPMC_PSRAM_RD_CYCLE_TIME 23U
	Read cycle time (FCLK periods) More...

#define	GPMC_PSRAM_ADV_AADMUX_ON_TIME 1U
	Address valid on time when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_PSRAM_ADV_AADMUX_RD_OFF_TIME 2U
	Address valid on time for read when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_PSRAM_ADV_AADMUX_WR_OFF_TIME 2U
	Address valid on time for write when using AAD- Muxed protocol. (FCLK periods) More...

#define	GPMC_PSRAM_PAGEBURST_ACCESS_TIME 3U
	Delay between successive words in a multiple access. (FCLK periods) More...

#define	GPMC_PSRAM_OE_ON_TIME 10U
	Output enable on time (FCLK periods) More...

#define	GPMC_PSRAM_OE_OFF_TIME 1U
	Output enable off time (FCLK periods) More...

#define	GPMC_PSRAM_OE_AADMUX_ON_TIME 1U
	Output enable assertion time for the first address phase in an AAD-muxed protocol. (FCLK periods) More...

#define	GPMC_PSRAM_OE_AADMUX_OFF_TIME 15U
	Output enable deassertion time for the first address phase in an AAD-muxed protocol. (FCLK periods) More...

#define	GPMC_PSRAM_ADV_RD_OFF_TIME 3U
	Address valid off time for read (FCLK periods) More...

#define	GPMC_PSRAM_WE_OFF_TIME 16U
	Write enable off time (FCLK periods) More...

#define	GPMC_PSRAM_RD_ACCESS_TIME 16U
	Read access time (FCLK periods) More...

#define	GPMC_PSRAM_C2C_DELAY 0U
	CS high pulse delay (FCLK periods) More...

#define	GPMC_PSRAM_ADMUX_DATA_VALID 0U
	First data write cycle (FCLK) More...

#define	GPMC_PSRAM_WR_ACCESS_TIME 8U
	Write access time (FCLK periods) More...

#define	GPMC_PSRAM_BRST_TAROUND_TIME 1U
	Burst turnaround latency (FCLK periods) More...

Macro Definition Documentation

◆ GPMC_CHIP_SELECT_CS0

#define GPMC_CHIP_SELECT_CS0 (0U)

GPMC CHIP select

Macros which can be used as to select CHIP select instance for GPMC.

◆ GPMC_CHIP_SELECT_CS1

#define GPMC_CHIP_SELECT_CS1 (1U)

◆ GPMC_CHIP_SELECT_CS2

#define GPMC_CHIP_SELECT_CS2 (2U)

◆ GPMC_CHIP_SELECT_CS3

#define GPMC_CHIP_SELECT_CS3 (3U)

◆ GPMC_FIFOEVENT_STATUS

#define GPMC_FIFOEVENT_STATUS (0U)

GPMC Interupt status flags

Macros which can be used as 'interupt' parameter to GPMC_interuptStatusGet, GPMC_interuptStatusClear APIs.

◆ GPMC_TERMINALCOUNT_STATUS

#define GPMC_TERMINALCOUNT_STATUS (1U)

◆ GPMC_WAIT0EDGEDETECTION_STATUS

#define GPMC_WAIT0EDGEDETECTION_STATUS (2U)

◆ GPMC_WAIT1EDGEDETECTION_STATUS

#define GPMC_WAIT1EDGEDETECTION_STATUS (3U)

◆ GPMC_FIFOEVENT_INT

#define GPMC_FIFOEVENT_INT (0U)

GPMC Interupt Flags

Macros which can be used as 'interupt' parameter to GPMC_enableInterupt, GPMC_disableInterupt APIs.

◆ GPMC_TERMINALCOUNT_INT

#define GPMC_TERMINALCOUNT_INT (1U)

◆ GPMC_WAIT0EDGEDETECTION_INT

#define GPMC_WAIT0EDGEDETECTION_INT (2U)

◆ GPMC_WAIT1EDGEDETECTION_INT

#define GPMC_WAIT1EDGEDETECTION_INT (3U)

◆ GPMC_PREFETCH_ACCESSMODE_READ

#define GPMC_PREFETCH_ACCESSMODE_READ (0U)

GPMC Interupt Flags

Macros which can be used as 'mode' parameter to GPMC_prefetchPostWriteConfigEnable API.

◆ GPMC_PREFETCH_ACCESSMODE_WRITE

#define GPMC_PREFETCH_ACCESSMODE_WRITE (1U)

◆ GPMC_ECC_ALGORITHM_HAMMINGCODE

#define GPMC_ECC_ALGORITHM_HAMMINGCODE (0U)

GPMC ECC algorithm

Macros which can be used to set GPMC ECC engine algorithm.

◆ GPMC_ECC_ALGORITHM_BCH

#define GPMC_ECC_ALGORITHM_BCH (1U)

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS

#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS (0U)

GPMC ECC error correvel level.

Macros which can be used to set GPMC ECC engine error correction level.

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS

#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS (1U)

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS

#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS (2U)

◆ GPMC_ECCPOINTER_RESULT_1

#define GPMC_ECCPOINTER_RESULT_1 (1U)

GPMC ECC Result Register

Macros which can be used to select ECC result register for GPMC ECC engine.

◆ GPMC_ECCPOINTER_RESULT_2

#define GPMC_ECCPOINTER_RESULT_2 (2U)

◆ GPMC_ECCPOINTER_RESULT_3

#define GPMC_ECCPOINTER_RESULT_3 (3U)

◆ GPMC_ECCPOINTER_RESULT_4

#define GPMC_ECCPOINTER_RESULT_4 (4U)

◆ GPMC_ECCPOINTER_RESULT_5

#define GPMC_ECCPOINTER_RESULT_5 (5U)

◆ GPMC_ECCPOINTER_RESULT_6

#define GPMC_ECCPOINTER_RESULT_6 (6U)

◆ GPMC_ECCPOINTER_RESULT_7

#define GPMC_ECCPOINTER_RESULT_7 (7U)

◆ GPMC_ECCPOINTER_RESULT_8

#define GPMC_ECCPOINTER_RESULT_8 (8U)

◆ GPMC_ECCPOINTER_RESULT_9

#define GPMC_ECCPOINTER_RESULT_9 (9U)

◆ GPMC_ECC_SIZE_0

#define GPMC_ECC_SIZE_0 (0U)

GPMC ECC Size Config

Macros which can be used to set length of used and unsued bytes in the ECC value.

◆ GPMC_ECC_SIZE_1

#define GPMC_ECC_SIZE_1 (1U)

◆ GPMC_ECC_RESULT_1

#define GPMC_ECC_RESULT_1 (1U)

GPMC ECC Result Register Size

Macros which can be used to set ECC size for ECC result register.

◆ GPMC_ECC_RESULT_2

#define GPMC_ECC_RESULT_2 (2U)

◆ GPMC_ECC_RESULT_3

#define GPMC_ECC_RESULT_3 (3U)

◆ GPMC_ECC_RESULT_4

#define GPMC_ECC_RESULT_4 (4U)

◆ GPMC_ECC_RESULT_5

#define GPMC_ECC_RESULT_5 (5U)

◆ GPMC_ECC_RESULT_6

#define GPMC_ECC_RESULT_6 (6U)

◆ GPMC_ECC_RESULT_7

#define GPMC_ECC_RESULT_7 (7U)

◆ GPMC_ECC_RESULT_8

#define GPMC_ECC_RESULT_8 (8U)

◆ GPMC_ECC_RESULT_9

#define GPMC_ECC_RESULT_9 (9U)

◆ GPMC_BCH_RESULT0

#define GPMC_BCH_RESULT0 (0U)

GPMC BCH RESULT

Macros which can be used to get BCH syndrome polynomial in GPMC_eccBchResultGet API.

◆ GPMC_BCH_RESULT1

#define GPMC_BCH_RESULT1 (1U)

◆ GPMC_BCH_RESULT2

#define GPMC_BCH_RESULT2 (2U)

◆ GPMC_BCH_RESULT3

#define GPMC_BCH_RESULT3 (3U)

◆ GPMC_BCH_RESULT4

#define GPMC_BCH_RESULT4 (4U)

◆ GPMC_BCH_RESULT5

#define GPMC_BCH_RESULT5 (5U)

◆ GPMC_BCH_RESULT6

#define GPMC_BCH_RESULT6 (6U)

◆ GPMC_CS_MASK_ADDR_SIZE_256MB

#define GPMC_CS_MASK_ADDR_SIZE_256MB (0x00U)

GPMC CHIP Select SIZE

Macros which can be used to set chip select address size.

◆ GPMC_CS_MASK_ADDR_SIZE_128MB

#define GPMC_CS_MASK_ADDR_SIZE_128MB (0x08U)

◆ GPMC_CS_MASK_ADDR_SIZE_64MB

#define GPMC_CS_MASK_ADDR_SIZE_64MB (0x0cU)

◆ GPMC_CS_MASK_ADDR_SIZE_32MB

#define GPMC_CS_MASK_ADDR_SIZE_32MB (0x0eU)

◆ GPMC_CS_MASK_ADDR_SIZE_16MB

#define GPMC_CS_MASK_ADDR_SIZE_16MB (0x0fU)

◆ GPMC_CS_TIMING_CONFIG

#define GPMC_CS_TIMING_CONFIG	(	CSWrOffTime,
		CSRdOffTime,
		CSExtDelayFlag,
		CSOnTime
	)

Value:

    ((uint32_t) (((CSWrOffTime) << CSL_GPMC_CONFIG2_CSWROFFTIME_SHIFT)    \
                 & CSL_GPMC_CONFIG2_CSWROFFTIME_MASK) |                   \
     (((CSRdOffTime) << CSL_GPMC_CONFIG2_CSRDOFFTIME_SHIFT)               \
      & CSL_GPMC_CONFIG2_CSRDOFFTIME_MASK) |                              \
     (((CSExtDelayFlag) << CSL_GPMC_CONFIG2_CSEXTRADELAY_SHIFT)           \
      & CSL_GPMC_CONFIG2_CSEXTRADELAY_MASK) |                             \
     (((CSOnTime) << CSL_GPMC_CONFIG2_CSONTIME_SHIFT)                     \
      & CSL_GPMC_CONFIG2_CSONTIME_MASK))

This macro used to make the conf value which is used to configure the CS signal timing configuration.

Parameters

CSWrOffTime	CS# de-assertion time from start cycle time for write accesses in GPMC_FCLK cycles.
CSRdOffTime	CS# de-assertion time from start cycle time for read accesses in GPMC_FCLK cycles
CSExtDelayFlag	Flag to indicate whether to add half GPMC_FCLK delay to CS or not. This can take one of the following values : CSL_GPMC_CONFIG2_CSEXTRADELAY_DELAYED : CS# Timing control signal is delayed of half GPMC_FCLK cycle. CSL_GPMC_CONFIG2_CSEXTRADELAY_NOTDELAYED : CS# Timing control signal is not delayed.
CSOnTime	CS# assertion time from start cycle time in GPMC_FCLK cycles.

◆ GPMC_ADV_TIMING_CONFIG

#define GPMC_ADV_TIMING_CONFIG	(	ADVAADMuxWrOffTime,
		ADVAADMuxRdOffTime,
		ADVWrOffTime,
		ADVRdOffTime,
		ADVExtDelayFlag,
		ADVAADMuxOnTime,
		ADVOnTime
	)

Value:

    ((uint32_t) (((ADVAADMuxWrOffTime) <<                                   \
                  CSL_GPMC_CONFIG3_ADVAADMUXWROFFTIME_SHIFT) &                \
                 CSL_GPMC_CONFIG3_ADVAADMUXWROFFTIME_MASK) |                  \
     (((ADVAADMuxRdOffTime) << CSL_GPMC_CONFIG3_ADVAADMUXRDOFFTIME_SHIFT) &   \
      CSL_GPMC_CONFIG3_ADVAADMUXRDOFFTIME_MASK) |                             \
     (((ADVWrOffTime) << CSL_GPMC_CONFIG3_ADVWROFFTIME_SHIFT) &               \
      CSL_GPMC_CONFIG3_ADVWROFFTIME_MASK) |                                   \
     (((ADVRdOffTime) << CSL_GPMC_CONFIG3_ADVRDOFFTIME_SHIFT) &               \
      CSL_GPMC_CONFIG3_ADVRDOFFTIME_MASK) |                                   \
     (((ADVExtDelayFlag) << CSL_GPMC_CONFIG3_ADVEXTRADELAY_SHIFT) &           \
      CSL_GPMC_CONFIG3_ADVEXTRADELAY_MASK) |                                  \
     (((ADVAADMuxOnTime) << CSL_GPMC_CONFIG3_ADVAADMUXONTIME_SHIFT) &         \
      CSL_GPMC_CONFIG3_ADVAADMUXONTIME_MASK) |                                \
     (((ADVOnTime) << CSL_GPMC_CONFIG3_ADVONTIME_SHIFT) &                     \
      CSL_GPMC_CONFIG3_ADVONTIME_MASK))

This macro used to make the conf value which is used to configure the ADV# signal timing configuration.

Parameters

ADVAADMuxWrOffTime	ADV# de-assertion time in GPMC_FCLK cycles for first address phase when using the AAD-Mux prorocol.
ADVAADMuxRdOffTime	ADV# de-assertion time in GPMC_FCLK cycles for first address phase when using the AAD-Mux prorocol.
ADVWrOffTime	ADV# de-assertion time in GPMC_FCLK cycles from start cycle time for write accesses
ADVRdOffTime	ADV# de-assertion time in GPMC_FCLK cycles from start cycle time for write accesses
ADVExtDelayFlag	Flag to indicate whether to add half GPMC_FCLK delay to ADV or not. This can take one of the following values : CSL_GPMC_CONFIG3_ADVEXTRADELAY_DELAYED : ADV# Timing control signal is delayed of half GPMC_FCLK cycle. CSL_GPMC_CONFIG3_ADVEXTRADELAY_NOTDELAYED : ADV# Timing control signal is not delayed.
ADVAADMuxOnTime	ADV# assertion time in GPMC_FCLK cycles for first address phase when using the AAD-Multiplexed protocol.
ADVOnTime	ADV# assertion time from start cycle time in GPMC_FCLK cycles.

◆ GPMC_WE_OE_TIMING_CONFIG

#define GPMC_WE_OE_TIMING_CONFIG	(	WEOffTime,
		WEExtDelayFlag,
		WEOnTime,
		OEAADMuxOffTime,
		OEOffTime,
		OEExtDelayFlag,
		OEAADMuxOnTime,
		OEOnTime
	)

Value:

    ((uint32_t) (((WEOffTime) <<                                                \
                  CSL_GPMC_CONFIG4_WEOFFTIME_SHIFT) &                             \
                 CSL_GPMC_CONFIG4_WEOFFTIME_MASK) |                               \
     (((WEExtDelayFlag) <<                                                      \
       CSL_GPMC_CONFIG4_WEEXTRADELAY_SHIFT) & CSL_GPMC_CONFIG4_WEEXTRADELAY_MASK) | \
     (((WEOnTime) <<                                                            \
       CSL_GPMC_CONFIG4_WEONTIME_SHIFT) & CSL_GPMC_CONFIG4_WEONTIME_MASK) |         \
     (((OEAADMuxOffTime) <<                                                     \
       CSL_GPMC_CONFIG4_OEAADMUXOFFTIME_SHIFT) &                                  \
      CSL_GPMC_CONFIG4_OEAADMUXOFFTIME_MASK) |                                    \
     (((OEOffTime) <<                                                           \
       CSL_GPMC_CONFIG4_OEOFFTIME_SHIFT) & CSL_GPMC_CONFIG4_OEOFFTIME_MASK) |       \
     (((OEExtDelayFlag) <<                                                      \
       CSL_GPMC_CONFIG4_OEEXTRADELAY_SHIFT) & CSL_GPMC_CONFIG4_OEEXTRADELAY_MASK) | \
     (((OEAADMuxOnTime) <<                                                      \
       CSL_GPMC_CONFIG4_OEAADMUXONTIME_SHIFT) &                                   \
      CSL_GPMC_CONFIG4_OEAADMUXONTIME_MASK) |                                     \
     (((OEOnTime) <<                                                            \
       CSL_GPMC_CONFIG4_OEONTIME_SHIFT) & CSL_GPMC_CONFIG4_OEONTIME_MASK))

This macro used to make the conf value which is used to configure the WE# and OE# signal timing configuration.

Parameters

WEOffTime	WE# de-assertion time in GPMC_FCLK cycles from start cycle time.
WEExtDelayFlag	Flag to indicate whether to add half GPMC_FCLK delay to WE or not. This can take one of the following values : CSL_GPMC_CONFIG4_WEEXTRADELAY_DELAYED : WE# Timing control signal is delayed of half GPMC_FCLK cycle. CSL_GPMC_CONFIG4_WEEXTRADELAY_NOTDELAYED : WE# Timing control signal is not delayed.
WEOnTime	WE# assertion time in GPMC_FCLK cycles from start cycle time.
OEAADMuxOffTime	OE# de-assertion time in GPMC_FCLK cycles for first address phase when using the AAD-Mux prorocol.
OEOffTime	OE# de-assertion time in GPMC_FCLK cycles from start cycle time.
OEExtDelayFlag	Flag to indicate whether to add half GPMC_FCLK delay to OE or not. This can take one of the following values : CSL_GPMC_CONFIG4_OEEXTRADELAY_DELAYED : OE# Timing control signal is delayed of half GPMC_FCLK cycle. CSL_GPMC_CONFIG4_OEEXTRADELAY_NOTDELAYED : OE# Timing control signal is not delayed.
OEAADMuxOnTime	OE# assertion time in GPMC_FCLK cycles for first address phase when using the AAD-Mux prorocol.
OEOnTime	OE# assertion time in GPMC_FCLK cycles from start cycle time.

◆ GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG

#define GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG	(	rdCycleTime,
		wrCycleTime,
		rdAccessTime,
		pageBurstAccessTime
	)

Value:

    ((uint32_t) (((rdCycleTime) <<                                              \
                  CSL_GPMC_CONFIG5_RDCYCLETIME_SHIFT) &                           \
                 CSL_GPMC_CONFIG5_RDCYCLETIME_MASK) |                             \
     (((wrCycleTime) <<                                                         \
       CSL_GPMC_CONFIG5_WRCYCLETIME_SHIFT) & CSL_GPMC_CONFIG5_WRCYCLETIME_MASK) |   \
     (((rdAccessTime) <<                                                        \
       CSL_GPMC_CONFIG5_RDACCESSTIME_SHIFT) & CSL_GPMC_CONFIG5_RDACCESSTIME_MASK) | \
     (((pageBurstAccessTime) <<                                                 \
       CSL_GPMC_CONFIG5_PAGEBURSTACCESSTIME_SHIFT) &                              \
      CSL_GPMC_CONFIG5_PAGEBURSTACCESSTIME_MASK))

This macro used to make the conf value which is used to configure the read access and cycle time timing configuration.

Parameters

rdCycleTime	Total read cycle time in GPMC_FCLK cycles.
wrCycleTime	Total write cycle time in GPMC_FCLK cycles.
rdAccessTime	Read access time (Delay between start cycle time and first data valid) in GPMC_FCLK cycles.
pageBurstAccessTime	Page burest access time (Delay between successive words in a multiple access)in GPMC_FCLK cycles.

◆ GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG

#define GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG	(	cycle2CycleDelay,
		cycle2CycleDelaySameCSCfg,
		cycle2CycleDelayDiffCSCfg,
		busTAtime
	)

Value:

    ((uint32_t) (((cycle2CycleDelay) <<                                         \
                  CSL_GPMC_CONFIG6_CYCLE2CYCLEDELAY_SHIFT) &                      \
                 CSL_GPMC_CONFIG6_CYCLE2CYCLEDELAY_MASK) |                        \
     (((cycle2CycleDelaySameCSCfg) <<                                           \
       CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_SHIFT) &                              \
      CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_MASK) |                                \
     (((cycle2CycleDelayDiffCSCfg) <<                                           \
       CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_SHIFT) &                              \
      CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_MASK) |                                \
     (((busTAtime) <<                                                           \
       CSL_GPMC_CONFIG6_BUSTURNAROUND_SHIFT) & CSL_GPMC_CONFIG6_BUSTURNAROUND_MASK))

This macro used to make the conf value which is used to configure the cycle to cycle and bus turn around time timing configuration.

Parameters

cycle2CycleDelay	Cycle to cycle delay (Chip select high pulse delay between two successive accesses)in GPMC_FCLK cycles.
cycle2CycleDelaySameCSCfg	Specified whether to add the cycle to cycle delay between two successive accesses or not (to the same chip-select). This can take one of the following values : CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_C2CDELAY : To add the delay. CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_NOC2CDELAY : Don't add the delay.
cycle2CycleDelayDiffCSCfg	Specified whether to add the cycle to cycle delay between two successive accesses or not (to the diffrent chip-select). This can take one of the following values : CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_C2CDELAY : To add the delay. CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_NOC2CDELAY : Don't add the delay.
busTAtime	Bus turn aroung time between two successive accesses to the same chip-select (read to write) or to a diff chip-select in GPMC_FCLK cycles.

◆ GPMC_NAND_CS_ON_TIME

#define GPMC_NAND_CS_ON_TIME 0U

Chip select on time (FCLK periods)

GPMC NAND Specific Timing Parameters

Nand flash specific GPMC timing parameters. These are used to GPMC CONFIG registers.

◆ GPMC_NAND_WE_ON_TIME

#define GPMC_NAND_WE_ON_TIME 0U

Write enable on time (FCLK periods)

◆ GPMC_NAND_ADV_ON_TIME

#define GPMC_NAND_ADV_ON_TIME 0U

Address valid on time (FCLK periods)

◆ GPMC_NAND_CS_WR_OFF_TIME

#define GPMC_NAND_CS_WR_OFF_TIME 6U

Chip select off time for write (FCLK periods)

◆ GPMC_NAND_WR_CYCLE_TIME

#define GPMC_NAND_WR_CYCLE_TIME 6U

Write cycle time (FCLK periods)

◆ GPMC_NAND_ADV_WR_OFF_TIME

#define GPMC_NAND_ADV_WR_OFF_TIME 4U

Address valid off time for write (FCLK periods)

◆ GPMC_NAND_CS_RD_OFF_TIME

#define GPMC_NAND_CS_RD_OFF_TIME 6U

Chip select off time for read (FCLK periods)

◆ GPMC_NAND_RD_CYCLE_TIME

#define GPMC_NAND_RD_CYCLE_TIME 6U

Read cycle time (FCLK periods)

◆ GPMC_NAND_ADV_AADMUX_ON_TIME

#define GPMC_NAND_ADV_AADMUX_ON_TIME 0U

Address valid on time when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_NAND_ADV_AADMUX_RD_OFF_TIME

#define GPMC_NAND_ADV_AADMUX_RD_OFF_TIME 0U

Address valid on time for read when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_NAND_ADV_AADMUX_WR_OFF_TIME

#define GPMC_NAND_ADV_AADMUX_WR_OFF_TIME 0U

Address valid on time for write when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_NAND_PAGEBURST_ACCESS_TIME

#define GPMC_NAND_PAGEBURST_ACCESS_TIME 0U

Delay between successive words in a multiple access. (FCLK periods)

◆ GPMC_NAND_OE_ON_TIME

#define GPMC_NAND_OE_ON_TIME 1U

Output enable on time (FCLK periods)

◆ GPMC_NAND_OE_OFF_TIME

#define GPMC_NAND_OE_OFF_TIME 4U

Output enable off time (FCLK periods)

◆ GPMC_NAND_OE_AADMUX_ON_TIME

#define GPMC_NAND_OE_AADMUX_ON_TIME 0U

Output enable assertion time for the first address phase in an AAD-muxed protocol. (FCLK periods)

◆ GPMC_NAND_OE_AADMUX_OFF_TIME

#define GPMC_NAND_OE_AADMUX_OFF_TIME 0U

Output enable deassertion time for the first address phase in an AAD-muxed protocol. (FCLK periods)

◆ GPMC_NAND_ADV_RD_OFF_TIME

#define GPMC_NAND_ADV_RD_OFF_TIME 4U

Address valid off time for read (FCLK periods)

◆ GPMC_NAND_WE_OFF_TIME

#define GPMC_NAND_WE_OFF_TIME 3U

Write enable off time (FCLK periods)

◆ GPMC_NAND_RD_ACCESS_TIME

#define GPMC_NAND_RD_ACCESS_TIME 4U

Read access time (FCLK periods)

◆ GPMC_NAND_C2C_DELAY

#define GPMC_NAND_C2C_DELAY 0U

CS high pulse delay (FCLK periods)

◆ GPMC_NAND_ADMUX_DATA_VALID

#define GPMC_NAND_ADMUX_DATA_VALID 0U

First data write cycle (FCLK)

◆ GPMC_NAND_WR_ACCESS_TIME

#define GPMC_NAND_WR_ACCESS_TIME 6U

Write access time (FCLK periods)

◆ GPMC_NAND_BRST_TAROUND_TIME

#define GPMC_NAND_BRST_TAROUND_TIME 0U

Burst turnaround latency (FCLK periods)

◆ GPMC_PSRAM_CS_ON_TIME

#define GPMC_PSRAM_CS_ON_TIME 3U

Chip select on time (FCLK periods)

GPMC PSRAM Specific Timing Parameters

PSRAM specific GPMC timing parameters. These are used to GPMC CONFIG registers.

◆ GPMC_PSRAM_WE_ON_TIME

#define GPMC_PSRAM_WE_ON_TIME 10U

Write enable on time (FCLK periods)

◆ GPMC_PSRAM_ADV_ON_TIME

#define GPMC_PSRAM_ADV_ON_TIME 1U

Address valid on time (FCLK periods)

◆ GPMC_PSRAM_CS_WR_OFF_TIME

#define GPMC_PSRAM_CS_WR_OFF_TIME 21U

Chip select off time for write (FCLK periods)

◆ GPMC_PSRAM_WR_CYCLE_TIME

#define GPMC_PSRAM_WR_CYCLE_TIME 23U

Write cycle time (FCLK periods)

◆ GPMC_PSRAM_ADV_WR_OFF_TIME

#define GPMC_PSRAM_ADV_WR_OFF_TIME 3U

Address valid off time for write (FCLK periods)

◆ GPMC_PSRAM_CS_RD_OFF_TIME

#define GPMC_PSRAM_CS_RD_OFF_TIME 21U

Chip select off time for read (FCLK periods)

◆ GPMC_PSRAM_RD_CYCLE_TIME

#define GPMC_PSRAM_RD_CYCLE_TIME 23U

Read cycle time (FCLK periods)

◆ GPMC_PSRAM_ADV_AADMUX_ON_TIME

#define GPMC_PSRAM_ADV_AADMUX_ON_TIME 1U

Address valid on time when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_PSRAM_ADV_AADMUX_RD_OFF_TIME

#define GPMC_PSRAM_ADV_AADMUX_RD_OFF_TIME 2U

Address valid on time for read when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_PSRAM_ADV_AADMUX_WR_OFF_TIME

#define GPMC_PSRAM_ADV_AADMUX_WR_OFF_TIME 2U

Address valid on time for write when using AAD- Muxed protocol. (FCLK periods)

◆ GPMC_PSRAM_PAGEBURST_ACCESS_TIME

#define GPMC_PSRAM_PAGEBURST_ACCESS_TIME 3U

Delay between successive words in a multiple access. (FCLK periods)

◆ GPMC_PSRAM_OE_ON_TIME

#define GPMC_PSRAM_OE_ON_TIME 10U

Output enable on time (FCLK periods)

◆ GPMC_PSRAM_OE_OFF_TIME

#define GPMC_PSRAM_OE_OFF_TIME 1U

Output enable off time (FCLK periods)

◆ GPMC_PSRAM_OE_AADMUX_ON_TIME

#define GPMC_PSRAM_OE_AADMUX_ON_TIME 1U

Output enable assertion time for the first address phase in an AAD-muxed protocol. (FCLK periods)

◆ GPMC_PSRAM_OE_AADMUX_OFF_TIME

#define GPMC_PSRAM_OE_AADMUX_OFF_TIME 15U

Output enable deassertion time for the first address phase in an AAD-muxed protocol. (FCLK periods)

◆ GPMC_PSRAM_ADV_RD_OFF_TIME

#define GPMC_PSRAM_ADV_RD_OFF_TIME 3U

Address valid off time for read (FCLK periods)

◆ GPMC_PSRAM_WE_OFF_TIME

#define GPMC_PSRAM_WE_OFF_TIME 16U

Write enable off time (FCLK periods)

◆ GPMC_PSRAM_RD_ACCESS_TIME

#define GPMC_PSRAM_RD_ACCESS_TIME 16U

Read access time (FCLK periods)

◆ GPMC_PSRAM_C2C_DELAY

#define GPMC_PSRAM_C2C_DELAY 0U

CS high pulse delay (FCLK periods)

◆ GPMC_PSRAM_ADMUX_DATA_VALID

#define GPMC_PSRAM_ADMUX_DATA_VALID 0U

First data write cycle (FCLK)

◆ GPMC_PSRAM_WR_ACCESS_TIME

#define GPMC_PSRAM_WR_ACCESS_TIME 8U

Write access time (FCLK periods)

◆ GPMC_PSRAM_BRST_TAROUND_TIME

#define GPMC_PSRAM_BRST_TAROUND_TIME 1U

Burst turnaround latency (FCLK periods)

◆ GPMC_DMA_COPY_LOWER_LIMIT

#define GPMC_DMA_COPY_LOWER_LIMIT (512U)

size in bytes

◆ GPMC_CS_BASE_ADDR_SHIFT

#define GPMC_CS_BASE_ADDR_SHIFT (24U)

GPMC CHIP select base address shift value.

◆ GPMC_ECC_WRAP_MODE1

#define GPMC_ECC_WRAP_MODE1 (1)

GPMC ECC Wrap mode for ECC value computation.

◆ GPMC_CMD_INVALID

#define GPMC_CMD_INVALID (0xFFFFFFFFU)

Invalid value for params initialisation.

◆ GPMC_MEM_TYPE_NAND

#define GPMC_MEM_TYPE_NAND (0)

◆ GPMC_MEM_TYPE_PSRAM

#define GPMC_MEM_TYPE_PSRAM (1)

Typedef Documentation

◆ GPMC_Handle

typedef void* GPMC_Handle

A handle that is returned from a GPMC_open() call.

◆ GPMC_CallbackFxn

typedef void(* GPMC_CallbackFxn) (GPMC_Handle handle, GPMC_Transaction *transaction)

The definition of a callback function used by the GPMC driver when used in GPMC_OPERATING_MODE_CALLBACK mode.

Parameters

GPMC_Handle	GPMC_Handle
GPMC_Transaction*	GPMC_Transaction*

Enumeration Type Documentation

◆ GPMC_nandEccAlgo

enum GPMC_nandEccAlgo

GPMC ECC engine algoritms.

Enumerator
GPMC_NAND_ECC_ALGO_NONE
GPMC_NAND_ECC_ALGO_HAMMING_1BIT
GPMC_NAND_ECC_ALGO_BCH_4BIT
GPMC_NAND_ECC_ALGO_BCH_8BIT
GPMC_NAND_ECC_ALGO_BCH_16BIT

◆ GPMC_OperatingMode

enum GPMC_OperatingMode

GPMC driver operating modes.

Enumerator
GPMC_OPERATING_MODE_BLOCKING	Interupt based blocking mode
GPMC_OPERATING_MODE_CALLBACK	Interupt based callback mode
GPMC_OPERATING_MODE_POLLING	Non interupt base blocking mode

◆ GPMC_TransferMode

enum GPMC_TransferMode

GPMC data transfer modes.

Enumerator
GPMC_TRANSFER_MODE_BLOCKING	GPMC driver transaction blocks execution. This mode can only be used when called within a Task context and is interrupt based.
GPMC_TRANSFER_MODE_CALLBACK	GPMC driver transaction does not block code execution and will call a callback function. This mode can be used in a Task, Swi, or Hwi context.

◆ GPMC_TransactionType

enum GPMC_TransactionType

Type of the GPMC transaction for read and write.

Enumerator
GPMC_TRANSACTION_TYPE_READ	Read transaction
GPMC_TRANSACTION_TYPE_WRITE	Write transaction
GPMC_TRANSACTION_TYPE_READ_CMDREG	Read transaction with command register
GPMC_TRANSACTION_TYPE_WRITE_CMDREG	Write transaction with command register

◆ GPMC_TransactionStatus

enum GPMC_TransactionStatus

Transaction status codes that are set by the GPMC driver.

Enumerator
GPMC_TRANSFER_COMPLETED
GPMC_TRANSFER_STARTED
GPMC_TRANSFER_CANCELED
GPMC_TRANSFER_FAILED
GPMC_TRANSFER_CSN_DEASSERT
GPMC_TRANSFER_TIMEOUT

Function Documentation

◆ GPMC_Params_init()

static void GPMC_Params_init ( GPMC_Params * params )

inlinestatic

Function to initialize the GPMC_Params struct to its defaults.

Parameters

params Pointer to GPMC_Params structure for initialization

◆ GPMC_init()

void GPMC_init ( void )

This function initializes the GPMC module.

◆ GPMC_deinit()

void GPMC_deinit ( void )

This function de-initializes the GPMC module.

◆ GPMC_open()

GPMC_Handle GPMC_open	(	uint32_t	index,
		const GPMC_Params *	prms
	)

This function opens a given GPMC peripheral.

Precondition: GPMC controller has been initialized using GPMC_init()

Parameters

index	Index of config to use in the GPMC_Config array
prms	Pointer to parameters GPMC_Params to open the driver instance.

Returns: A GPMC_Handle on success or a NULL on an error or if it has been opened already

See also: GPMC_init(); GPMC_close()

◆ GPMC_close()

void GPMC_close ( GPMC_Handle handle )

Function to close a GPMC peripheral specified by the GPMC handle.

Precondition: GPMC_open() has to be called first

Parameters

handle GPMC_Handle returned from GPMC_open()

See also: GPMC_open()

◆ GPMC_getInputClk()

uint32_t GPMC_getInputClk ( GPMC_Handle handle )

This function returns the input clk frequency GPMC was programmed at.

Precondition: GPMC controller has been opened using GPMC_open()

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: GPMC RCLK in Hertz

◆ GPMC_getHandle()

GPMC_Handle GPMC_getHandle ( uint32_t driverInstanceIndex )

This function returns the handle of an open GPMC Instance from the instance index.

Precondition: GPMC controller has been opened using GPMC_open()

Parameters

driverInstanceIndex Index of config to use in the GPMC_Config array

Returns: An GPMC_Handle if it has been opened already or NULL otherwise

See also: GPMC_init(); GPMC_open()

◆ GPMC_writeNandCommandParamsInit()

void GPMC_writeNandCommandParamsInit ( GPMC_nandCmdParams * cmdParams )

Function to initialise GPMC_nandCmdParams structure to default values.

Parameters

cmdParams Pointer to GPMC_nandCmdParams structure

◆ GPMC_writeNandCommand()

int32_t GPMC_writeNandCommand	(	GPMC_Handle	handle,
		GPMC_nandCmdParams *	cmdParams
	)

Function to write NAND command parameters.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
cmdParams	Pointer to GPMC_nandCmdParams structure

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_transactionInit()

void GPMC_transactionInit ( GPMC_Transaction * trans )

Function to initialise GPMC_Transaction structure to default values.

Parameters

trans Pointer to GPMC_Transaction structure

◆ GPMC_nandReadData()

int32_t GPMC_nandReadData	(	GPMC_Handle	handle,
		GPMC_Transaction *	trans
	)

Function to read data from NAND flash using DMA or CPU prefetch/post write engine.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
trans	Pointer to GPMC_Transaction structure

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_nandWriteData()

int32_t GPMC_nandWriteData	(	GPMC_Handle	handle,
		GPMC_Transaction *	trans
	)

Function to write data to NANDflash using CPU prefetch/post write engine.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
trans	Pointer to GPMC_Transaction structure

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_setDeviceSize()

int32_t GPMC_setDeviceSize ( GPMC_Handle handle )

Function to set device width for GPMC instance connected to external device.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_setDeviceType()

int32_t GPMC_setDeviceType ( GPMC_Handle handle )

Function to set device type (NANDLIKE OR NORLIKE) for GPMC instance connected to external device.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_configureTimingParameters()

int32_t GPMC_configureTimingParameters ( GPMC_Handle handle )

Function to configure GPMC timing parameters.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_configureTimingParametersPsram()

int32_t GPMC_configureTimingParametersPsram ( GPMC_Handle handle )

Function to configure GPMC timing parameters for PSRAM/NOR Devices.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccValueSizeSet()

int32_t GPMC_eccValueSizeSet	(	GPMC_Handle	handle,
		uint32_t	eccSize,
		uint32_t	eccSizeVal
	)

Function to set ECC used and unused bytes size in nibbles.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
eccSize	Param to set GPMC_ECC_SIZE_0 (used bytes) or GPMC_ECC_SIZE_1 unused bytes
eccSizeVal	ECC used or ununsed bytes value in nibbles.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccBchConfigureElm()

int32_t GPMC_eccBchConfigureElm	(	GPMC_Handle	handle,
		uint8_t	numSectors
	)

Function to configure ELM module for error correction.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
numSectors	Number of 512 bytes sector in a NAND page.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccEngineBCHConfig()

int32_t GPMC_eccEngineBCHConfig	(	GPMC_Handle	handle,
		uint32_t	eccSteps
	)

Function to configure GPMC ECC engine for BCH algorithm.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
eccSteps	Number of 512 bytes sectors to process BCH syndrome polynomial computation.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccEngineEnable()

int32_t GPMC_eccEngineEnable ( GPMC_Handle handle )

Function to enable GPMC ECC engine.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccResultRegisterClear()

void GPMC_eccResultRegisterClear ( GPMC_Handle handle )

Function to clear GPMC ECC result register.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

◆ GPMC_eccBchFillSyndromeValue()

int32_t GPMC_eccBchFillSyndromeValue	(	GPMC_Handle	handle,
		uint32_t	sector,
		uint32_t *	bchData
	)

Function to fill BCH syndrome value per sector to ELM module.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number
bchData	Pointer to syndrome polynomial value.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccBchStartErrorProcessing()

int32_t GPMC_eccBchStartErrorProcessing	(	GPMC_Handle	handle,
		uint8_t	sector
	)

Function to start error processing for a sector by ELM module.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccBchCheckErrorProcessingStatus()

int32_t GPMC_eccBchCheckErrorProcessingStatus	(	GPMC_Handle	handle,
		uint32_t	sector
	)

Function to get error processing status for a sector by ELM module.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccBchSectorGetError()

int32_t GPMC_eccBchSectorGetError	(	GPMC_Handle	handle,
		uint32_t	sector,
		uint32_t *	errCount,
		uint32_t *	errLoc
	)

Function to get number of errors per sector by ELM module.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number
errCount	Pointer to store number of errors in a sector
errLoc	Pointer to store error locations in a sector

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccCalculateBchSyndromePolynomial()

int32_t GPMC_eccCalculateBchSyndromePolynomial	(	GPMC_Handle	handle,
		uint8_t *	pEccdata,
		uint32_t	sector
	)

Function to compute BCH syndrome polynomial for NAND write operation.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number
pEccdata	Pointer to store BCH syndrome polynomial.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_eccGetBchSyndromePolynomial()

int32_t GPMC_eccGetBchSyndromePolynomial	(	GPMC_Handle	handle,
		uint32_t	sector,
		uint32_t *	bchData
	)

Function to get BCH syndrome polynomial per sector NAND read operation.

Parameters

handle	An GPMC_Handle returned from an GPMC_open()
sector	Sector number
bchData	Pointer to store BCH syndrome polynomial.

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_configurePrefetchPostWriteEngine()

int32_t GPMC_configurePrefetchPostWriteEngine ( GPMC_Handle handle )

Function to configure GPMC PREFETCH read and POST write engine.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_disableFlashWriteProtect()

int32_t GPMC_disableFlashWriteProtect ( GPMC_Handle handle )

Function to disable WRITE protect line.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

◆ GPMC_enableFlashWriteProtect()

int32_t GPMC_enableFlashWriteProtect ( GPMC_Handle handle )

Function to disable WRITE protect line.

Parameters

handle An GPMC_Handle returned from an GPMC_open()

Returns: SystemP_SUCCESS or SystemP_FAILURE

Variable Documentation

◆ gGpmcConfig

GPMC_Config gGpmcConfig[]

extern

Externally defined driver configuration array.

◆ gGpmcConfigNum

uint32_t gGpmcConfigNum

extern

Externally defined driver configuration array size.

Introduction

Data Structures

Functions

Typedefs

Enumerations

Macros

Macro Definition Documentation

◆ GPMC_CHIP_SELECT_CS0

◆ GPMC_CHIP_SELECT_CS1

◆ GPMC_CHIP_SELECT_CS2

◆ GPMC_CHIP_SELECT_CS3

◆ GPMC_FIFOEVENT_STATUS

◆ GPMC_TERMINALCOUNT_STATUS

◆ GPMC_WAIT0EDGEDETECTION_STATUS

◆ GPMC_WAIT1EDGEDETECTION_STATUS

◆ GPMC_FIFOEVENT_INT

◆ GPMC_TERMINALCOUNT_INT

◆ GPMC_WAIT0EDGEDETECTION_INT

◆ GPMC_WAIT1EDGEDETECTION_INT

◆ GPMC_PREFETCH_ACCESSMODE_READ

◆ GPMC_PREFETCH_ACCESSMODE_WRITE

◆ GPMC_ECC_ALGORITHM_HAMMINGCODE

◆ GPMC_ECC_ALGORITHM_BCH

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS

◆ GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS

◆ GPMC_ECCPOINTER_RESULT_1

◆ GPMC_ECCPOINTER_RESULT_2

◆ GPMC_ECCPOINTER_RESULT_3

◆ GPMC_ECCPOINTER_RESULT_4

◆ GPMC_ECCPOINTER_RESULT_5

◆ GPMC_ECCPOINTER_RESULT_6

◆ GPMC_ECCPOINTER_RESULT_7

◆ GPMC_ECCPOINTER_RESULT_8

◆ GPMC_ECCPOINTER_RESULT_9

◆ GPMC_ECC_SIZE_0

◆ GPMC_ECC_SIZE_1

◆ GPMC_ECC_RESULT_1

◆ GPMC_ECC_RESULT_2

◆ GPMC_ECC_RESULT_3

◆ GPMC_ECC_RESULT_4

◆ GPMC_ECC_RESULT_5

◆ GPMC_ECC_RESULT_6

◆ GPMC_ECC_RESULT_7

◆ GPMC_ECC_RESULT_8

◆ GPMC_ECC_RESULT_9

◆ GPMC_BCH_RESULT0

◆ GPMC_BCH_RESULT1

◆ GPMC_BCH_RESULT2

◆ GPMC_BCH_RESULT3

◆ GPMC_BCH_RESULT4

◆ GPMC_BCH_RESULT5

◆ GPMC_BCH_RESULT6

◆ GPMC_CS_MASK_ADDR_SIZE_256MB

◆ GPMC_CS_MASK_ADDR_SIZE_128MB

◆ GPMC_CS_MASK_ADDR_SIZE_64MB

◆ GPMC_CS_MASK_ADDR_SIZE_32MB

◆ GPMC_CS_MASK_ADDR_SIZE_16MB

◆ GPMC_CS_TIMING_CONFIG

◆ GPMC_ADV_TIMING_CONFIG

◆ GPMC_WE_OE_TIMING_CONFIG

◆ GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG

◆ GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG

◆ GPMC_NAND_CS_ON_TIME

◆ GPMC_NAND_WE_ON_TIME

◆ GPMC_NAND_ADV_ON_TIME

◆ GPMC_NAND_CS_WR_OFF_TIME

◆ GPMC_NAND_WR_CYCLE_TIME

◆ GPMC_NAND_ADV_WR_OFF_TIME

◆ GPMC_NAND_CS_RD_OFF_TIME

◆ GPMC_NAND_RD_CYCLE_TIME

◆ GPMC_NAND_ADV_AADMUX_ON_TIME

◆ GPMC_NAND_ADV_AADMUX_RD_OFF_TIME

◆ GPMC_NAND_ADV_AADMUX_WR_OFF_TIME

◆ GPMC_NAND_PAGEBURST_ACCESS_TIME

◆ GPMC_NAND_OE_ON_TIME

◆ GPMC_NAND_OE_OFF_TIME

◆ GPMC_NAND_OE_AADMUX_ON_TIME

◆ GPMC_NAND_OE_AADMUX_OFF_TIME

◆ GPMC_NAND_ADV_RD_OFF_TIME