For more details and example usage, see SOC
Data Structures | |
struct | SOC_RcmClkSrcInfo |
struct | SOC_RcmXTALInfo |
struct | SOC_RcmADPLLJConfig_t |
struct | SOC_RcmPllHsDivOutConfig |
Functions | |
void | SOC_rcmCoreApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
Configure CORE PLL. More... | |
uint32_t | SOC_rcmCoreApllRelockPreRequisite (void) |
Pre-requisite sequence to Re-configure CORE PLL. More... | |
void | SOC_rcmSetR5ClockSource (uint32_t r5ClkSrc) |
Set R5 clock source. More... | |
void | SOC_rcmCoreApllHSDivConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
Configure CORE PLL HSDIVIDERS. More... | |
void | SOC_rcmPerApllConfig (SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg) |
Configure PER PLL. More... | |
void | SOC_rcmsetR5SysClock (uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId) |
Set R5FSS and Sysclk frequency (Root clock configuration) More... | |
void | SOC_rcmsetTraceClock (uint32_t traceFreqHz) |
Set Trace clock frequency. More... | |
void | SOC_rcmsetClkoutClock (uint32_t clkout0FreqHz, uint32_t clkout1FreqHz) |
Set CLKOUT clock frequency. More... | |
int32_t | SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz) |
Set module clock (IP clock configuration) More... | |
SOC_RcmResetCause | SOC_rcmGetResetCause (SOC_Rcmr5fssNum r5fssNum) |
Get R5FSS reset cause. More... | |
int32_t | SOC_rcmEnablePeripheralClock (SOC_RcmPeripheralId periphId, uint32_t enable) |
Enable/disable module clock (IP clock configuration) More... | |
int32_t | SOC_rcmSetR5Clock (uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId) |
Set R5SS0/R5SS1 and SysClk frequency. More... | |
uint32_t | SOC_rcmGetR5Clock (uint32_t cpuId) |
Get R5SS0/1 frequency. More... | |
void | SOC_rcmR5ConfigLockStep (uint32_t cpuId) |
Configure R5 in lock step mode. More... | |
void | SOC_rcmR5ConfigDualCore (uint32_t cpuId) |
Configure R5 in dual core mode. More... | |
void | SOC_rcmR5SS0TriggerReset (void) |
Trigger R5 core reset. More... | |
void | SOC_rcmCoreR5FUnhalt (uint32_t cpuId) |
Unhalt R5 cores. More... | |
void | SOC_rcmStartMemInitTCMA (uint32_t cpuId) |
Start memory initialization for R5 TCMA. More... | |
void | SOC_rcmWaitMemInitTCMA (uint32_t cpuId) |
Wait memory initialization to complete for R5 TCMA. More... | |
void | SOC_rcmStartMemInitTCMB (uint32_t cpuId) |
Start memory initialization for R5 TCMB. More... | |
void | SOC_rcmWaitMemInitTCMB (uint32_t cpuId) |
Wait memory initialization to complete for R5 TCMB. More... | |
void | SOC_rcmMemInitMailboxMemory (void) |
Wait memory initialization to complete for Mailbox memory. More... | |
void | SOC_rcmMemInitL2Memory (void) |
Wait memory initialization to complete for L2 Bank2 and Bank3 memory. More... | |
void | SOC_rcmR5SS0PowerOnReset (void) |
Reset R5SS0 Core. More... | |
void | SOC_rcmR5SS1TriggerReset (void) |
Trigger R5SS1 core reset. More... | |
void | SOC_rcmR5SS1PowerOnReset (void) |
Reset R5SS1 Core. More... | |
uint32_t | SOC_rcmIsR5FInLockStepMode (uint32_t r5fClusterGroupId) |
Return R5SS status operating in lockstep or dual core mode. More... | |
void | SOC_generateSwWarmReset (void) |
Generate SW WARM reset. More... | |
void | SOC_configureWarmResetSource (uint32_t source) |
Configure WARM reset source. More... | |
SOC_WarmResetCause | SOC_getWarmResetCause (void) |
Returns cause of WARM reset. More... | |
void | SOC_clearWarmResetCause (void) |
Clear Reset Cause register. More... | |
void | SOC_configureWarmResetOutputDelay (uint16_t opDelayValue) |
Program output delay on warm reset Pad 1. More... | |
void | SOC_configureWarmResetInputRiseDelay (uint16_t inpRiseDelayValue) |
Program input rise delay on warm reset Pad 2. More... | |
void | SOC_configureWarmResetInputFallDelay (uint16_t inpFallDelayValue) |
Program output delay on warm reset Pad 3. More... | |
Macros | |
#define | SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000) |
#define | SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000)) |
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U) |
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U) |
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U) |
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U) |
#define | RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL |
#define | RCM_PLL_HSDIV_OUTPUT_IDX0 (0) |
#define | RCM_PLL_HSDIV_OUTPUT_IDX1 (1) |
#define | RCM_PLL_HSDIV_OUTPUT_IDX2 (2) |
#define | RCM_PLL_HSDIV_OUTPUT_IDX3 (3) |
#define | RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1) |
SOC Warm Reset Causes | |
enum | SOC_WarmResetCause { SOC_WarmResetCause_POWER_ON_RESET = 0x41U, SOC_WarmResetCause_MSS_WDT0 = 0x42U, SOC_WarmResetCause_MSS_WDT1 = 0x44U, SOC_WarmResetCause_MSS_WDT2 = 0x48U, SOC_WarmResetCause_MSS_WDT3 = 0x50U, SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ = 0x60U, SOC_WarmResetCause_EXT_PAD_RESET = 0x40U, SOC_WarmResetCause_HSM_WDT = 0xC0U, SOC_WarmResetCause_DBG_RESET = 0x140U, SOC_WarmResetCause_TEMP_SENSOR0_RESET = 0x240U, SOC_WarmResetCause_TEMP_SENSOR1_RESET = 0x440U } |
SOC RCM Reset Causes | |
enum | SOC_RcmResetCause { SOC_RcmResetCause_POWER_ON_RESET = 0x0U, SOC_RcmResetCause_WARM_RESET = 0x1U, SOC_RcmResetCause_STC_RESET = 0x2U, SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U, SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U, SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U, SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U, SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U, SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U, SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U, SOC_RcmResetCause_POR_RST_CTRL0 = 0xAU, SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xBU } |
SOC R5F subsystems | |
enum | SOC_Rcmr5fssNum { r5fss0 = 0x0U, r5fss1 = 0x1U } |
SOC PLL frequency output IDs | |
enum | SOC_RcmPllFoutFreqId { RCM_PLL_FOUT_FREQID_CLK_2000MHZ, RCM_PLL_FOUT_FREQID_CLK_1920MHZ } |
SOC XTAL frequency IDs | |
enum | SOC_RcmXtalFreqId { RCM_XTAL_FREQID_CLK_25MHZ } |
enum | SOC_RcmPllId { RCM_PLLID_CORE, RCM_PLLID_PER, RCM_PLLID_XTALCLK, RCM_PLLID_WUCPUCLK, RCM_PLLID_RCCLK32K, RCM_PLLID_RCCLK10M, RCM_PLLID_EXTREFCLK } |
SOC HSDIVIDER IDs | |
enum | SOC_RcmPllHSDIVOutId { RCM_PLLHSDIV_OUT_0, RCM_PLLHSDIV_OUT_1, RCM_PLLHSDIV_OUT_2, RCM_PLLHSDIV_OUT_NONE } |
#define SOC_RCM_FREQ_MHZ2HZ | ( | x | ) | ((x) * 1000 * 1000) |
#define SOC_RCM_FREQ_HZ2MHZ | ( | x | ) | ((x) / (1000 * 1000)) |
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U) |
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U) |
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U) |
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U) |
#define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL |
#define RCM_PLL_HSDIV_OUTPUT_IDX0 (0) |
#define RCM_PLL_HSDIV_OUTPUT_IDX1 (1) |
#define RCM_PLL_HSDIV_OUTPUT_IDX2 (2) |
#define RCM_PLL_HSDIV_OUTPUT_IDX3 (3) |
#define RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1) |
enum SOC_WarmResetCause |
enum SOC_RcmResetCause |
enum SOC_Rcmr5fssNum |
enum SOC_RcmPeripheralId |
enum SOC_RcmPllFoutFreqId |
enum SOC_RcmXtalFreqId |
enum SOC_RcmPllId |
enum SOC_RcmPllHSDIVOutId |
void SOC_rcmCoreApllConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
) |
Configure CORE PLL.
outFreqId | [in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId |
*hsDivCfg | [in] HSDIVIDER configuration |
uint32_t SOC_rcmCoreApllRelockPreRequisite | ( | void | ) |
Pre-requisite sequence to Re-configure CORE PLL.
void SOC_rcmSetR5ClockSource | ( | uint32_t | r5ClkSrc | ) |
Set R5 clock source.
void SOC_rcmCoreApllHSDivConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
) |
Configure CORE PLL HSDIVIDERS.
outFreqId | [in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId |
*hsDivCfg | [in] HSDIVIDER configuration |
void SOC_rcmPerApllConfig | ( | SOC_RcmPllFoutFreqId | outFreqId, |
SOC_RcmPllHsDivOutConfig * | hsDivCfg | ||
) |
Configure PER PLL.
outFreqId | [in] PLL output frequency ID. Enumberation: SOC_RcmPllFoutFreqId |
*hsDivCfg | [in] HSDIVIDER configuration |
void SOC_rcmsetR5SysClock | ( | uint32_t | cr5FreqHz, |
uint32_t | sysClkFreqHz, | ||
uint32_t | cpuId | ||
) |
Set R5FSS and Sysclk frequency (Root clock configuration)
cr5FreqHz | [in] R5F frequency |
sysClkFreqHz | [in] SYSCLK frequency |
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmsetTraceClock | ( | uint32_t | traceFreqHz | ) |
Set Trace clock frequency.
traceFreqHz | [in] Trace frequency |
void SOC_rcmsetClkoutClock | ( | uint32_t | clkout0FreqHz, |
uint32_t | clkout1FreqHz | ||
) |
Set CLKOUT clock frequency.
clkout0FreqHz | [in] CLKOUT0 frequency |
clkout1FreqHz | [in] CLKOUT1 frequency |
int32_t SOC_rcmSetPeripheralClock | ( | SOC_RcmPeripheralId | periphId, |
SOC_RcmPeripheralClockSource | clkSource, | ||
uint32_t | freqHz | ||
) |
Set module clock (IP clock configuration)
This API programs the Clock Source Selection and Clock divider values for a specified peripheral Id.
periphId | [in] Peripheral ID |
clkSource | [in] Clock source |
freqHz | [in] Frequency |
SOC_RcmResetCause SOC_rcmGetResetCause | ( | SOC_Rcmr5fssNum | r5fssNum | ) |
Get R5FSS reset cause.
This API returns the reset cause for R5 core. It also clears the Reset cause.
r5fssNum | [in] R5FSS0 or R5FSS1 |
int32_t SOC_rcmEnablePeripheralClock | ( | SOC_RcmPeripheralId | periphId, |
uint32_t | enable | ||
) |
Enable/disable module clock (IP clock configuration)
This API programs the IP clock gates for a specified peripheral Id.
periphId | [in] Peripheral ID |
enable | [in] ungate (1)/gate clock (0) |
int32_t SOC_rcmSetR5Clock | ( | uint32_t | r5FreqHz, |
uint32_t | sysClkFreqHz, | ||
uint32_t | cpuId | ||
) |
Set R5SS0/R5SS1 and SysClk frequency.
r5FreqHz | [in] R5 frequency, in Hz |
sysClkFreqHz | [in] SysClk frequency, in Hz |
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
uint32_t SOC_rcmGetR5Clock | ( | uint32_t | cpuId | ) |
Get R5SS0/1 frequency.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmR5ConfigLockStep | ( | uint32_t | cpuId | ) |
Configure R5 in lock step mode.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmR5ConfigDualCore | ( | uint32_t | cpuId | ) |
Configure R5 in dual core mode.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmR5SS0TriggerReset | ( | void | ) |
Trigger R5 core reset.
void SOC_rcmCoreR5FUnhalt | ( | uint32_t | cpuId | ) |
Unhalt R5 cores.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmStartMemInitTCMA | ( | uint32_t | cpuId | ) |
Start memory initialization for R5 TCMA.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmWaitMemInitTCMA | ( | uint32_t | cpuId | ) |
Wait memory initialization to complete for R5 TCMA.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmStartMemInitTCMB | ( | uint32_t | cpuId | ) |
Start memory initialization for R5 TCMB.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmWaitMemInitTCMB | ( | uint32_t | cpuId | ) |
Wait memory initialization to complete for R5 TCMB.
cpuId | [in] Cpu Id. Refer CSL_CoreID for applicable values. |
void SOC_rcmMemInitMailboxMemory | ( | void | ) |
Wait memory initialization to complete for Mailbox memory.
void SOC_rcmMemInitL2Memory | ( | void | ) |
Wait memory initialization to complete for L2 Bank2 and Bank3 memory.
void SOC_rcmR5SS0PowerOnReset | ( | void | ) |
Reset R5SS0 Core.
void SOC_rcmR5SS1TriggerReset | ( | void | ) |
Trigger R5SS1 core reset.
void SOC_rcmR5SS1PowerOnReset | ( | void | ) |
Reset R5SS1 Core.
uint32_t SOC_rcmIsR5FInLockStepMode | ( | uint32_t | r5fClusterGroupId | ) |
Return R5SS status operating in lockstep or dual core mode.
r5fClusterGroupId | [in] R5F Cluster Group Id. Refer CSL_ArmR5ClusterGroupID for applicable values. |
void SOC_generateSwWarmReset | ( | void | ) |
Generate SW WARM reset.
void SOC_configureWarmResetSource | ( | uint32_t | source | ) |
Configure WARM reset source.
source | [in] WARM reset source. User needs to set the source as multibit and program only the required fields. |
SOC_WarmResetCause SOC_getWarmResetCause | ( | void | ) |
Returns cause of WARM reset.
void SOC_clearWarmResetCause | ( | void | ) |
Clear Reset Cause register.
void SOC_configureWarmResetOutputDelay | ( | uint16_t | opDelayValue | ) |
Program output delay on warm reset Pad 1.
opDelayValue | [in] Programmable delay value. Refer SOC_RcmWarm_ResetTime123_t |
void SOC_configureWarmResetInputRiseDelay | ( | uint16_t | inpRiseDelayValue | ) |
Program input rise delay on warm reset Pad 2.
inpRiseDelayValue | [in] Programmable delay value. Refer SOC_RcmWarm_ResetTime123_t |
void SOC_configureWarmResetInputFallDelay | ( | uint16_t | inpFallDelayValue | ) |
Program output delay on warm reset Pad 3.
inpFallDelayValue | [in] Programmable delay value. Refer SOC_RcmWarm_ResetTime123_t |