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AM263x MCU+ SDK
08.05.00
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39 #ifndef SDL_MSS_CR5_SOC_H_
40 #define SDL_MSS_CR5_SOC_H_
46 #include <sdl/include/am263x/sdlr_soc_baseaddress.h>
47 #include <sdl/include/am263x/sdlr_mss_ctrl.h>
56 #define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
58 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)
59 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)
60 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)
61 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)
62 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)
63 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)
64 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)
65 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)
67 #define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020)
68 #define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020)
69 #define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )
70 #define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )
71 #define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)
72 #define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)
73 #define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+100U)