#define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE |
#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U) |
#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U) |
#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U) |
#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U) |
#define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE) |
#define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE) |
#define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE) |
#define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE) |
#define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020) |
#define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020) |
#define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE ) |
#define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE ) |
#define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE) |
#define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE) |
#define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE+100U) |