For more details and example usage, see Cache
Data Structures | |
struct | CacheP_Config |
Cache config structure, this used by SysConfig and not to be used by end-users directly. More... | |
Functions | |
void | CacheP_enable (uint32_t type) |
Cache enable. More... | |
void | CacheP_disable (uint32_t type) |
Cache disable. More... | |
uint32_t | CacheP_getEnabled () |
Get cache enabled bits. More... | |
void | CacheP_wbAll (uint32_t type) |
Cache writeback for full cache. More... | |
void | CacheP_wbInvAll (uint32_t type) |
Cache writeback and invalidate for full cache. More... | |
void | CacheP_wb (void *addr, uint32_t size, uint32_t type) |
Cache writeback for a specified region. More... | |
void | CacheP_inv (void *addr, uint32_t size, uint32_t type) |
Cache invalidate for a specified region. More... | |
void | CacheP_wbInv (void *addr, uint32_t size, uint32_t type) |
Cache writeback and invalidate for a specified region. More... | |
void | CacheP_init () |
Initialize Cache sub-system, called by SysConfig, not to be called by end users. More... | |
Enumerations | |
enum | CacheP_Type { CacheP_TYPE_L1P = (0x0001u), CacheP_TYPE_L1D = (0x0002u), CacheP_TYPE_L2P = (0x0004u), CacheP_TYPE_L2D = (0x0008u), CacheP_TYPE_L1 = (CacheP_TYPE_L1P|CacheP_TYPE_L1D), CacheP_TYPE_L2 = (CacheP_TYPE_L2P|CacheP_TYPE_L2D), CacheP_TYPE_ALLP = (CacheP_TYPE_L1P|CacheP_TYPE_L2P), CacheP_TYPE_ALLD = (CacheP_TYPE_L1D|CacheP_TYPE_L2D), CacheP_TYPE_ALL = (CacheP_TYPE_L1|CacheP_TYPE_L2) } |
Cache type. More... | |
Macros | |
#define | CacheP_CACHELINE_ALIGNMENT (128U) |
Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's. More... | |
#define CacheP_CACHELINE_ALIGNMENT (128U) |
Cache line size for alignment of buffers. Actual CPU defined cache line can be smaller that this value, this define is a utility macro to keep application portable across different CPU's.
enum CacheP_Type |
Cache type.
void CacheP_enable | ( | uint32_t | type | ) |
Cache enable.
type | [in] cache type's to enable, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_disable | ( | uint32_t | type | ) |
Cache disable.
type | [in] cache type's to disable, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
uint32_t CacheP_getEnabled | ( | ) |
Get cache enabled bits.
void CacheP_wbAll | ( | uint32_t | type | ) |
Cache writeback for full cache.
type | [in] cache type's to writeback, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wbInvAll | ( | uint32_t | type | ) |
Cache writeback and invalidate for full cache.
type | [in] cache type's to writeback and invalidate, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wb | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache writeback for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to writeback, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_inv | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache invalidate for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to invalidate, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_wbInv | ( | void * | addr, |
uint32_t | size, | ||
uint32_t | type | ||
) |
Cache writeback and invalidate for a specified region.
addr | [in] region address. Recommend to specify address that is cache line aligned |
size | [in] region size in bytes. Recommend to specify size that is multiple of cache line size |
type | [in] cache type's to writeback and invalidate, refer CacheP_Type R5: Supports CacheP_TYPE_L1P, CacheP_TYPE_L1D, A53: Supports CacheP_TYPE_L1P , CacheP_TYPE_L2P, CacheP_TYPE_L1D and CacheP_TYPE_L2D, C66x: Not used assumes CacheP_TYPE_ALL, M4: Not supported |
void CacheP_init | ( | ) |
Initialize Cache sub-system, called by SysConfig, not to be called by end users.
|
extern |
Externally defined Cache configuration.