AM263x MCU+ SDK  08.05.00
ECC : Error Correcting Code

Table of Contents

To increase functional and system reliability, the memories in many device modules and subsystems are protected by Error Correcting Code (ECC), which performs Single Error Correction (SEC) and Double Error Detection (DED). Detected errors are reported via ESM. Single bit errors are corrected, and double bit errors are detected. The ECC Aggregator is connected to these memory and interconnect components which have the ECC. The ECC aggregator provides access to control and monitor the ECC protected memories in a module or subsystem.

SDL provides support for ECC aggregator configuration. Each ECC aggregator instance can be independently configured through the same SDL API by passing a different instance. The safety manual also defines test-for-diagnostics for the various IPs with ECC/parity support. The SDL also provides the support for executing ECC aggregator self-tests, using the error injection feature of the ECC aggregator. The ECC aggregators should be configured at startup, after running BIST.

Features Supported

The SDL provides support for the ECC through:

  • ECC Configuration API
  • ECC self-test API
  • ECC error injection API
  • ECC static register readback API

  • ECC error status APIs

    The SDL ECC module requires a mapping of certain aggregator registers into the address space of the R5F Core. In these cases, the ECC module will use the DPL API SDL_DPL_addrTranslate() to get the address. The application must provide the mapped address through this call. This mapping is required for any ECC aggregator that is used which has an address which is not in the 32-bit address space. The mapping is expected to always be valid because it may be needed at runtime to get information about ECC errors that may be encountered.

There are over 13 ECC aggregators on the device each supporting multiple memories and interconnects.

Error Injection for Various RAM ID types

There are two types of ECC aggregator RAM IDs supported on the device (wrapper and interconnect). The wrapper types are used for memories where local computations are performed for particular processing cores in the device, and the interconnect types are utilized for interconnect bus signals between cores or to/from peripherals.

For wrapper RAM ID types, after injecting an error, the memory associated with that RAM ID needs to be accessed in order to trigger the error interrupt event. It is the application's responsibility to trigger the error event through memory access after injecting the error.

SysConfig Features

  • None

Features NOT Supported

  • None

Important Usage Guidelines

  • None

Example Usage of R5F ATCM0

The following shows an example of SDL R5F ECC API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include <sdl/sdl_exception.h>
#include <sdl/r5/v0/interrupt.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x00000510u) // R5F ATCM0 RAM address
#define SDL_EXAMPLE_ECC_AGGR SDL_R5FSS0_CORE0_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
int32_t retVal = 0;
uint32_t rd_data = 0;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x \r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
/* Clear DED MSS_CTRL register*/
SDL_REG32_WR(0x50D18094u, 0x01);
rd_data = SDL_REG32_RD(0x50D18094u);
printf("\r\nRead data of DED MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear DED RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18098u, 0x01);
rd_data = SDL_REG32_RD(0x50D18098u);
printf("\r\nRead data of DED RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
/* Clear SEC MSS_CTRL register*/
SDL_REG32_WR(0x50D18088u, 0x01);
rd_data = SDL_REG32_RD(0x50D18088u);
printf("\r\nRead data of SEC MSS_CTRL register is 0x%u\r\n",rd_data);
/* Clear SEC RAW MSS_CTRL register*/
SDL_REG32_WR(0x50D18084u, 0x01);
rd_data = SDL_REG32_RD(0x50D18084u);
printf("\r\nRead data of SEC RAW MSS_CTRL register is 0x%u\r\n",rd_data);
}
esmError = true;
return retVal;
}

This is the list of exception handle and the parameters

const SDL_R5ExptnHandlers ECC_Test_R5ExptnHandlers =
{
.udefExptnHandler = &SDL_EXCEPTION_undefInstructionExptnHandler,
.swiExptnHandler = &SDL_EXCEPTION_swIntrExptnHandler,
.pabtExptnHandler = &SDL_EXCEPTION_prefetchAbortExptnHandler,
.dabtExptnHandler = &SDL_EXCEPTION_dataAbortExptnHandler,
.irqExptnHandler = &SDL_EXCEPTION_irqExptnHandler,
.fiqExptnHandler = &SDL_EXCEPTION_fiqExptnHandler,
.udefExptnHandlerArgs = ((void *)0u),
.swiExptnHandlerArgs = ((void *)0u),
.pabtExptnHandlerArgs = ((void *)0u),
.dabtExptnHandlerArgs = ((void *)0u),
.irqExptnHandlerArgs = ((void *)0u),
};

Below are the functions used to print the which exception is occured

void ECC_Test_undefInstructionExptnCallback(void)
{
printf("\r\nUndefined Instruction exception\r\n");
}
void ECC_Test_swIntrExptnCallback(void)
{
printf("\r\nSoftware interrupt exception\r\n");
}
void ECC_Test_prefetchAbortExptnCallback(void)
{
printf("\r\nPrefetch Abort exception\r\n");
}
void ECC_Test_dataAbortExptnCallback(void)
{
printf("\r\nData Abort exception\r\n");
}
void ECC_Test_irqExptnCallback(void)
{
printf("\r\nIrq exception\r\n");
}
void ECC_Test_fiqExptnCallback(void)
{
printf("\r\nFiq exception\r\n");
}

Initilize Exception handler

void ECC_Test_exceptionInit(void)
{
SDL_EXCEPTION_CallbackFunctions_t exceptionCallbackFunctions =
{
.udefExptnCallback = ECC_Test_undefInstructionExptnCallback,
.swiExptnCallback = ECC_Test_swIntrExptnCallback,
.pabtExptnCallback = ECC_Test_prefetchAbortExptnCallback,
.dabtExptnCallback = ECC_Test_dataAbortExptnCallback,
.irqExptnCallback = ECC_Test_irqExptnCallback,
.fiqExptnCallback = ECC_Test_fiqExptnCallback,
};
/* Initialize SDL exception handler */
SDL_EXCEPTION_init(&exceptionCallbackFunctions);
/* Register SDL exception handler */
Intc_RegisterExptnHandlers(&ECC_Test_R5ExptnHandlers);
return;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_R5FSS0_CORE0_subMemTypeList[SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_R5FSS0_CORE0_ECCInitConfig =
{
.numRams = SDL_R5FSS0_CORE0_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_R5FSS0_CORE0_subMemTypeList[0]),
};
SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000000u, 0x000010000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00000000u, 0x00018000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Enabling the ECC module

SDL_ECC_UTILS_enableECCATCM();

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC R5F ATCM0 single bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 1 bit error */
injectErrorConfig.flipBitMask = 0x02;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Enabling the ECC module

SDL_ECC_UTILS_enableECCATCM();

Enabling the Event bus

SDL_UTILS_enable_event_bus();

Execute ECC R5F ATCM0 double bit inject test

int32_t ECC_Test_run_R5FSS0_CORE0_ATCM0_BANK0_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: starting \r\n");
/* Run one shot test for R5FSS0 CORE0 ATCM0 BANK0 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nR5FSS0 CORE0 ATCM0 BANK0 Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Example Usage of MSS L2

The following shows an example of SDL MSS L2 API usage by the application for Error Injection Tests and Exception handling.

Include the below file to access the APIs

#include <sdl/sdl_ecc.h>
#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x70100008u) /* MSS_L2_SLV2 address */
#define SDL_EXAMPLE_ECC_AGGR SDL_SOC_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID
#define SDL_MSS_L2_MEM_INIT_ADDR (0x50D00240u)
#define SDL_MSS_L2_MEM_INIT_DONE_ADDR (0x50D00244u)
#define SDL_ECC_AGGR_ERROR_STATUS1_ADDR (0x53000020u)
#define SDL_ECC_MSS_L2_BANK_MEM_INIT (0xcu) /* Bank 3 */

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf(" \r\nTake action \r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MSS_L2_subMemTypeList[SDL_MSS_L2_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MSS_L2_ECCInitConfig =
{
.numRams = SDL_MSS_L2_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MSS_L2_subMemTypeList[0]),
};

Event BitMap for ECC ESM callback for MSS

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00180000u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x00180000u, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialization of MSS L2 memory

/* Clear Done memory*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, 0xfu);
/* Initialization of MSS L2 memory*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);
while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR)!=SDL_ECC_MSS_L2_BANK_MEM_INIT);
/* Clear Done memory after MEM init*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_R5FSS0_CORE0_ECCInitConfig);

Execute ECC MSS L2 single bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MSS L2 RAMB 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMSS L2 RAMB Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Initialization of MSS L2 memory

SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);
while(SDL_REG32_RD(SDL_MSS_L2_MEM_INIT_DONE_ADDR)!=SDL_ECC_MSS_L2_BANK_MEM_INIT);
/* Clear Done memory after MEM init*/
SDL_REG32_WR(SDL_MSS_L2_MEM_INIT_DONE_ADDR, SDL_ECC_MSS_L2_BANK_MEM_INIT);

Clearing any old interrupt presented

SDL_REG32_WR(SDL_ECC_AGGR_ERROR_STATUS1_ADDR, 0xF0Fu);

Initialize ECC Memory

SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Execute ECC MSS L2 double bit inject test

int32_t ECC_Test_run_MSS_L2RAMB_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: starting \r\n");
/* Run one shot test for MSS L2 RAMB 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x30002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMSS L2 RAMB Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Example Usage of MCAN

Include the below file to access the APIs

#include "ecc_main.h"

Below are the macros specifies the RAM address, ECC aggregator and ECC aggregator RAMID for inject the ECC error

#define SDL_EXAMPLE_ECC_RAM_ADDR (0x52600000u) /*MCAN0 address*/
#define SDL_EXAMPLE_ECC_AGGR SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR
#define SDL_EXAMPLE_ECC_RAM_ID SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID

This structure defines the elements of ECC Init configuration

static SDL_ECC_MemSubType ECC_Test_MCANA_subMemTypeList[SDL_MCANA_MAX_MEM_SECTIONS] =
{
SDL_EXAMPLE_ECC_RAM_ID,
};
static SDL_ECC_InitConfig_t ECC_Test_MCANA_ECCInitConfig =
{
.numRams = SDL_MCANA_MAX_MEM_SECTIONS,
.pMemSubTypeList = &(ECC_Test_MCANA_subMemTypeList[0]),
};

ESM callback function

int32_t SDL_ESM_applicationCallbackFunction(SDL_ESM_Inst esmInst,
SDL_ESM_IntType esmIntrType,
uint32_t grpChannel,
uint32_t index,
uint32_t intSrc,
uintptr_t *arg)
{
SDL_ECC_MemType eccmemtype;
SDL_Ecc_AggrIntrSrc eccIntrSrc;
SDL_ECC_ErrorInfo_t eccErrorInfo;
int32_t retVal;
printf("\r\nESM Call back function called : instType 0x%x, intType 0x%x, " \
"grpChannel 0x%x, index 0x%x, intSrc 0x%x\r\n",
esmInst, esmIntrType, grpChannel, index, intSrc);
printf("\r\nTake action\r\n");
if(esmIntrType == 1u){
printf("\r\nHigh Priority Interrupt Executed\r\n");
}
else{
printf("\r\nLow Priority Interrupt Executed\r\n");
}
retVal = SDL_ECC_getESMErrorInfo(esmInst, intSrc, &eccmemtype, &eccIntrSrc);
/* Any additional customer specific actions can be added here */
retVal = SDL_ECC_getErrorInfo(eccmemtype, eccIntrSrc, &eccErrorInfo);
printf("\r\nECC Error Call back function called : eccMemType %d, errorSrc 0x%x, " \
"ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\r\n",
eccmemtype, eccIntrSrc, eccErrorInfo.memSubType, (uint32_t)(eccErrorInfo.bitErrorOffset >> 32),
(uint32_t)(eccErrorInfo.bitErrorOffset & 0x00000000FFFFFFFF), eccErrorInfo.bitErrorGroup);
if (eccErrorInfo.injectBitErrCnt != 0)
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT, eccErrorInfo.injectBitErrCnt);
}
else
{
SDL_ECC_clearNIntrPending(eccmemtype, eccErrorInfo.memSubType, eccIntrSrc, SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL, eccErrorInfo.bitErrCnt);
}
retVal = SDL_ECC_ackIntr(eccmemtype, eccIntrSrc);
esmError = true;
return retVal;
}

Event BitMap for ECC ESM callback for MCAN

SDL_ESM_config ECC_Test_esmInitConfig_MAIN =
{
.esmErrorConfig = {1u, 8u}, /* Self test error config */
.enableBitmap = {0x0000000cu, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
/* CCM_1_SELFTEST_ERR and _R5FSS0COMPARE_ERR_PULSE_0 */
.priorityBitmap = {0x00000008u, 0x000000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u },
.errorpinBitmap = {0x0000000cu, 0x00000000u, 0x00000000u, 0x00000000u,
0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u},
};

Initialize ECC memory for the ECC aggregator

result = SDL_ECC_initMemory(SDL_EXAMPLE_ECC_AGGR, SDL_EXAMPLE_ECC_RAM_ID);

Initialize ESM module

result = SDL_ESM_init(SDL_ESM_INST_MAIN_ESM0, &ECC_Test_esmInitConfig_MAIN, SDL_ESM_applicationCallbackFunction, ptr);

Initialize ECC parameters for single and double bit error injection

result = SDL_ECC_init(SDL_EXAMPLE_ECC_AGGR, &ECC_Test_MCANA_ECCInitConfig);

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN single bit inject test

int32_t ECC_Test_run_MCANA_1BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA Single bit error inject: starting \r\n");
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
/* Run one shot test for MCANA 1 bit error */
injectErrorConfig.flipBitMask = 0x002;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
&injectErrorConfig);
if (result != SDL_PASS ) {
retVal = -1;
} else {
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
DebugP_log("\r\nMCANA Single bit error inject at pErrMem = 0x%p and the value of pErrMem is 0x%p :test complete\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

Write some data to the RAM memory before injecting

for(i=1;i<=num_of_iterations;i++){
wr_data = (i)<<24 | (i)<<16 | (i)<<8 | i;
SDL_REG32_WR(addr+i*16, wr_data);
}

Execute ECC MCAN double bit inject test

int32_t ECC_Test_run_MCANA_2BitInjectTest(void)
{
SDL_ErrType_t result;
int32_t retVal=0;
SDL_ECC_InjectErrorConfig_t injectErrorConfig;
volatile uint32_t testLocationValue;
DebugP_log("\r\nMCANA double bit error inject: starting \r\n");
/* Run one shot test for MCANA 2 bit error */
/* Note the address is relative to start of ram */
injectErrorConfig.pErrMem = (uint32_t *)(SDL_EXAMPLE_ECC_RAM_ADDR);
injectErrorConfig.flipBitMask = 0x03;
result = SDL_ECC_injectError(SDL_EXAMPLE_ECC_AGGR,
SDL_EXAMPLE_ECC_RAM_ID,
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
&injectErrorConfig);
/* Access the memory where injection is expected */
testLocationValue = injectErrorConfig.pErrMem[0];
if (result != SDL_PASS ) {
retVal = -1;
} else {
DebugP_log("\r\nMCANA Double bit error inject: pErrMem fixed location = 0x%p once test complete: the value of pErrMem is 0x%p\r\n",
injectErrorConfig.pErrMem, testLocationValue);
}
return retVal;
}

Read data from the RAM memory after injecting

for(i=1;i<=num_of_iterations;i++){
rd_data = SDL_REG32_RD(addr+i*16);
DebugP_log("\r\nRead data = 0x%p\r\n",rd_data);
}

API

ECC Aggregator (ECC_AGGR)

SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL
#define SDL_ECC_AGGR_ERROR_SUBTYPE_NORMAL
Definition: V1/sdl_ip_ecc.h:189
SDL_ECC_getErrorInfo
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ESM_IntType
SDL_ESM_IntType
Definition: sdl_esm.h:94
SDL_ECC_InitConfig_t
Definition: sdl_ecc.h:190
SDL_ECC_ErrorInfo_t::memSubType
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:220
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:191
SDL_R5ExptnHandlers
Structure containing the Exception Handlers. If application does not want register an exception handl...
Definition: sdl_interrupt.h:111
SDL_ECC_MemType
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:121
SDL_ESM_config
ESM init configuration.
Definition: sdl_esm.h:184
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
SDL_EXCEPTION_swIntrExptnHandler
void SDL_EXCEPTION_swIntrExptnHandler(void *param)
SW Interrupt Exception Handler.
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:176
SDL_EXCEPTION_undefInstructionExptnHandler
void SDL_EXCEPTION_undefInstructionExptnHandler(void *param)
Undefined Instruction Exception Handler.
SDL_ECC_getESMErrorInfo
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
SDL_EXCEPTION_prefetchAbortExptnHandler
void SDL_EXCEPTION_prefetchAbortExptnHandler(void *param)
Prefetch Abort Exception Handler.
Intc_RegisterExptnHandlers
void Intc_RegisterExptnHandlers(const SDL_R5ExptnHandlers *handlers)
This function registers handlers for various exceptions.
SDL_REG32_WR
#define SDL_REG32_WR(p, v)
This macro writes a 32-bit value to a hardware register.
Definition: sdlr.h:127
SDL_ECC_ErrorInfo_t::bitErrorGroup
uint32_t bitErrorGroup
Definition: sdl_ecc.h:228
DebugP_log
#define DebugP_log(format,...)
Function to log a string to the enabled console.
Definition: DebugP.h:211
SDL_ECC_InjectErrorConfig_t
Definition: sdl_ecc.h:203
SDL_ECC_UTILS_enableECCATCM
void SDL_ECC_UTILS_enableECCATCM(void)
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:204
SDL_EXCEPTION_irqExptnHandler
void SDL_EXCEPTION_irqExptnHandler(void *param)
IRQ Exception Handler.
SDL_ECC_ErrorInfo_t::bitErrorOffset
uint64_t bitErrorOffset
Definition: sdl_ecc.h:230
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:206
sdl_exception.h
Header file contains enumerations, structure definitions and function declarations for SDL EXCEPTION ...
SDL_EXCEPTION_init
void SDL_EXCEPTION_init(const SDL_EXCEPTION_CallbackFunctions_t *callbackFunctions)
Initialise Exception module.
SDL_EXCEPTION_CallbackFunctions_t
Structure of call back functions for various exception events.
Definition: sdl_exception.h:93
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT
#define SDL_ECC_AGGR_ERROR_SUBTYPE_INJECT
Definition: V1/sdl_ip_ecc.h:191
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:89
SDL_REG32_RD
#define SDL_REG32_RD(p)
This macro reads a 32-bit value from a hardware register and returns the value.
Definition: sdlr.h:118
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:106
SDL_ESM_config::esmErrorConfig
SDL_ESM_ErrorConfig_t esmErrorConfig
Definition: sdl_esm.h:185
SDL_ESM_init
int32_t SDL_ESM_init(SDL_ESM_Inst instance, const SDL_ESM_config *pConfig, SDL_ESM_applicationCallback applicationCallback, void *appArg)
SDL ESM API to initialize an ESM instance. The API initializes the specified ESM instance with the pr...
SDL_UTILS_enable_event_bus
void SDL_UTILS_enable_event_bus(void)
SDL_R5ExptnHandlers::udefExptnHandler
exptnHandlerPtr udefExptnHandler
Definition: sdl_interrupt.h:112
SDL_ECC_ErrorInfo_t
Definition: sdl_ecc.h:217
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SDL_ECC_ErrorInfo_t::injectBitErrCnt
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:226
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:87
SDL_ECC_clearNIntrPending
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
SDL_ECC_ErrorInfo_t::bitErrCnt
uint32_t bitErrCnt
Definition: sdl_ecc.h:224
SDL_EXCEPTION_fiqExptnHandler
void SDL_EXCEPTION_fiqExptnHandler(void *param)
FIQ Exception Handler.
SDL_EXCEPTION_dataAbortExptnHandler
void SDL_EXCEPTION_dataAbortExptnHandler(void *param)
Data Abort Exception Handler.
SDL_ECC_ackIntr
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
SDL_EXCEPTION_CallbackFunctions_t::udefExptnCallback
SDL_EXCEPTION_Callback_t udefExptnCallback
Definition: sdl_exception.h:94