![Logo](ti_logo.svg) |
AM263x MCU+ SDK
08.03.00
|
|
Go to the documentation of this file.
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_epwm.h>
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
376 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
377 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
780 #define EPWM_DB_INPUT_EPWMA (0U)
781 #define EPWM_DB_INPUT_EPWMB (1U)
783 #define EPWM_DB_INPUT_DB_RED (2U)
864 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
865 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
867 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
869 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
871 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
873 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
875 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
877 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
879 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
881 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
883 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
885 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
887 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
889 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
891 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
893 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
895 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x10000U)
897 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1000000U)
1020 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1021 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1023 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1025 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1027 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1029 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1031 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1040 #define EPWM_TZ_FLAG_CBC (0x2U)
1041 #define EPWM_TZ_FLAG_OST (0x4U)
1043 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1045 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1047 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1049 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1051 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1061 #define EPWM_TZ_INTERRUPT (0x1U)
1071 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1072 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1074 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1076 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1078 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1080 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1082 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1084 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1086 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1097 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1098 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1100 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1102 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1104 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1106 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1108 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1110 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1112 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1138 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1139 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1141 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1143 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1145 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1147 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1149 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1159 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1160 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1162 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1164 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1166 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1168 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1170 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1172 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1174 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1176 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1178 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1180 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1182 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1192 #define EPWM_INT_TBCTR_ZERO (1U)
1193 #define EPWM_INT_TBCTR_PERIOD (2U)
1195 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1197 #define EPWM_INT_TBCTR_U_CMPA (4U)
1199 #define EPWM_INT_TBCTR_U_CMPC (8U)
1201 #define EPWM_INT_TBCTR_D_CMPA (5U)
1203 #define EPWM_INT_TBCTR_D_CMPC (10U)
1205 #define EPWM_INT_TBCTR_U_CMPB (6U)
1207 #define EPWM_INT_TBCTR_U_CMPD (12U)
1209 #define EPWM_INT_TBCTR_D_CMPB (7U)
1211 #define EPWM_INT_TBCTR_D_CMPD (14U)
1221 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1222 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1224 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1226 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1228 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1230 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1232 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1234 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1236 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1238 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1240 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1348 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1349 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1351 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1353 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1355 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1357 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1359 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1361 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1363 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1365 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1367 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1369 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1371 #define EPWM_DC_COMBINATIONAL_TRIPIN13 (0x1000U)
1373 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1375 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1403 #define EPWM_DC_TBCTR_ZERO (0x1)
1404 #define EPWM_DC_TBCTR_PERIOD (0x2)
1406 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1408 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1410 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1412 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1414 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1416 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1418 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1420 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1567 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1568 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1570 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1572 #define EPWM_GL_REGISTER_CMPC (0x8U)
1574 #define EPWM_GL_REGISTER_CMPD (0x10U)
1576 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1578 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1580 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1582 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1584 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1586 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1720 #define EPWM_MINDB_BLOCK_A (0x0)
1721 #define EPWM_MINDB_BLOCK_B (0x1)
1730 #define EPWM_MINDB_NO_INVERT (0x0)
1731 #define EPWM_MINDB_INVERT (0x1)
1740 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1741 #define EPWM_MINDB_LOGICAL_OR (0x1)
1750 #define EPWM_MINDB_PWMB (0x0)
1751 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1753 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1755 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1757 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1759 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1761 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1763 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1765 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1767 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1769 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1771 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1773 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1775 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1777 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1779 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1788 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1789 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1798 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1799 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1801 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1803 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1805 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1807 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1809 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1811 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1813 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1815 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1817 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1819 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1821 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1823 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1825 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1827 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
1966 #define EPWM_XCMP_ACTIVE (0x0)
1967 #define EPWM_XCMP_SHADOW1 (0x1)
1969 #define EPWM_XCMP_SHADOW2 (0x2)
1971 #define EPWM_XCMP_SHADOW3 (0x3)
2340 #define EPWM_DE_CHANNEL_A (0x0)
2341 #define EPWM_DE_CHANNEL_B (0x1)
2351 #define EPWM_DE_COUNT_UP (0x0)
2352 #define EPWM_DE_COUNT_DOWN (0x1)
2362 #define EPWM_DE_TRIPL (0x1)
2363 #define EPWM_DE_TRIPH (0x0)
2373 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
2374 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
2375 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
2376 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
2377 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
2378 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
2379 #define EPWM_LOCK_KEY (0xA5A50000U)
2420 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2447 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2448 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2449 CSL_EPWM_TBCTL_PHSDIR_MASK));
2456 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2457 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2458 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2492 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2493 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2494 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2495 (((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2496 ((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2518 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2519 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2558 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2559 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2560 (~CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2561 ((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2610 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2611 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2655 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2656 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2657 ~((uint16_t)source)));
2684 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2685 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2686 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2687 (uint16_t)trigger));
2714 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2715 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2722 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2723 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2745 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2746 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2766 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2767 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
2793 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2794 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2795 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
2825 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2826 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2827 ~(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
2828 ((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
2847 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2848 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
2849 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2869 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2870 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
2871 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
2891 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
2892 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
2906 static inline uint16_t
2912 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
2933 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
2934 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
2935 CSL_EPWM_TBSTS_CTRMAX_MASK) ?
true :
false);
2956 HW_WR_REG16(base + CSL_EPWM_TBSTS,
2957 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
2978 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
2979 CSL_EPWM_TBSTS_SYNCI_MASK) ?
true :
false);
2999 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3000 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
3016 static inline uint16_t
3022 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
3046 HW_WR_REG32(base + CSL_EPWM_TBPHS,
3047 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
3048 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
3049 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
3075 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
3089 static inline uint16_t
3095 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
3166 uint32_t registerOffset;
3170 registerOffset = base + CSL_EPWM_EPWMXLINK2;
3175 registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
3180 registerOffset = base + CSL_EPWM_EPWMXLINK;
3186 HW_WR_REG32(registerOffset,
3187 ((HW_RD_REG32(registerOffset) &
3188 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComp)) |
3189 ((uint32_t)epwmLink << linkComp)));
3227 uint16_t syncModeOffset;
3228 uint16_t loadModeOffset;
3229 uint16_t shadowModeOffset;
3230 uint32_t registerOffset;
3235 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
3236 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
3237 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3241 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
3242 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
3243 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3253 registerOffset = base + CSL_EPWM_CMPCTL;
3257 registerOffset = base + CSL_EPWM_CMPCTL2;
3264 HW_WR_REG16(registerOffset,
3265 ((HW_RD_REG16(registerOffset) &
3266 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
3267 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
3268 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
3269 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3270 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
3296 uint16_t shadowModeOffset;
3297 uint32_t registerOffset;
3302 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3306 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3316 registerOffset = base + CSL_EPWM_CMPCTL;
3320 registerOffset = base + CSL_EPWM_CMPCTL2;
3326 HW_WR_REG16(registerOffset,
3327 (HW_RD_REG16(registerOffset) |
3328 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
3354 uint32_t registerOffset;
3359 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3370 HW_WR_REG16(registerOffset + 0x2U, compCount);
3377 HW_WR_REG16(registerOffset, compCount);
3398 static inline uint16_t
3401 uint32_t registerOffset;
3407 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3418 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3419 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3420 CSL_EPWM_CMPA_CMPA_SHIFT);
3427 compCount = HW_RD_REG16(registerOffset);
3461 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3462 ((((uint16_t)compModule >> 1U) & 0x2U) +
3463 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3464 0x1U) == 0x1U) ?
true:
false);
3505 uint16_t syncModeOffset;
3506 uint16_t shadowModeOffset;
3508 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3509 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3515 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3516 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3517 (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3518 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3519 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
3520 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3521 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3522 (uint16_t)aqModule))));
3545 uint16_t shadowModeOffset;
3547 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3553 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3554 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3555 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3587 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3588 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3589 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3590 ((uint16_t)trigger)));
3622 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3623 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3624 (~CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3625 ((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3676 uint32_t registerOffset;
3677 uint32_t registerTOffset;
3682 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3683 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3688 if(((uint16_t)
event & 0x1U) == 1U)
3693 HW_WR_REG16(base + registerTOffset,
3694 ((HW_RD_REG16(base + registerTOffset) &
3695 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3696 ((uint16_t)output << ((uint16_t)event - 1U))));
3703 HW_WR_REG16(base + registerOffset,
3704 ((HW_RD_REG16(base + registerOffset) &
3705 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3706 ((uint16_t)output << (uint16_t)event)));
3799 uint32_t registerOffset;
3804 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3809 HW_WR_REG16(base + registerOffset, action);
3878 uint32_t registerTOffset;
3883 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3888 HW_WR_REG16(base + registerTOffset, action);
3921 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
3922 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
3923 ~CSL_EPWM_AQSFRC_RLDCSF_MASK) |
3924 ((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
3959 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
3960 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
3961 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
3962 ((uint16_t)output)));
3966 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
3967 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
3968 ~CSL_EPWM_AQCSFRC_CSFB_MASK) |
3969 ((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
4007 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4008 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4009 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
4010 ((uint16_t)output)));
4014 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4015 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4016 ~CSL_EPWM_AQSFRC_ACTSFB_MASK) |
4017 ((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
4046 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4047 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4048 CSL_EPWM_AQSFRC_OTSFA_MASK));
4052 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4053 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4054 CSL_EPWM_AQSFRC_OTSFB_MASK));
4085 bool enableSwapMode)
4089 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
4096 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4097 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4104 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4105 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4133 bool enableDelayMode)
4137 mask = 1U << ((uint16_t)(delayMode + CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
4144 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4145 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4152 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4153 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4185 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
4190 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4191 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
4192 ((uint16_t)polarity << shift)));
4224 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4225 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4226 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
4227 (input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
4265 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4266 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
4267 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4274 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4275 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4276 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4281 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4282 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4283 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
4284 (input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
4314 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4315 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4316 ~CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
4317 (CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
4338 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4339 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4340 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
4368 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4369 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4370 ~CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
4371 ((uint16_t)CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
4372 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
4393 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4394 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4395 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4423 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4424 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4425 ~CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4426 (CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4427 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4448 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4449 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4450 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4478 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4479 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4480 ~CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4481 ((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4508 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4535 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4558 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4559 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4579 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4580 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4609 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4610 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4611 (dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4640 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4641 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4642 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4643 (freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4667 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
4672 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4673 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4674 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
4675 (firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
4720 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4721 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
4763 HW_WR_REG32(base + CSL_EPWM_TZSEL,
4764 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
4807 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
4808 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
4809 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
4810 ((uint16_t)dcEvent << (uint16_t)dcType)));
4832 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4833 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4853 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4854 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
4896 HW_WR_REG16(base + CSL_EPWM_TZCTL,
4897 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
4898 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
4899 ((uint16_t)tzAction << (uint16_t)tzEvent)));
4947 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4948 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
4949 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
4950 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
4952 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
4953 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
4999 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
5000 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
5001 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5002 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5004 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5005 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5050 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
5051 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
5052 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5053 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5055 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5056 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5087 DebugP_assert((tzInterrupt >= 0U) && (tzInterrupt < 0x80U));
5092 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5093 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
5129 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5130 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
5153 static inline uint16_t
5159 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
5185 static inline uint16_t
5191 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
5215 static inline uint16_t
5221 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
5251 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5252 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
5253 ~CSL_EPWM_TZCLR_CBCPULSE_MASK) |
5254 ((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
5291 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5292 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
5329 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
5330 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
5366 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
5367 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
5400 HW_WR_REG16(base + CSL_EPWM_TZFRC,
5401 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5427 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5428 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5454 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5455 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5478 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5479 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5499 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5500 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5531 uint16_t mixedSource)
5538 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5539 (interruptSource == 10U) || (interruptSource == 12U) ||
5540 (interruptSource == 14U));
5550 intSource = interruptSource >> 1U;
5555 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5556 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5557 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5564 intSource = interruptSource;
5569 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5570 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5571 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5575 intSource = interruptSource;
5580 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5584 intSource = interruptSource;
5590 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5591 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5592 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
5620 HW_WR_REG16(base + CSL_EPWM_ETPS,
5621 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
5623 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
5624 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5625 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
5647 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
5648 0x1U) ?
true :
false);
5668 HW_WR_REG16(base + CSL_EPWM_ETCLR,
5669 (HW_RD_REG16(base + CSL_EPWM_ETCLR) | CSL_EPWM_ETCLR_INT_MASK));
5692 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5693 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5694 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5715 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5716 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
5717 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
5741 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
5742 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
5743 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
5766 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
5771 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
5772 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
5773 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
5774 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
5788 static inline uint16_t
5794 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5795 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
5796 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
5816 HW_WR_REG16(base + CSL_EPWM_ETFRC,
5817 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
5846 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5847 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
5851 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5852 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
5879 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5880 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
5884 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5885 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
5925 uint16_t mixedSource)
5934 source = (uint16_t)socSource >> 1U;
5938 source = (uint16_t)socSource;
5946 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5947 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5948 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
5949 (source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
5962 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5963 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5964 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
5974 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5975 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5976 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
5983 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
5997 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5998 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5999 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
6000 (source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
6013 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6014 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6015 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6025 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6026 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6027 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6034 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
6071 uint16_t preScaleCount)
6076 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
6081 HW_WR_REG16(base + CSL_EPWM_ETPS,
6082 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
6083 CSL_EPWM_ETPS_SOCPSSEL_MASK));
6090 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6091 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6092 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
6100 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6101 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6102 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
6103 (preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
6130 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
6131 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
6132 0x1U) == 0x1U) ?
true :
false);
6157 HW_WR_REG16(base + CSL_EPWM_ETCLR,
6158 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
6159 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT)));
6188 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6189 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | 1U <<
6190 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT)));
6218 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6219 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6220 ~(1U << ((uint16_t)adcSOCType +
6221 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6247 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6248 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6249 1U << ((uint16_t)adcSOCType +
6250 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT)));
6273 uint16_t eventCount)
6278 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
6285 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6286 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6287 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
6288 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
6292 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6293 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6294 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
6295 (eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
6314 static inline uint16_t
6318 uint16_t eventCount;
6325 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6326 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
6327 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
6331 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6332 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
6333 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
6360 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6361 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
6362 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT)));
6401 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6402 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
6403 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
6404 ((uint16_t)dcType << 2U))) |
6405 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6428 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6429 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6449 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6450 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6471 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6472 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6492 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6493 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6494 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6519 uint16_t mixedSource)
6526 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6532 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6533 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6534 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6535 ((uint16_t)((uint32_t)blankingPulse <<
6536 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6564 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6565 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6566 ((uint16_t)filterInput)));
6590 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6591 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6592 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6612 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6613 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6614 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6640 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6641 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6642 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
6643 (edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
6674 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6675 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6676 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
6677 (edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
6692 static inline uint16_t
6698 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6699 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
6700 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
6715 static inline uint16_t
6721 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6722 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
6723 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
6746 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
6768 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
6782 static inline uint16_t
6788 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
6802 static inline uint16_t
6808 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
6846 uint32_t registerOffset;
6855 HW_WR_REG16(base + registerOffset,
6856 ((HW_RD_REG16(base + registerOffset) &
6857 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
6858 (uint16_t)dcEventSource));
6862 HW_WR_REG16(base + registerOffset,
6863 ((HW_RD_REG16(base + registerOffset) &
6864 ~CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
6865 ((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
6901 uint32_t registerOffset;
6910 HW_WR_REG16(base + registerOffset,
6911 ((HW_RD_REG16(base + registerOffset) &
6912 ~CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
6913 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
6917 HW_WR_REG16(base + registerOffset,
6918 ((HW_RD_REG16(base + registerOffset) &
6919 ~CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
6920 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
6944 uint32_t registerOffset;
6951 HW_WR_REG16(base + registerOffset,
6952 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
6975 uint32_t registerOffset;
6982 HW_WR_REG16(base + registerOffset,
6983 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7006 uint32_t registerOffset;
7013 HW_WR_REG16(base + registerOffset,
7014 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7037 uint32_t registerOffset;
7044 HW_WR_REG16(base + registerOffset,
7045 (HW_RD_REG16(base + registerOffset) &
7046 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7079 uint32_t registerOffset;
7088 HW_WR_REG16(base + registerOffset,
7089 ((HW_RD_REG16(base + registerOffset) &
7090 ~CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
7091 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
7095 HW_WR_REG16(base + registerOffset,
7096 ((HW_RD_REG16(base + registerOffset) &
7097 ~CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
7098 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
7137 uint32_t registerOffset;
7146 HW_WR_REG16(base + registerOffset,
7147 ((HW_RD_REG16(base + registerOffset) &
7148 ~CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
7149 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
7153 HW_WR_REG16(base + registerOffset,
7154 ((HW_RD_REG16(base + registerOffset) &
7155 ~CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
7156 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
7188 uint32_t registerOffset;
7198 status = HW_RD_REG16(base + registerOffset) &
7199 CSL_EPWM_DCACTL_EVT1LAT_MASK;
7203 status = HW_RD_REG16(base + registerOffset) &
7204 CSL_EPWM_DCACTL_EVT2LAT_MASK;
7207 return(status != 0U);
7230 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7231 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
7251 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7252 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7253 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
7274 if(enableShadowMode)
7279 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7280 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7281 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7288 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7289 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
7290 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7314 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7315 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
7331 static inline uint16_t
7337 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
7366 uint32_t registerOffset;
7372 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7378 HW_WR_REG16(base + registerOffset,
7379 (HW_RD_REG16(base + registerOffset) | tripInput));
7384 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
7385 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
7386 (CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
7415 uint32_t registerOffset;
7421 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7427 HW_WR_REG16(base + registerOffset,
7428 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7451 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7452 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
7472 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7473 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
7497 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7498 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7499 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
7523 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7524 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7525 ~CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
7526 ((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
7561 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
7562 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7563 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
7564 (startCount | (stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
7584 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7585 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
7586 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7606 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7607 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7608 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
7629 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
7650 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
7651 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
7652 ~CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
7653 ((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
7680 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7681 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ==
7682 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ?
true :
false);
7689 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
7690 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
7691 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ?
true :
false);
7709 static inline uint16_t
7715 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
7729 static inline uint16_t
7735 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
7757 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7758 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
7779 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7780 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
7818 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7819 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7820 ~CSL_EPWM_GLDCTL_GLDMODE_MASK) |
7821 ((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
7851 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7852 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
7853 (prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
7869 static inline uint16_t
7875 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
7876 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
7898 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7899 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
7900 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
7922 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
7923 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
7945 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
7946 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
7967 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
7968 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
8002 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8007 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8008 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
8043 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8049 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8050 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
8072 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
8096 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8097 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8098 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8102 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8103 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8104 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8125 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8126 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8127 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8131 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8132 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8133 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8157 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8158 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8159 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
8160 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
8164 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8165 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8166 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
8167 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
8188 uint32_t referenceSignal)
8192 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8193 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8194 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
8195 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
8199 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8200 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8201 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
8202 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
8222 uint32_t blockingSignal)
8226 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8227 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8228 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
8229 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
8233 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8234 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8235 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
8236 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
8255 uint32_t referenceSignal)
8259 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8260 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8261 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
8262 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
8266 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8267 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8268 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
8269 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
8285 static inline uint32_t
8292 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8293 CSL_EPWM_MINDBDLY_DELAYA_MASK);
8297 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8298 CSL_EPWM_MINDBDLY_DELAYB_MASK);
8323 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8324 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8325 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
8326 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
8330 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8331 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8332 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
8333 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
8357 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8358 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
8359 CSL_EPWM_LUTCTLA_BYPASS_MASK));
8363 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8364 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
8365 CSL_EPWM_LUTCTLB_BYPASS_MASK));
8386 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8387 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8388 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
8392 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8393 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8394 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
8416 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8417 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8418 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
8419 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
8423 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8424 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8425 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
8426 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
8448 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8449 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8450 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
8451 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
8452 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
8486 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount);
8516 HW_WR_REG16(base + CSL_EPWM_TBPHS,
8517 ((HW_RD_REG16(base + CSL_EPWM_TBPHS) &
8518 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
8519 ((uint32_t)hrPhaseCount << CSL_EPWM_TBPHS_TBPHSHR_SHIFT)));
8546 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
8551 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
8565 static inline uint16_t
8571 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR));
8607 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8608 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8609 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
8610 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
8644 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8645 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8646 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
8647 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
8682 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8683 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
8684 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
8685 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
8708 if(enableOutputSwap)
8710 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8711 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
8715 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8716 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
8741 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8742 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
8743 ((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
8764 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8765 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8786 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
8787 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
8807 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8808 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
8828 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8829 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
8850 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8851 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
8871 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8872 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
8911 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8912 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
8913 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
8914 ((uint16_t)syncPulseSource << 1U)));
8918 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
8919 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
8920 ((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
8947 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
8989 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
8996 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
9017 static inline uint32_t
9031 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9038 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9066 uint16_t hrCompCount)
9081 HW_WR_REG32(base + CSL_EPWM_CMPA,
9082 HW_RD_REG32(base + CSL_EPWM_CMPA) | (hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK));
9089 HW_WR_REG32(base + CSL_EPWM_CMPB,
9090 HW_RD_REG32(base + CSL_EPWM_CMPB) | (hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK));
9110 static inline uint16_t
9114 uint16_t hrCompCount;
9124 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
9131 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
9134 return(hrCompCount);
9164 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
9165 HW_RD_REG16(base + CSL_EPWM_DBREDHR) |
9166 (hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
9195 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
9196 HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
9197 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK |
9198 (hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
9226 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
9227 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
9228 mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT));
9259 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9260 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
9261 ((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
9289 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9290 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
9291 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
9318 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9319 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
9320 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
9341 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9343 HW_WR_REG32(registerOffset,
9344 (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
9361 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9363 HW_WR_REG32(registerOffset,
9364 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
9383 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9384 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
9386 HW_WR_REG32(registerOffset,
9387 (HW_RD_REG32(registerOffset) | ( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
9405 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9406 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
9408 HW_WR_REG32(registerOffset,
9409 (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
9438 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9439 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
9441 HW_WR_REG32(registerOffset,
9442 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( alloctype << offset )));
9465 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
9466 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
9468 HW_WR_REG32(registerOffset,
9469 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( alloctype << offset )));
9498 uint32_t registerOffset;
9503 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
9508 HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
9556 uint32_t registerOffset;
9564 registerOffset = CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)(epwmOutput/2);
9566 HW_WR_REG16(base + registerOffset,
9567 ((HW_RD_REG16(base + registerOffset) &
9568 ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
9569 ((uint16_t)output << (uint16_t)event)));
9573 registerOffset = CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)(epwmOutput/2);
9575 HW_WR_REG16(base + registerOffset,
9576 ((HW_RD_REG16(base + registerOffset) &
9577 ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
9578 ((uint16_t)output << (uint16_t)event)));
9582 registerOffset = CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)(epwmOutput/2);
9584 HW_WR_REG16(base + registerOffset,
9585 ((HW_RD_REG16(base + registerOffset) &
9586 ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
9587 ((uint16_t)output << (uint16_t)event)));
9591 registerOffset = CSL_EPWM_XAQCTLA_SHDW3 + (uint16_t)(epwmOutput/2);
9593 HW_WR_REG16(base + registerOffset,
9594 ((HW_RD_REG16(base + registerOffset) &
9595 ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
9596 ((uint16_t)output << (uint16_t)event)));
9616 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
9618 HW_WR_REG32(registerOffset,
9619 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
9636 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
9638 HW_WR_REG32(registerOffset,
9639 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
9660 uint32_t registerOffset;
9665 registerOffset = base + CSL_EPWM_XLOADCTL;
9669 HW_WR_REG32(registerOffset,
9670 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
9674 HW_WR_REG32(registerOffset,
9675 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
9698 uint32_t registerOffset;
9703 registerOffset = base + CSL_EPWM_XLOADCTL;
9705 HW_WR_REG32(registerOffset,
9706 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
9707 ((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
9729 uint32_t registerOffset;
9734 registerOffset = base + CSL_EPWM_XLOADCTL;
9736 HW_WR_REG32(registerOffset,
9737 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
9738 ((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
9762 uint32_t registerOffset;
9766 registerOffset = base + CSL_EPWM_XLOADCTL;
9770 HW_WR_REG32(registerOffset,
9771 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
9772 | (count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
9776 HW_WR_REG32(registerOffset,
9777 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
9778 | (count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
9802 uint32_t registerOffset;
9806 registerOffset = base + CSL_EPWM_DECTL;
9808 HW_WR_REG32(registerOffset,
9809 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
9828 uint32_t registerOffset;
9832 registerOffset = base + CSL_EPWM_DECTL;
9834 HW_WR_REG32(registerOffset,
9835 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
9857 uint32_t registerOffset;
9862 registerOffset = base + CSL_EPWM_DECTL;
9866 HW_WR_REG32(registerOffset,
9867 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
9871 HW_WR_REG32(registerOffset,
9872 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
9893 uint32_t registerOffset;
9897 registerOffset = base + CSL_EPWM_DECTL;
9899 HW_WR_REG32(registerOffset,
9900 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
9901 | (delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
9927 uint32_t registerOffset;
9931 registerOffset = base + CSL_EPWM_DECOMPSEL;
9935 HW_WR_REG32(registerOffset,
9936 ((HW_RD_REG32(registerOffset) &
9937 ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
9938 (source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
9942 HW_WR_REG32(registerOffset,
9943 ((HW_RD_REG32(registerOffset) &
9944 ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
9945 (source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
9974 uint32_t registerOffset;
9978 registerOffset = base + CSL_EPWM_DEACTCTL;
9982 HW_WR_REG32(registerOffset,
9983 ((HW_RD_REG32(registerOffset) &
9984 ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
9985 (signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
9989 HW_WR_REG32(registerOffset,
9990 ((HW_RD_REG32(registerOffset) &
9991 ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
9992 (signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
10018 uint32_t registerOffset;
10022 registerOffset = base + CSL_EPWM_DEACTCTL;
10026 HW_WR_REG32(registerOffset,
10027 ((HW_RD_REG32(registerOffset) &
10028 ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
10029 (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
10033 HW_WR_REG32(registerOffset,
10034 ((HW_RD_REG32(registerOffset) &
10035 ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
10036 (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
10052 uint32_t registerOffset;
10056 registerOffset = base + CSL_EPWM_DEACTCTL;
10058 HW_WR_REG32(registerOffset,
10059 (HW_RD_REG32(registerOffset) &
10060 ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10076 uint32_t registerOffset;
10080 registerOffset = base + CSL_EPWM_DEACTCTL;
10082 HW_WR_REG32(registerOffset,
10083 (HW_RD_REG32(registerOffset) |
10084 (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10100 uint32_t registerOffset;
10104 registerOffset = base + CSL_EPWM_DEFRC;
10106 HW_WR_REG32(registerOffset,
10107 (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
10124 uint32_t registerOffset;
10128 registerOffset = base + CSL_EPWM_DEMONCTL;
10130 HW_WR_REG32(registerOffset,
10131 (HW_RD_REG32(registerOffset) |
10132 (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10147 uint32_t registerOffset;
10151 registerOffset = base + CSL_EPWM_DEMONCTL;
10153 HW_WR_REG32(registerOffset,
10154 (HW_RD_REG32(registerOffset) &
10155 ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10177 uint32_t registerOffset;
10181 registerOffset = base + CSL_EPWM_DEMONSTEP;
10185 HW_WR_REG32(registerOffset,
10186 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
10187 | (stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
10191 HW_WR_REG32(registerOffset,
10192 ((HW_RD_REG32(registerOffset) &
10193 ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
10194 (stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
10211 uint32_t registerOffset;
10215 registerOffset = base + CSL_EPWM_DEMONTHRES;
10217 HW_WR_REG32(registerOffset,
10218 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
10219 | (threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
10274 #endif // EPWM_V1_H_
@ EPWM_TZ_ACTION_HIGH
high voltage state
Definition: etpwm.h:955
@ HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:1889
static void EPWM_disableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5710
static void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, bool enableSwapMode)
Definition: etpwm.h:4084
static void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6182
@ EPWM_AQ_OUTPUT_HIGH_UP_T1
T1 event on count up and set output pins to high.
Definition: etpwm.h:675
static uint16_t EPWM_getValleyHWDelay(uint32_t base)
Definition: etpwm.h:7730
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
Definition: etpwm.h:6716
EPWM_TimeBaseCountMode
Definition: etpwm.h:346
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
Trip source is INPUTXBAR out22 signal.
Definition: etpwm.h:2260
@ EPWM_TZ_ACTION_LOW
low voltage state
Definition: etpwm.h:956
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
Sync-in source is EPWM8 sync-out signal.
Definition: etpwm.h:204
static uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5186
EPWM_ActionQualifierLoadMode
Definition: etpwm.h:508
@ EPWM_LINK_WITH_EPWM_5
link current ePWM with ePWM5
Definition: etpwm.h:393
static void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4417
static void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode)
Definition: etpwm.h:2819
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
Clear CBC pulse when counter equals zero or period.
Definition: etpwm.h:1128
static void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp)
Definition: etpwm.h:3163
EPWM_XCMP_XLOADCTL_SHDWLEVEL
Definition: etpwm.h:2161
static void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode)
Definition: etpwm.h:8601
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
Sync-in source is FSI-RX2 RX Trigger 2 signal.
Definition: etpwm.h:300
@ EPWM_SOC_A
SOC A.
Definition: etpwm.h:1257
@ EPWM_DC_EVENT_1
Digital Compare Event number 1.
Definition: etpwm.h:1464
@ EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:514
@ EPWM_AQ_SW_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:600
@ EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
Time base counter equals zero.
Definition: etpwm.h:1391
@ EPWM_DE_TRIP_SRC_CMPSSB1
Trip source is CMPSSB1 signal.
Definition: etpwm.h:2302
@ EPWM_HSCLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:168
@ EPWM_LINK_WITH_EPWM_9
link current ePWM with ePWM9
Definition: etpwm.h:397
static void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
Definition: etpwm.h:9216
static void EPWM_startValleyCapture(uint32_t base)
Definition: etpwm.h:7492
static void EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
Definition: etpwm.h:9760
static void EPWM_disableOneShotSync(uint32_t base)
Definition: etpwm.h:2864
@ EPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2048
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
load when counter is equal to cmpc and cmpc is incrementing
Definition: etpwm.h:1549
static void EPWM_enableValleyHWDelay(uint32_t base)
Definition: etpwm.h:7579
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
Trip source is INPUTXBAR out18 signal.
Definition: etpwm.h:2252
static void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent)
Definition: etpwm.h:5245
static void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
Definition: etpwm.h:4630
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
Sync-in source is C2K Timesync xbar sync pwm out1 signal.
Definition: etpwm.h:278
static void EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5422
@ EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
shadow to active load occurs when time base counter reaches 0.
Definition: etpwm.h:362
@ EPWM_DE_TRIP_SRC_CMPSSB0
Trip source is CMPSSB0 signal.
Definition: etpwm.h:2300
@ EPWM_REGISTER_GROUP_TRIP_ZONE
Trip zone register group.
Definition: etpwm.h:1706
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
Sync-in source is EPWM24 sync-out signal.
Definition: etpwm.h:236
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
Digital Compare event A/B 1 while counting up.
Definition: etpwm.h:1004
static void EPWM_forceDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10098
@ EPWM_COMP_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:469
EPWM_ActionQualifierContForce
Definition: etpwm.h:726
@ EPWM_DE_SYNC_INV_TRIPHorL
synchronized and inverted version of TRIPH or TRIPL signal
Definition: etpwm.h:2327
static uint16_t EPWM_getTimeBaseCounterValue(uint32_t base)
Definition: etpwm.h:2907
static uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6315
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
Trip source is INPUTXBAR out16 signal.
Definition: etpwm.h:2248
@ EPWM_DE_HIGH
a constant high signal
Definition: etpwm.h:2331
static void EPWM_enableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:4827
@ HRPWM_PWMSYNC_SOURCE_ZERO
Counter equals zero.
Definition: etpwm.h:1919
@ HRPWM_PWMSYNC_SOURCE_COMPD_UP
Counter equals COMPD when counting up.
Definition: etpwm.h:1925
static void HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
Definition: etpwm.h:9185
static void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action)
Definition: etpwm.h:3795
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
Clear CBC latch when counter equals zero or period.
Definition: etpwm.h:1523
@ EPWM_CLOCK_DIVIDER_32
Divide clock by 32.
Definition: etpwm.h:154
static void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
Definition: etpwm.h:4525
@ EPWM_XCMP_4_CMPA
Allocate XCMP1 - XCMP4 registers to CMPA.
Definition: etpwm.h:2110
#define EPWM_XCMP_SHADOW1
XCMP set = Shadow 2.
Definition: etpwm.h:1968
@ EPWM_COMP_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:475
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
Sync-in source is C2K Timesync xbar sync pwm out0 signal.
Definition: etpwm.h:276
@ EPWM_DE_TRIP_SRC_CMPSSB2
Trip source is CMPSSB2 signal.
Definition: etpwm.h:2304
@ EPWM_DC_EDGEFILT_EDGECNT_6
Digital Compare Edge filter edge count = 7.
Definition: etpwm.h:1691
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
Trip source is INPUTXBAR out12 signal.
Definition: etpwm.h:2240
Float32 dutyValA
Desired ePWMxA Signal Duty.
Definition: etpwm.h:2390
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
load on sync or when counter equals zero
Definition: etpwm.h:518
static void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput)
Definition: etpwm.h:4038
@ EPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:1985
@ EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
Clear CBC latch when counter equals zero.
Definition: etpwm.h:1519
@ EPWM_LINK_WITH_EPWM_22
link current ePWM with ePWM22
Definition: etpwm.h:410
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
T1 event on count down and no change in the output pins.
Definition: etpwm.h:679
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
@ EPWM_LINK_WITH_EPWM_16
link current ePWM with ePWM16
Definition: etpwm.h:404
EPWM_DigitalCompareEdgeFilterEdgeCount
Definition: etpwm.h:1677
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
Time base counter down equals COMPA and set output pins to high.
Definition: etpwm.h:640
static void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:6394
EPWM_TripZoneDigitalCompareOutput
Definition: etpwm.h:907
EPWM_TripZoneAdvancedEvent
Definition: etpwm.h:967
@ EPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2054
@ EPWM_FED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:833
static void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6151
@ EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:473
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
Sync-in source is ECAP9 sync-out signal.
Definition: etpwm.h:270
@ EPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2004
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
Sync-in source is ECAP0 sync-out signal.
Definition: etpwm.h:252
@ EPWM_XMINMAX_SHADOW1
XMINMAX_SHADOW1.
Definition: etpwm.h:2022
#define EPWM_XCMP_ACTIVE
< XCMP set = Active
Definition: etpwm.h:1966
static void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode)
Definition: etpwm.h:8638
static void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode)
Definition: etpwm.h:6896
@ EPWM_DB_POLARITY_ACTIVE_HIGH
DB polarity is not inverted.
Definition: etpwm.h:769
static void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode)
Definition: etpwm.h:3914
@ EPWM_DB_RED
DB RED (Rising Edge Delay) mode.
Definition: etpwm.h:757
@ EPWM_LINK_WITH_EPWM_24
link current ePWM with ePWM24
Definition: etpwm.h:412
EPWM_ActionQualifierTriggerSource
Definition: etpwm.h:534
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
Time base counter equals XCMP1.
Definition: etpwm.h:2076
@ HRPWM_MEP_PHASE_CTRL
TBPHSHR controls MEP edge.
Definition: etpwm.h:1872
#define EPWM_SYNC_OUT_SOURCE_M
Definition: etpwm.h:79
@ EPWM_COUNTER_COMPARE_D
counter compare D
Definition: etpwm.h:457
@ EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
Event when DCxL high DCxH low.
Definition: etpwm.h:927
@ EPWM_LINK_TBPRD
link TBPRD:TBPRDHR registers
Definition: etpwm.h:430
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
Trip source is INPUTXBAR out29 signal.
Definition: etpwm.h:2274
#define EPWM_INT_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1212
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_U
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up.
Definition: etpwm.h:975
@ EPWM_SOC_TBCTR_PERIOD
Time-base counter equal to period.
Definition: etpwm.h:1274
static uint16_t EPWM_getGlobalLoadEventCount(uint32_t base)
Definition: etpwm.h:7870
static void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5043
@ EPWM_AQ_OUTPUT_TOGGLE_ZERO
Time base counter equals zero and toggle the output pins.
Definition: etpwm.h:618
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
Sync-in source is EPWM18 sync-out signal.
Definition: etpwm.h:224
static void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge)
Definition: etpwm.h:9253
@ EPWM_DE_TRIP_SRC_CMPSSB4
Trip source is CMPSSB4 signal.
Definition: etpwm.h:2308
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
Digital compare filter event.
Definition: etpwm.h:543
@ HRPWM_DB_MEP_CTRL_RED
MEP controls Rising Edge Delay.
Definition: etpwm.h:1953
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
Sync-in source is EPWM0 sync-out signal.
Definition: etpwm.h:188
@ EPWM_SOC_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1284
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
Trip source is INPUTXBAR out14 signal.
Definition: etpwm.h:2244
static void EPWM_setOneShotSyncOutTrigger(uint32_t base, EPWM_OneShotSyncOutTrigger trigger)
Definition: etpwm.h:2678
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
Time base counter down equals COMPA.
Definition: etpwm.h:561
EPWM_ActionQualifierEventAction
Definition: etpwm.h:610
static void EPWM_disableXCMPMode(uint32_t base)
Definition: etpwm.h:9359
static void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
Definition: etpwm.h:6741
@ EPWM_XCMP_6_CMPA
Allocate XCMP1 - XCMP6 registers to CMPA.
Definition: etpwm.h:2114
EPWM_ClockDivider tbClkDiv
Time Base Counter Clock Divider.
Definition: etpwm.h:2395
@ EPWM_AQ_OUTPUT_NO_CHANGE
No change in the output pins.
Definition: etpwm.h:584
@ EPWM_DE_TRIP_SRC_CMPSSA0
Trip source is CMPSSA0 signal.
Definition: etpwm.h:2280
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
Digital compare event B 1.
Definition: etpwm.h:537
static void HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
Definition: etpwm.h:9154
@ EPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2062
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
Sync-in source is FSI-RX1 RX Trigger 1 signal.
Definition: etpwm.h:290
@ HRPWM_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:1885
static void EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
Definition: etpwm.h:8319
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
Sync-in source is EPWM27 sync-out signal.
Definition: etpwm.h:242
@ EPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2050
@ EPWM_LINK_WITH_EPWM_12
link current ePWM with ePWM12
Definition: etpwm.h:400
static void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
Definition: etpwm.h:8736
static void EPWM_enableInterrupt(uint32_t base)
Definition: etpwm.h:5473
static void EPWM_disableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:4848
#define EPWM_DB_INPUT_EPWMA
Input signal is ePWMA.
Definition: etpwm.h:780
static void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode)
Definition: etpwm.h:4472
@ EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
Trigger is OSHT reload.
Definition: etpwm.h:322
@ EPWM_AQ_OUTPUT_HIGH_ZERO
Time base counter equals zero and set output pins to high.
Definition: etpwm.h:616
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
load on sync event or when counter is equal to period
Definition: etpwm.h:1545
HRPWM_ChannelBOutput
Definition: etpwm.h:1901
@ EPWM_LINK_WITH_EPWM_2
link current ePWM with ePWM2
Definition: etpwm.h:390
static void EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:8353
static void HRPWM_disablePeriodControl(uint32_t base)
Definition: etpwm.h:8823
@ EPWM_DB_OUTPUT_A
DB output is ePWMA.
Definition: etpwm.h:745
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
Clear CBC pulse when counter equals period.
Definition: etpwm.h:1126
EPWM_TripZoneDigitalCompareOutputEvent
Definition: etpwm.h:921
@ EPWM_SHADOW_LOAD_MODE_SYNC
shadow to active load occurs only when a SYNC occurs
Definition: etpwm.h:367
static void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
Definition: etpwm.h:2788
EPWM_PeriodLoadMode
Definition: etpwm.h:332
Float32 sysClkInHz
SYSCLK Frequency(in Hz)
Definition: etpwm.h:2393
EPWM_CurrentLink
Definition: etpwm.h:387
static void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity)
Definition: etpwm.h:4179
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
Sync-in source is EPWM15 sync-out signal.
Definition: etpwm.h:218
@ EPWM_HSCLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:167
static void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
Definition: etpwm.h:4662
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
Sync-in source is EPWM4 sync-out signal.
Definition: etpwm.h:196
@ EPWM_HSCLOCK_DIVIDER_14
Divide clock by 14.
Definition: etpwm.h:174
@ EPWM_AQ_OUTPUT_LOW_DOWN_T2
T2 event on count down and set output pins to low.
Definition: etpwm.h:697
#define EPWM_DCxxTRIPSEL
Definition: etpwm.h:2374
HRPWM_MEPCtrlMode
Definition: etpwm.h:1868
EPWM_DiodeEmulationSignal
Definition: etpwm.h:2322
@ EPWM_REGISTER_GROUP_DIGITAL_COMPARE
Digital compare group.
Definition: etpwm.h:1708
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
Sync-in source is FSI-RX3 RX Trigger 0 signal.
Definition: etpwm.h:304
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
Time base counter equals XCMP8.
Definition: etpwm.h:2090
@ EPWM_XCMP_7_CMPA
Allocate XCMP1 - XCMP7 registers to CMPA.
Definition: etpwm.h:2116
static void EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4443
static void EPWM_clearEventTriggerInterruptFlag(uint32_t base)
Definition: etpwm.h:5663
EPWM_DigitalCompareTripInput
Definition: etpwm.h:1321
@ EPWM_AQ_SW_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:599
static void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7362
EPWM_SyncInPulseSource
Definition: etpwm.h:184
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
T2 event on count down and toggle the output pins.
Definition: etpwm.h:701
static void EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8254
EPWM_DeadBandControlLoadMode
Definition: etpwm.h:793
EPWM_ActionQualifierSWOutput
Definition: etpwm.h:597
static void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
Definition: etpwm.h:7645
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
T1 event on count up.
Definition: etpwm.h:567
static void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
Definition: etpwm.h:5281
static void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9313
EPWM_ADCStartOfConversionType
Definition: etpwm.h:1256
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
Trip source is INPUTXBAR out28 signal.
Definition: etpwm.h:2272
@ EPWM_XCMP_2_CMPA
Allocate XCMP1 - XCMP2 registers to CMPA.
Definition: etpwm.h:2106
static void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
Definition: etpwm.h:7518
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
Definition: etpwm.h:1642
static void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
Definition: etpwm.h:2440
static void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction)
Definition: etpwm.h:4941
@ EPWM_GL_LOAD_PULSE_SYNC
load on sync event
Definition: etpwm.h:1541
static void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6487
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
load on sync event or when counter is equal to zero
Definition: etpwm.h:1543
static void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
Definition: etpwm.h:4599
#define EPWM_INT_TBCTR_ETINTMIX
Time-base counter based on mix events.
Definition: etpwm.h:1196
@ EPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2012
@ EPWM_LINK_WITH_EPWM_18
link current ePWM with ePWM18
Definition: etpwm.h:406
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
Time base counter down equals COMPA and no change in the output pins.
Definition: etpwm.h:636
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
Trip source is INPUTXBAR out25 signal.
Definition: etpwm.h:2266
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
Only Active register is available.
Definition: etpwm.h:2163
static void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:5610
static void EPWM_nobypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10050
@ EPWM_CLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:152
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
Trip source is INPUTXBAR out3 signal.
Definition: etpwm.h:2222
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_D
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down.
Definition: etpwm.h:973
static bool EPWM_getSyncStatus(uint32_t base)
Definition: etpwm.h:2973
@ EPWM_TZ_ADV_ACTION_LOW
low voltage state
Definition: etpwm.h:989
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:479
@ EPWM_COUNTER_MODE_UP
Up - count mode.
Definition: etpwm.h:347
@ EPWM_SOC_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1288
static void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource, uint16_t mixedSource)
Definition: etpwm.h:5922
static void EPWM_disableSplitXCMP(uint32_t base)
Definition: etpwm.h:9403
static void EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8092
@ EPWM_HSCLOCK_DIVIDER_6
Divide clock by 6.
Definition: etpwm.h:170
@ EPWM_XCMP_1_CMPA
Allocate XCMP1 register to CMPA.
Definition: etpwm.h:2104
static uint16_t EPWM_getTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5154
@ EPWM_REGISTER_GROUP_GLOBAL_LOAD
Global load register group.
Definition: etpwm.h:1705
@ EPWM_GL_LOAD_PULSE_CNTR_PERIOD
load when counter is equal to period
Definition: etpwm.h:1537
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
Time base counter equals XCMP2.
Definition: etpwm.h:2078
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
T2 event on count up and no change in the output pins.
Definition: etpwm.h:687
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
Sync-in source is FSI-RX0 RX Trigger 0 signal.
Definition: etpwm.h:280
static uint16_t EPWM_getTimeBasePeriod(uint32_t base)
Definition: etpwm.h:3090
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
Sync-in source is FSI-RX0 RX Trigger 2 signal.
Definition: etpwm.h:284
static void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
Definition: etpwm.h:7624
@ EPWM_DC_MODULE_A
Digital Compare Module A.
Definition: etpwm.h:1449
@ EPWM_AQ_OUTPUT_A
ePWMxA output
Definition: etpwm.h:715
EPWM_GlobalLoadTrigger
Definition: etpwm.h:1533
@ EPWM_HSCLOCK_DIVIDER_10
Divide clock by 10.
Definition: etpwm.h:172
@ EPWM_LINK_WITH_EPWM_0
link current ePWM with ePWM0
Definition: etpwm.h:388
@ EPWM_COUNT_MODE_DOWN_AFTER_SYNC
Count down after sync event.
Definition: etpwm.h:137
@ EPWM_DC_WINDOW_START_TBCTR_ZERO
Time base counter equals zero.
Definition: etpwm.h:1389
@ EPWM_AQ_OUTPUT_TOGGLE
Toggle the output pins.
Definition: etpwm.h:587
EPWM_DigitalCompareCBCLatchClearEvent
Definition: etpwm.h:1517
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
Digital compare event A 1.
Definition: etpwm.h:535
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
Shadow buffer 2 is in use.
Definition: etpwm.h:2186
static void EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10145
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T1
T1 event on count down and set output pins to high.
Definition: etpwm.h:683
@ EPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2008
static bool EPWM_getDigitalCompareCaptureStatus(uint32_t base)
Definition: etpwm.h:7309
@ EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
Valley capture trigged by software.
Definition: etpwm.h:1598
static void EPWM_setGlobalLoadOneShotLatch(uint32_t base)
Definition: etpwm.h:7940
@ EPWM_AQ_SW_DISABLED
Software forcing disabled.
Definition: etpwm.h:598
@ EPWM_XMINMAX_SHADOW2
XMINMAX_SHADOW2.
Definition: etpwm.h:2043
EPWM_ADCStartOfConversionSource
Definition: etpwm.h:1268
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
Trip source is INPUTXBAR out23 signal.
Definition: etpwm.h:2262
static void EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7411
@ HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
Counter equals COMPD when counting down.
Definition: etpwm.h:1927
EPWM_EmulationMode
Definition: etpwm.h:120
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
Trip zone 2.
Definition: etpwm.h:540
@ EPWM_DC_WINDOW_SOURCE_DCBEVT2
DC filter signal source is DCBEVT2.
Definition: etpwm.h:1434
#define EPWM_INT_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1200
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
Sync-in source is EPWM25 sync-out signal.
Definition: etpwm.h:238
@ EPWM_DC_EDGEFILT_EDGECNT_2
Digital Compare Edge filter edge count = 3.
Definition: etpwm.h:1683
#define EPWM_INT_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1210
EPWM_XCMP_ALLOC_CMPA
Values that can be passed to EPWM_allocAXCMP() as the alloctype parameter.
Definition: etpwm.h:2100
@ EPWM_LINK_WITH_EPWM_20
link current ePWM with ePWM20
Definition: etpwm.h:408
@ EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:817
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
Digital compare event A 2.
Definition: etpwm.h:536
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
Time base counter equals XCMP6.
Definition: etpwm.h:2086
static void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
Definition: etpwm.h:8899
static void HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
Definition: etpwm.h:8541
@ EPWM_LINK_WITH_EPWM_30
link current ePWM with ePWM30
Definition: etpwm.h:418
static void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:6941
@ EPWM_DC_TYPE_DCAL
Digital Compare A Low.
Definition: etpwm.h:1309
EPWM_CounterCompareModule
Definition: etpwm.h:453
EPWM_HSClockDivider tbHSClkDiv
Time Base Counter HS Clock Divider.
Definition: etpwm.h:2396
@ EPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2020
@ EPWM_OSHT_SYNC_OUT_TRIG_SYNC
Trigger is OSHT sync.
Definition: etpwm.h:321
HRPWM_CounterCompareModule
Definition: etpwm.h:1937
@ EPWM_TZ_EVENT_DCXL_LOW
Event when DCxL low.
Definition: etpwm.h:925
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
Digital Compare event A/B 1 while counting down.
Definition: etpwm.h:1006
static void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
Definition: etpwm.h:8476
EPWM_DigitalCompareSyncMode
Definition: etpwm.h:1489
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
Trip source is INPUTXBAR out15 signal.
Definition: etpwm.h:2246
static void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
Definition: etpwm.h:2415
@ EPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:454
@ EPWM_DC_EDGEFILT_MODE_BOTH
Definition: etpwm.h:1667
@ EPWM_LINK_WITH_EPWM_13
link current ePWM with ePWM13
Definition: etpwm.h:401
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
Sync-in source is EPWM16 sync-out signal.
Definition: etpwm.h:220
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
Time base counter up equals COMPB.
Definition: etpwm.h:563
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
Sync-in source is ECAP4 sync-out signal.
Definition: etpwm.h:260
@ EPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2025
static void EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:4715
@ EPWM_DC_TRIP_TRIPIN13
Trip 13.
Definition: etpwm.h:1334
@ EPWM_DC_EDGEFILT_EDGECNT_7
Definition: etpwm.h:1693
@ EPWM_AQ_OUTPUT_B
ePWMxB output
Definition: etpwm.h:716
@ EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
Trip zone clear group.
Definition: etpwm.h:1707
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
Time base counter equals period.
Definition: etpwm.h:557
static void EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6444
@ EPWM_SOC_TBCTR_ZERO
Time-base counter equal to zero.
Definition: etpwm.h:1272
@ EPWM_LINK_WITH_EPWM_29
link current ePWM with ePWM29
Definition: etpwm.h:417
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
Definition: etpwm.h:1648
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
Trip source is INPUTXBAR out31 signal.
Definition: etpwm.h:2278
@ EPWM_LINK_WITH_EPWM_14
link current ePWM with ePWM14
Definition: etpwm.h:402
static void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3581
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
Sync-in source is EPWM17 sync-out signal.
Definition: etpwm.h:222
#define EPWM_MINDB_BLOCK_A
Values that can be passed to.
Definition: etpwm.h:1720
EPWM_ActionQualifierOutputEvent
Definition: etpwm.h:553
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
load on sync or when counter equals period
Definition: etpwm.h:520
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
Load mode is LOADMULTIPLE.
Definition: etpwm.h:2150
@ EPWM_DC_EDGEFILT_EDGECNT_0
Digital Compare Edge filter edge count = 0.
Definition: etpwm.h:1679
@ EPWM_AQ_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:510
@ EPWM_DC_TYPE_DCAH
Digital Compare A High.
Definition: etpwm.h:1308
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
Sync-in source is EPWM1 sync-out signal.
Definition: etpwm.h:190
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
Sync-in source is EPWM31 sync-out signal.
Definition: etpwm.h:250
@ EPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2060
@ HRPWM_OUTPUT_ON_B_INV_A
Definition: etpwm.h:1905
static void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
Definition: etpwm.h:7813
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
Sync-in source is EPWM3 sync-out signal.
Definition: etpwm.h:194
@ EPWM_TZ_ACTION_EVENT_TZB
TZ1 - TZ6, DCBEVT2, DCBEVT1.
Definition: etpwm.h:939
static bool EPWM_getEventTriggerInterruptStatus(uint32_t base)
Definition: etpwm.h:5642
static void EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_XCMPActionQualifierOutputEvent event)
Definition: etpwm.h:9551
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:481
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
Time base counter equals XCMP4.
Definition: etpwm.h:2082
@ EPWM_CLOCK_DIVIDER_64
Divide clock by 64.
Definition: etpwm.h:155
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T1
T1 event on count up and toggle the output pins.
Definition: etpwm.h:677
static void EPWM_selectDiodeEmulationTripSignal(uint32_t base, uint32_t channel, uint32_t signal)
Definition: etpwm.h:10015
static void EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
Definition: etpwm.h:9436
@ EPWM_LINK_WITH_EPWM_3
link current ePWM with ePWM3
Definition: etpwm.h:391
EPWM_TimeBaseCountMode tbCtrMode
Time Base Counter Mode.
Definition: etpwm.h:2394
static void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
Definition: etpwm.h:3041
static void EPWM_enableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:9800
EPWM_DigitalCompareType
Definition: etpwm.h:1307
@ EPWM_COMP_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:483
@ EPWM_REGISTER_GROUP_HR
HRPWM register group.
Definition: etpwm.h:1704
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
Time base counter down equals COMPA and toggle the output pins.
Definition: etpwm.h:642
@ EPWM_LINK_WITH_EPWM_21
link current ePWM with ePWM21
Definition: etpwm.h:409
static void EPWM_forceEventTriggerInterrupt(uint32_t base)
Definition: etpwm.h:5811
static void EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
Definition: etpwm.h:8412
static void EPWM_setDiodeEmulationMode(uint32_t base, EPWM_DiodeEmulationMode mode)
Definition: etpwm.h:9855
EPWM_DeadBandOutput
Definition: etpwm.h:744
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
Digital Compare event A/B 2 while counting up.
Definition: etpwm.h:1008
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
Sync-in source is FSI-RX0 RX Trigger 1 signal.
Definition: etpwm.h:282
@ EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
Stop when counter completes whole cycle.
Definition: etpwm.h:124
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_D
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down.
Definition: etpwm.h:969
static void EPWM_disableValleyHWDelay(uint32_t base)
Definition: etpwm.h:7601
@ EPWM_SOC_TBCTR_MIXED_EVENT
Time-base counter equal to zero or period.
Definition: etpwm.h:1276
static void EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
Definition: etpwm.h:9727
static void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler)
Definition: etpwm.h:2486
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
Time base counter up equals COMPB and toggle the output pins.
Definition: etpwm.h:650
static uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
Definition: etpwm.h:6803
@ EPWM_AQ_OUTPUT_LOW_UP_CMPB
Time base counter up equals COMPB and set output pins to low.
Definition: etpwm.h:646
@ EPWM_RED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:813
@ EPWM_HSCLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:171
@ EPWM_TZ_DC_OUTPUT_A2
Digital Compare output 2 A.
Definition: etpwm.h:909
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
Trip source is INPUTXBAR out13 signal.
Definition: etpwm.h:2242
Float32 dutyValB
Desired ePWMxB Signal Duty.
Definition: etpwm.h:2391
static void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
Definition: etpwm.h:8067
static void HRPWM_disableAutoConversion(uint32_t base)
Definition: etpwm.h:8781
@ EPWM_DE_TRIP_SRC_CMPSSA2
Trip source is CMPSSA2 signal.
Definition: etpwm.h:2284
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
Sync-in source is EPWM12 sync-out signal.
Definition: etpwm.h:212
#define EPWM_INT_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1204
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
T2 event on count down and no change in the output pins.
Definition: etpwm.h:695
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T2
T2 event on count up and toggle the output pins.
Definition: etpwm.h:693
@ EPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:1997
static void EPWM_enableXLoad(uint32_t base)
Definition: etpwm.h:9614
@ EPWM_TZ_ACTION_DISABLE
disable action
Definition: etpwm.h:957
@ EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
ePWM sync
Definition: etpwm.h:542
static void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6241
static uint32_t EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
Definition: etpwm.h:8286
@ EPWM_XCMP_NONE_CMPA
Allocate 0 XCMP registers to CMPA.
Definition: etpwm.h:2102
static void EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:8382
@ EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
load on sync event or when counter is equal to period or zero
Definition: etpwm.h:1547
static void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule)
Definition: etpwm.h:3542
static void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount)
Definition: etpwm.h:6069
static void EPWM_enableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5687
EPWM_DiodeEmulationTripSource
Definition: etpwm.h:2214
static void EPWM_enableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7225
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
Shadow buffer 1 is in use.
Definition: etpwm.h:2184
@ EPWM_DC_WINDOW_SOURCE_DCAEVT1
DC filter signal source is DCAEVT1.
Definition: etpwm.h:1431
EPWM_DigitalCompareEvent
Definition: etpwm.h:1463
static void HRPWM_enableAutoConversion(uint32_t base)
Definition: etpwm.h:8759
@ EPWM_LINK_COMP_B
link COMPB registers
Definition: etpwm.h:432
@ EPWM_LINK_WITH_EPWM_6
link current ePWM with ePWM6
Definition: etpwm.h:394
static void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6466
@ EPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2052
@ EPWM_LINK_WITH_EPWM_15
link current ePWM with ePWM15
Definition: etpwm.h:403
@ HRPWM_MEP_DUTY_PERIOD_CTRL
CMPAHR/CMPBHR or TBPRDHR controls MEP edge.
Definition: etpwm.h:1870
static void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
Definition: etpwm.h:4333
@ EPWM_DE_TRIP_SRC_CMPSSA5
Trip source is CMPSSA5 signal.
Definition: etpwm.h:2290
@ EPWM_DB_POLARITY_ACTIVE_LOW
DB polarity is inverted.
Definition: etpwm.h:770
static void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4362
@ EPWM_TZ_ADV_ACTION_DISABLE
disable action
Definition: etpwm.h:991
@ EPWM_CLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:151
@ EPWM_DC_EVENT_INPUT_SYNCED
DC input signal is synced with TBCLK.
Definition: etpwm.h:1491
@ EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
Time base counter equals period and no change in the output pins.
Definition: etpwm.h:620
@ EPWM_LINK_DBRED
link DBRED registers
Definition: etpwm.h:436
EPWM_ValleyCounterEdge
Definition: etpwm.h:1622
EPWM_LockRegisterGroup
Definition: etpwm.h:1703
@ EPWM_SYNC_IN_PULSE_SRC_DISABLE
Disable Sync-in.
Definition: etpwm.h:186
static void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4251
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
Shadow buffer 3 is in use.
Definition: etpwm.h:2188
EPWM_SyncCountMode
Definition: etpwm.h:136
@ EPWM_RED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:819
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
Sync-in source is FSI-RX1 RX Trigger 0 signal.
Definition: etpwm.h:288
@ EPWM_HSCLOCK_DIVIDER_12
Divide clock by 12.
Definition: etpwm.h:173
HRPWM_Channel
Definition: etpwm.h:1838
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
Sync-in source is EPWM21 sync-out signal.
Definition: etpwm.h:230
static void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode)
Definition: etpwm.h:4308
@ EPWM_DC_TRIP_TRIPIN4
Trip 4.
Definition: etpwm.h:1325
EPWM_HSClockDivider
Definition: etpwm.h:166
@ EPWM_RED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:815
static void HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
Definition: etpwm.h:8703
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
Time base counter down equals COMPA and set output pins to low.
Definition: etpwm.h:638
@ HRPWM_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1852
@ EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
Time base counter equals zero and no change in the output pins.
Definition: etpwm.h:612
@ EPWM_DE_TRIP_SRC_CMPSSA1
Trip source is CMPSSA1 signal.
Definition: etpwm.h:2282
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
Trip source is INPUTXBAR out19 signal.
Definition: etpwm.h:2254
@ EPWM_AQ_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:585
@ EPWM_XCMP_1_CMPB
Allocate XCMP5 register to CMPB.
Definition: etpwm.h:2130
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
Trip source is INPUTXBAR out8 signal.
Definition: etpwm.h:2232
static uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base)
Definition: etpwm.h:3017
HRPWM_LoadMode
Definition: etpwm.h:1883
@ EPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:1983
static void EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8187
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
Sync-in source is EPWM19 sync-out signal.
Definition: etpwm.h:226
static uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base)
Definition: etpwm.h:7332
static void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse, uint16_t mixedSource)
Definition: etpwm.h:6517
#define EPWM_INT_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1208
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
Load mode is LOADONCE.
Definition: etpwm.h:2148
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
Sync-in source is FSI-RX3 RX Trigger 1 signal.
Definition: etpwm.h:306
@ EPWM_LINK_XLOAD
link XLOAD registers
Definition: etpwm.h:438
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_U
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up.
Definition: etpwm.h:971
@ EPWM_TZ_EVENT_DC_DISABLED
Event is disabled.
Definition: etpwm.h:922
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
SHDW3, SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2169
static uint16_t EPWM_getInterruptEventCount(uint32_t base)
Definition: etpwm.h:5789
static void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
Definition: etpwm.h:7272
Float32 freqInHz
Desired Signal Frequency(in Hz)
Definition: etpwm.h:2389
@ EPWM_ACTION_QUALIFIER_A
Action Qualifier A.
Definition: etpwm.h:497
#define EPWM_DE_TRIPH
Definition: etpwm.h:2364
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
Sync-in source is EPWM11 sync-out signal.
Definition: etpwm.h:210
@ EPWM_DE_TRIP_SRC_CMPSSB5
Trip source is CMPSSB5 signal.
Definition: etpwm.h:2310
@ EPWM_DE_TRIP_SRC_CMPSSA4
Trip source is CMPSSA4 signal.
Definition: etpwm.h:2288
#define EPWM_XCMP_SHADOW3
Definition: etpwm.h:1972
EPWM_TripZoneEvent
Definition: etpwm.h:937
@ EPWM_DC_TRIP_COMBINATION
All Trips (Trip1 - Trip 15) are selected.
Definition: etpwm.h:1337
@ EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
load on global force
Definition: etpwm.h:1557
@ EPWM_DC_TRIP_TRIPIN15
Trip 15.
Definition: etpwm.h:1336
static void EPWM_disableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:7893
#define EPWM_INT_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1202
EPWM_DigitalCompareBlankingPulse
Definition: etpwm.h:1385
static uint16_t HRPWM_getHiResCounterCompareValueOnly(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9111
static void EPWM_forceSyncPulse(uint32_t base)
Definition: etpwm.h:2513
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
Definition: etpwm.h:1645
EPWM_ValleyDelayMode
Definition: etpwm.h:1634
@ EPWM_LINK_WITH_EPWM_11
link current ePWM with ePWM11
Definition: etpwm.h:399
@ EPWM_CLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:149
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
Time base counter up equals COMPA and no change in the output pins.
Definition: etpwm.h:628
@ EPWM_XCMP_3_CMPA
Allocate XCMP1 - XCMP3 registers to CMPA.
Definition: etpwm.h:2108
static void EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
Definition: etpwm.h:2553
@ EPWM_DE_TRIP_SRC_CMPSSB8
Trip source is CMPSSB8 signal.
Definition: etpwm.h:2316
@ EPWM_TZ_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:954
static void EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
Definition: etpwm.h:9463
@ HRPWM_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:1887
static void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:4992
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
Trip source is INPUTXBAR out6 signal.
Definition: etpwm.h:2228
static void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode)
Definition: etpwm.h:6634
@ EPWM_LINK_WITH_EPWM_23
link current ePWM with ePWM23
Definition: etpwm.h:411
@ EPWM_EMULATION_STOP_AFTER_NEXT_TB
Stop after next Time Base counter increment or decrement.
Definition: etpwm.h:122
@ EPWM_XMINMAX_SHADOW3
XMINMAX_SHADOW3.
Definition: etpwm.h:2064
static void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
Definition: etpwm.h:7840
@ EPWM_SOC_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1282
@ EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
signal source is unfiltered (DCAEVT1/2)
Definition: etpwm.h:1477
bool invertSignalB
Invert ePWMxB Signal if true.
Definition: etpwm.h:2392
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
Sync-in source is FSI-RX1 RX Trigger 2 signal.
Definition: etpwm.h:292
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
T2 event on count down.
Definition: etpwm.h:573
static void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event)
Definition: etpwm.h:3671
@ EPWM_DB_FED
DB FED (Falling Edge Delay) mode.
Definition: etpwm.h:758
static void EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8121
@ EPWM_TZ_DC_OUTPUT_B2
Digital Compare output 2 B.
Definition: etpwm.h:911
static void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount)
Definition: etpwm.h:3351
@ EPWM_TZ_ADV_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:987
static uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
Definition: etpwm.h:6783
static void EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block, uint32_t invert)
Definition: etpwm.h:8152
@ EPWM_DE_TRIP_SRC_CMPSSA8
Trip source is CMPSSA8 signal.
Definition: etpwm.h:2296
@ EPWM_DC_TYPE_DCBL
Digital Compare B Low.
Definition: etpwm.h:1311
@ EPWM_CLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:150
EPWM_DeadBandDelayMode
Definition: etpwm.h:756
static void EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6585
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
Sync-in source is EPWM26 sync-out signal.
Definition: etpwm.h:240
@ EPWM_DC_EDGEFILT_EDGECNT_3
Digital Compare Edge filter edge count = 4.
Definition: etpwm.h:1685
@ HRPWM_LOAD_ON_CMPB_EQ
load on translater event CMPB-3
Definition: etpwm.h:1891
#define EPWM_INT_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1198
static void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode)
Definition: etpwm.h:3223
EPWM_OneShotSyncOutTrigger
Definition: etpwm.h:320
static void EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:9495
static void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
Definition: etpwm.h:4498
static void EPWM_enableSplitXCMP(uint32_t base)
Definition: etpwm.h:9381
@ EPWM_TZ_EVENT_DCXH_HIGH
Event when DCxH high.
Definition: etpwm.h:924
@ EPWM_CLOCK_DIVIDER_16
Divide clock by 16.
Definition: etpwm.h:153
@ EPWM_DC_TRIP_TRIPIN12
Trip 12.
Definition: etpwm.h:1333
@ EPWM_XCMP_2_CMPB
Allocate XCMP5 - XCMP6 registers to CMPB.
Definition: etpwm.h:2132
static void EPWM_disableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:9826
@ EPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2033
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
Trip source is INPUTXBAR out5 signal.
Definition: etpwm.h:2226
@ EPWM_LINK_WITH_EPWM_10
link current ePWM with ePWM10
Definition: etpwm.h:398
static void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:5839
@ EPWM_DC_TRIP_TRIPIN10
Trip 10.
Definition: etpwm.h:1331
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
Sync-in source is ECAP2 sync-out signal.
Definition: etpwm.h:256
static void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount)
Definition: etpwm.h:6271
HRPWM_MEPDeadBandEdgeMode
Definition: etpwm.h:1949
@ EPWM_SOC_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1280
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
Trip source is INPUTXBAR out4 signal.
Definition: etpwm.h:2224
@ EPWM_VALLEY_COUNT_STOP_EDGE
Valley count stop edge.
Definition: etpwm.h:1624
@ EPWM_COUNTER_MODE_STOP_FREEZE
Stop - Freeze counter.
Definition: etpwm.h:350
@ EPWM_LINK_WITH_EPWM_17
link current ePWM with ePWM17
Definition: etpwm.h:405
static void EPWM_setDigitalCompareCBCLatchMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchMode latchMode)
Definition: etpwm.h:7074
static void EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
Definition: etpwm.h:7962
static bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
Definition: etpwm.h:7673
EPWM_ActionQualifierOutput
Definition: etpwm.h:583
@ EPWM_DC_EDGEFILT_MODE_RISING
Digital Compare Edge filter low to high edge mode.
Definition: etpwm.h:1663
@ EPWM_TZ_ACTION_EVENT_DCBEVT2
DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:943
@ EPWM_AQ_OUTPUT_LOW_UP_T1
T1 event on count up and set output pins to low.
Definition: etpwm.h:673
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
Sync-in source is EPWM14 sync-out signal.
Definition: etpwm.h:216
@ EPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2006
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
Trip source is INPUTXBAR out7 signal.
Definition: etpwm.h:2230
@ HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
Counter equals COMPC when counting down.
Definition: etpwm.h:1923
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
Sync-in source is EPWM10 sync-out signal.
Definition: etpwm.h:208
EPWM_ClockDivider
Definition: etpwm.h:148
#define EPWM_DB_INPUT_DB_RED
Input signal is the output of Rising Edge delay.
Definition: etpwm.h:784
EPWM_LinkComponent
Definition: etpwm.h:429
static void EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2645
static void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6212
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
load when counter is equal to cmpd and cmpd is decrementing
Definition: etpwm.h:1555
HRPWM_SyncPulseSource
Definition: etpwm.h:1915
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
Trip source is INPUTXBAR out17 signal.
Definition: etpwm.h:2250
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
Valley capture trigged by when counter is equal to zero.
Definition: etpwm.h:1600
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
Time base counter down equals COMPB and set output pins to low.
Definition: etpwm.h:654
EPWM_DigitalCompareModule
Definition: etpwm.h:1448
static bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6124
@ EPWM_FED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:837
EPWM_DigitalCompareCBCLatchMode
Definition: etpwm.h:1503
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
Sync-in source is FSI-RX1 RX Trigger 3 signal.
Definition: etpwm.h:294
@ EPWM_SOC_B
SOC B.
Definition: etpwm.h:1258
@ EPWM_PERIOD_SHADOW_LOAD
PWM Period register access is through shadow register.
Definition: etpwm.h:334
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
Digital Compare event A/B 2 while counting down.
Definition: etpwm.h:1010
@ EPWM_DC_EDGEFILT_EDGECNT_1
Digital Compare Edge filter edge count = 2.
Definition: etpwm.h:1681
static void HRPWM_setHiResCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint16_t hrCompCount)
Definition: etpwm.h:9064
@ EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
signal source is filtered (DCEVTFILT)
Definition: etpwm.h:1479
@ EPWM_DE_TRIP_SRC_CMPSSA3
Trip source is CMPSSA3 signal.
Definition: etpwm.h:2286
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
Sync-in source is EPWM23 sync-out signal.
Definition: etpwm.h:234
@ EPWM_LINK_WITH_EPWM_8
link current ePWM with ePWM8
Definition: etpwm.h:396
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPB
Time base counter up equals COMPB and set output pins to high.
Definition: etpwm.h:648
static bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
Definition: etpwm.h:2928
@ EPWM_DE_TRIP_SRC_CMPSSA9
Trip source is CMPSSA9 signal.
Definition: etpwm.h:2298
@ EPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:455
@ EPWM_SOC_DCxEVT1
Event is based on DCxEVT1.
Definition: etpwm.h:1270
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
T1 event on count up and no change in the output pins.
Definition: etpwm.h:671
@ EPWM_DC_CBC_LATCH_ENABLED
DC cycle-by-cycle(CBC) latch is enabled.
Definition: etpwm.h:1507
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
Trip zone 1.
Definition: etpwm.h:539
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
Sync-in source is EPWM28 sync-out signal.
Definition: etpwm.h:244
EPWM_ValleyTriggerSource
Definition: etpwm.h:1596
@ EPWM_DC_TRIP_TRIPIN6
Trip 6.
Definition: etpwm.h:1327
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
Sync-in source is ECAP5 sync-out signal.
Definition: etpwm.h:262
@ EPWM_TZ_ADV_ACTION_TOGGLE
toggle the output
Definition: etpwm.h:990
@ EPWM_LINK_COMP_A
link COMPA registers
Definition: etpwm.h:431
static void EPWM_enableGlobalLoad(uint32_t base)
Definition: etpwm.h:7752
static void EPWM_disableValleyCapture(uint32_t base)
Definition: etpwm.h:7467
@ EPWM_TZ_ADV_ACTION_HIGH
high voltage state
Definition: etpwm.h:988
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:1610
EPWM_AdditionalActionQualifierEventAction
Definition: etpwm.h:669
static void EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source, uint32_t tripLorH)
Definition: etpwm.h:9924
@ EPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2037
static void EPWM_enableChopper(uint32_t base)
Definition: etpwm.h:4553
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
Time base counter equals zero.
Definition: etpwm.h:555
@ EPWM_DC_TRIP_TRIPIN3
Trip 3.
Definition: etpwm.h:1324
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
Sync-in source is FSI-RX2 RX Trigger 1 signal.
Definition: etpwm.h:298
static void EPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2740
static void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
Definition: etpwm.h:4800
@ EPWM_AQ_SW_IMMEDIATE_LOAD
No shadow load mode. Immediate mode only.
Definition: etpwm.h:734
@ EPWM_DC_WINDOW_SOURCE_DCBEVT1
DC filter signal source is DCBEVT1.
Definition: etpwm.h:1433
static void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
Definition: etpwm.h:2951
EPWM_DeadBandPolarity
Definition: etpwm.h:768
@ EPWM_DC_TRIP_TRIPIN7
Trip 7.
Definition: etpwm.h:1328
@ EPWM_LINK_WITH_EPWM_28
link current ePWM with ePWM28
Definition: etpwm.h:416
HRPWM_MEPEdgeMode
Definition: etpwm.h:1850
static void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:5872
@ EPWM_DB_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:801
static void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:8676
@ EPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2058
static void EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10122
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
No Shadow buffer is in use.
Definition: etpwm.h:2182
static void EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6423
@ EPWM_DC_WINDOW_START_TBCTR_PERIOD
Time base counter equals period.
Definition: etpwm.h:1387
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
Trip source is INPUTXBAR out11 signal.
Definition: etpwm.h:2238
EPWM_TripZoneAdvancedAction
Definition: etpwm.h:986
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
Definition: etpwm.h:1639
@ HRPWM_MEP_CTRL_RISING_EDGE
MEP controls rising edge.
Definition: etpwm.h:1854
@ EPWM_DC_TRIP_TRIPIN14
Trip 14.
Definition: etpwm.h:1335
#define EPWM_DE_CHANNEL_A
< Diode emulation channel A
Definition: etpwm.h:2340
static void HRPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:8866
static void EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5449
@ EPWM_XCMP_8_CMPA
Allocate XCMP1 - XCMP8 registers to CMPA.
Definition: etpwm.h:2118
@ EPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2056
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
Trip source is INPUTXBAR out26 signal.
Definition: etpwm.h:2268
@ EPWM_AQ_OUTPUT_TOGGLE_PERIOD
Time base counter equals period and toggle the output pins.
Definition: etpwm.h:626
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
Valley capture trigged when counter is equal to zero or period.
Definition: etpwm.h:1604
static void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output)
Definition: etpwm.h:3998
static void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8038
@ EPWM_COUNTER_MODE_UP_DOWN
Up - down - count mode.
Definition: etpwm.h:349
@ EPWM_DC_TRIP_TRIPIN11
Trip 11.
Definition: etpwm.h:1332
static void EPWM_enableOneShotSync(uint32_t base)
Definition: etpwm.h:2842
static void EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2600
static void EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action)
Definition: etpwm.h:3874
EPWM_TripZoneAction
Definition: etpwm.h:953
@ HRPWM_DB_MEP_CTRL_RED_FED
MEP controls both Falling and Rising edge delay.
Definition: etpwm.h:1957
@ EPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:1993
#define EPWM_LOCK_KEY
Definition: etpwm.h:2379
@ HRPWM_MEP_CTRL_FALLING_EDGE
MEP controls falling edge.
Definition: etpwm.h:1856
@ EPWM_DE_TRIP_SRC_CMPSSB3
Trip source is CMPSSB3 signal.
Definition: etpwm.h:2306
@ EPWM_DE_TRIP_SRC_CMPSSB6
Trip source is CMPSSB6 signal.
Definition: etpwm.h:2312
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
Sync-in source is ECAP8 sync-out signal.
Definition: etpwm.h:268
@ EPWM_DC_CBC_LATCH_DISABLED
DC cycle-by-cycle(CBC) latch is disabled.
Definition: etpwm.h:1505
@ EPWM_LINK_GLDCTL2
link GLDCTL2 registers
Definition: etpwm.h:435
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
Valley capture trigged by when counter is equal period.
Definition: etpwm.h:1602
EPWM_TripZoneAdvDigitalCompareEvent
Definition: etpwm.h:1002
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
Trip source is INPUTXBAR out9 signal.
Definition: etpwm.h:2234
static void EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block, uint32_t blockingSignal)
Definition: etpwm.h:8221
EPWM_DigitalCompareEventSource
Definition: etpwm.h:1475
@ EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
Definition: etpwm.h:365
static void EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base, uint16_t threshold)
Definition: etpwm.h:10209
EPWM_XCMP_ALLOC_CMPB
Values that can be passed to EPWM_allocBXCMP() as the alloctype parameter.
Definition: etpwm.h:2128
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
T2 event on count up.
Definition: etpwm.h:571
static uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5216
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
Time base counter down equals COMPB and toggle the output pins.
Definition: etpwm.h:658
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
Time base counter equals XCMP7.
Definition: etpwm.h:2088
@ HRPWM_OUTPUT_ON_B_NORMAL
ePWMxB output is normal.
Definition: etpwm.h:1903
static void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction)
Definition: etpwm.h:4890
@ EPWM_FED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:831
EPWM_DigitalCompareEdgeFilterMode
Definition: etpwm.h:1661
@ EPWM_LINK_WITH_EPWM_7
link current ePWM with ePWM7
Definition: etpwm.h:395
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
Time base counter up equals COMPB and no change in the output pins.
Definition: etpwm.h:644
static void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput)
Definition: etpwm.h:6558
@ EPWM_AQ_OUTPUT_LOW_DOWN_T1
T1 event on count down and set output pins to low.
Definition: etpwm.h:681
#define EPWM_INT_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1206
@ EPWM_DC_EDGEFILT_EDGECNT_5
Digital Compare Edge filter edge count = 6.
Definition: etpwm.h:1689
@ EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:835
@ EPWM_TZ_EVENT_DCXL_HIGH
Event when DCxL high.
Definition: etpwm.h:926
@ EPWM_TZ_ACTION_EVENT_DCAEVT1
DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:940
@ EPWM_TZ_EVENT_DCXH_LOW
Event when DCxH low.
Definition: etpwm.h:923
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPA
Time base counter up equals COMPA and set output pins to high.
Definition: etpwm.h:632
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
Sync-in source is FSI-RX0 RX Trigger 3 signal.
Definition: etpwm.h:286
static void EPWM_forceInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5736
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
Definition: etpwm.h:6693
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:477
@ EPWM_AQ_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:586
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
load when counter is equal to zero or period
Definition: etpwm.h:1539
@ HRPWM_DB_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1951
@ EPWM_DC_TRIP_TRIPIN9
Trip 9.
Definition: etpwm.h:1330
@ EPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:1987
static void EPWM_enableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:7917
EPWM_RisingEdgeDelayLoadMode
Definition: etpwm.h:811
@ EPWM_SOC_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1290
EPWM_CycleByCycleTripZoneClearMode
Definition: etpwm.h:1122
#define EPWM_DE_COUNT_UP
Values that can be passed to EPWM_setDiodeEmulationMonitorModeStep()
Definition: etpwm.h:2351
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
shadow mode load when counter equals period
Definition: etpwm.h:730
@ EPWM_VALLEY_COUNT_START_EDGE
Valley count start edge.
Definition: etpwm.h:1623
EPWM_XCMPActionQualifierOutputEvent
Values that can be passed to EPWM_setXCMPActionQualifierAction() as the event parameter.
Definition: etpwm.h:2074
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
Trip source is INPUTXBAR out2 signal.
Definition: etpwm.h:2220
@ EPWM_DE_TRIP_SRC_CMPSSA7
Trip source is CMPSSA7 signal.
Definition: etpwm.h:2294
@ EPWM_LINK_WITH_EPWM_27
link current ePWM with ePWM27
Definition: etpwm.h:415
@ EPWM_DC_EDGEFILT_MODE_FALLING
Digital Compare Edge filter both edges mode.
Definition: etpwm.h:1665
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
shadow mode load when counter equals zero or period
Definition: etpwm.h:732
@ EPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2039
static void HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
Definition: etpwm.h:8506
@ EPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2029
@ EPWM_DC_EVENT_2
Digital Compare Event number 2.
Definition: etpwm.h:1465
@ EPWM_COUNTER_COMPARE_C
counter compare C
Definition: etpwm.h:456
static void EPWM_disableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7246
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
Sync-in source is ECAP6 sync-out signal.
Definition: etpwm.h:264
static void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5082
static void EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
Definition: etpwm.h:8446
@ EPWM_LINK_WITH_EPWM_19
link current ePWM with ePWM19
Definition: etpwm.h:407
@ EPWM_AQ_OUTPUT_LOW_PERIOD
Time base counter equals period and set output pins to low.
Definition: etpwm.h:622
EPWM_DiodeEmulationMode
Definition: etpwm.h:2200
@ EPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2046
@ EPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2010
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
Sync-in source is ECAP7 sync-out signal.
Definition: etpwm.h:266
static void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
Definition: etpwm.h:6763
static void EPWM_setDiodeEmulationReentryDelay(uint32_t base, uint8_t delay)
Definition: etpwm.h:9891
static void EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4388
@ EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
Dead band counter runs at 2*TBCLK rate.
Definition: etpwm.h:851
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
Sync-in source is EPWM5 sync-out signal.
Definition: etpwm.h:198
@ EPWM_DC_TRIP_TRIPIN2
Trip 2.
Definition: etpwm.h:1323
@ EPWM_XCMP_4_CMPB
Allocate XCMP5 - XCMP8 registers to CMPB.
Definition: etpwm.h:2136
static bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3449
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
Time base counter equals XCMP3.
Definition: etpwm.h:2080
static void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
Definition: etpwm.h:2707
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T2
T2 event on count down and set output pins to high.
Definition: etpwm.h:699
static void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode)
Definition: etpwm.h:3501
static void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output)
Definition: etpwm.h:3950
@ EPWM_SOC_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1286
static void EPWM_selectDiodeEmulationPWMsignal(uint32_t base, uint32_t channel, EPWM_DiodeEmulationSignal signal)
Definition: etpwm.h:9971
EPWM_FallingEdgeDelayLoadMode
Definition: etpwm.h:829
static void EPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2761
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
Time base counter down equals COMPB.
Definition: etpwm.h:565
@ EPWM_DE_LOW
a constant low signal
Definition: etpwm.h:2329
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
Trip source is INPUTXBAR out0 signal.
Definition: etpwm.h:2216
static void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
Definition: etpwm.h:5356
@ EPWM_DB_OUTPUT_B
DB output is ePWMB.
Definition: etpwm.h:746
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
Trip source is INPUTXBAR out20 signal.
Definition: etpwm.h:2256
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
Clear CBC pulse when counter equals zero.
Definition: etpwm.h:1124
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
load when counter is equal to cmpd and cmpd is incrementing
Definition: etpwm.h:1553
static void EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
Definition: etpwm.h:9696
@ HRPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:1938
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
shadow mode load when counter equals zero
Definition: etpwm.h:728
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
T1 event on count down and toggle the output pins.
Definition: etpwm.h:685
@ EPWM_AQ_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:524
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
Sync-in source is EPWM13 sync-out signal.
Definition: etpwm.h:214
@ EPWM_LINK_COMP_D
link COMPD registers
Definition: etpwm.h:434
@ EPWM_COUNT_MODE_UP_AFTER_SYNC
Count up after sync event.
Definition: etpwm.h:138
@ EPWM_DC_EDGEFILT_EDGECNT_4
Digital Compare Edge filter edge count = 5.
Definition: etpwm.h:1687
static void EPWM_enableValleyCapture(uint32_t base)
Definition: etpwm.h:7446
static void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, bool enableDelayMode)
Definition: etpwm.h:4132
@ EPWM_DE_TRIP_SRC_CMPSSB7
Trip source is CMPSSB7 signal.
Definition: etpwm.h:2314
@ EPWM_AQ_OUTPUT_HIGH_UP_T2
T2 event on count up and set output pins to high.
Definition: etpwm.h:691
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
Time base counter down equals COMPB and no change in the output pins.
Definition: etpwm.h:652
static void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3616
static void EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:4758
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
Time base counter up equals COMPA and toggle the output pins.
Definition: etpwm.h:634
@ EPWM_DC_TRIP_TRIPIN8
Trip 8.
Definition: etpwm.h:1329
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
Sync-in source is EPWM30 sync-out signal.
Definition: etpwm.h:248
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
Sync-in source is FSI-RX3 RX Trigger 2 signal.
Definition: etpwm.h:308
@ EPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2018
#define EPWM_DB_INPUT_EPWMB
Input signal is ePWMB.
Definition: etpwm.h:782
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
Time base counter equals XCMP5.
Definition: etpwm.h:2084
@ EPWM_SOC_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1278
@ EPWM_LINK_WITH_EPWM_26
link current ePWM with ePWM26
Definition: etpwm.h:414
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
Trip source is INPUTXBAR out1 signal.
Definition: etpwm.h:2218
@ EPWM_DE_TRIP_SRC_CMPSSA6
Trip source is CMPSSA6 signal.
Definition: etpwm.h:2292
@ EPWM_XCMP_5_CMPA
Allocate XCMP1 - XCMP5 registers to CMPA.
Definition: etpwm.h:2112
static void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
Definition: etpwm.h:5319
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
Trip source is INPUTXBAR out24 signal.
Definition: etpwm.h:2264
@ EPWM_ACTION_QUALIFIER_B
Action Qualifier B.
Definition: etpwm.h:498
@ EPWM_DC_MODULE_B
Digital Compare Module B.
Definition: etpwm.h:1450
@ EPWM_DB_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:797
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:1606
@ EPWM_PERIOD_DIRECT_LOAD
PWM Period register access is directly.
Definition: etpwm.h:336
#define EPWM_DCxCTL_STEP
Defines to be used by the driver.
Definition: etpwm.h:2373
EPWM_XCMPReg
Definition: etpwm.h:1981
@ EPWM_LINK_DBFED
link DBFED registers
Definition: etpwm.h:437
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
T1 event on count down.
Definition: etpwm.h:569
@ HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
MEP controls both rising and falling edge.
Definition: etpwm.h:1858
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
Sync-in source is ECAP1 sync-out signal.
Definition: etpwm.h:254
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:159
EPWM_ActionQualifierModule
Definition: etpwm.h:496
EPWM_ActionQualifierOutputModule
Definition: etpwm.h:714
@ EPWM_LINK_WITH_EPWM_25
link current ePWM with ePWM25
Definition: etpwm.h:413
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
Trip source is INPUTXBAR out30 signal.
Definition: etpwm.h:2276
static void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6355
@ EPWM_DC_EVENT_INPUT_NOT_SYNCED
DC input signal is not synced with TBCLK.
Definition: etpwm.h:1493
static void EPWM_setDiodeEmulationMonitorModeStep(uint32_t base, uint32_t direction, uint8_t stepsize)
Definition: etpwm.h:10174
@ EPWM_XMINMAX_ACTIVE
XMINMAX_ACTIVE.
Definition: etpwm.h:2001
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
Digital compare event B 2.
Definition: etpwm.h:538
EPWM_DigitalCompareFilterInput
Definition: etpwm.h:1430
static void EPWM_setXCMPLoadMode(uint32_t base, EPWM_XCMPXloadCtlLoadMode mode)
Definition: etpwm.h:9658
@ EPWM_TZ_DC_OUTPUT_B1
Digital Compare output 1 B.
Definition: etpwm.h:910
@ EPWM_AQ_OUTPUT_LOW_UP_CMPA
Time base counter up equals COMPA and set output pins to low.
Definition: etpwm.h:630
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load on sync or when counter equals zero or period
Definition: etpwm.h:522
@ EPWM_LINK_WITH_EPWM_1
link current ePWM with ePWM1
Definition: etpwm.h:389
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:1612
@ EPWM_LINK_WITH_EPWM_4
link current ePWM with ePWM4
Definition: etpwm.h:392
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
Sync-in source is FSI-RX2 RX Trigger 0 signal.
Definition: etpwm.h:296
@ EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:799
static void EPWM_disableXLoad(uint32_t base)
Definition: etpwm.h:9634
@ EPWM_AQ_OUTPUT_LOW_UP_T2
T2 event on count up and set output pins to low.
Definition: etpwm.h:689
static uint16_t EPWM_getValleyCount(uint32_t base)
Definition: etpwm.h:7710
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
Trip zone 3.
Definition: etpwm.h:541
static void EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6607
@ EPWM_COUNTER_MODE_DOWN
Down - count mode.
Definition: etpwm.h:348
static void HRPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:8845
@ EPWM_DE_TRIP_SRC_CMPSSB9
Trip source is CMPSSB9 signal.
Definition: etpwm.h:2318
@ EPWM_SOC_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1292
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
Sync-in source is EPWM20 sync-out signal.
Definition: etpwm.h:228
static void EPWM_enableXCMPMode(uint32_t base)
Definition: etpwm.h:9339
@ EPWM_DIODE_EMULATION_OST
Diode Emulation mode is One Shot.
Definition: etpwm.h:2204
@ HRPWM_CHANNEL_B
HRPWM B.
Definition: etpwm.h:1840
static void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3293
static void HRPWM_enablePeriodControl(uint32_t base)
Definition: etpwm.h:8802
@ EPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2031
@ EPWM_DE_SYNC_TRIPHorL
synchronized version of TRIPH or TRIPL signal
Definition: etpwm.h:2325
@ EPWM_TZ_ACTION_EVENT_DCBEVT1
DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:942
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
Clear CBC latch when counter equals period.
Definition: etpwm.h:1521
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO
load when counter is equal to zero
Definition: etpwm.h:1535
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
Sync-in source is EPWM9 sync-out signal.
Definition: etpwm.h:206
@ EPWM_DIODE_EMULATION_CBC
Diode Emulation mode is Cycle by Cycle.
Definition: etpwm.h:2202
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
Trip source is INPUTXBAR out21 signal.
Definition: etpwm.h:2258
static void EPWM_disableInterrupt(uint32_t base)
Definition: etpwm.h:5494
static void EPWM_disableGlobalLoad(uint32_t base)
Definition: etpwm.h:7774
static void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4213
#define EPWM_XCMP_SHADOW2
XCMP set = Shadow 3.
Definition: etpwm.h:1970
static void EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
Definition: etpwm.h:7132
@ HRPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:1939
static void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount)
Definition: etpwm.h:8972
static void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount)
Definition: etpwm.h:7550
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
Sync-in source is Input XBAR out4 signal.
Definition: etpwm.h:272
@ EPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2035
static void EPWM_disableChopper(uint32_t base)
Definition: etpwm.h:4574
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
Sync-in source is FSI-RX2 RX Trigger 3 signal.
Definition: etpwm.h:302
static void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7034
@ EPWM_LINK_COMP_C
link COMPC registers
Definition: etpwm.h:433
static void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:6972
@ EPWM_COMP_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:471
@ EPWM_HSCLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:169
@ EPWM_XCMP_3_CMPB
Allocate XCMP5 - XCMP7 registers to CMPB.
Definition: etpwm.h:2134
@ HRPWM_DB_MEP_CTRL_FED
MEP controls Falling Edge Delay.
Definition: etpwm.h:1955
static uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3399
static void EPWM_bypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10074
static void EPWM_startOneShotSync(uint32_t base)
Definition: etpwm.h:2886
@ EPWM_AQ_OUTPUT_LOW_ZERO
Time base counter equals zero and set output pins to low.
Definition: etpwm.h:614
static void HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
Definition: etpwm.h:8937
@ EPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:1999
EPWM_PeriodShadowLoadMode
Definition: etpwm.h:360
#define EPWM_DE_TRIPL
Values that can be passed to EPWM_configureDiodeEmulationTripSources()
Definition: etpwm.h:2362
static void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:7997
@ EPWM_AQ_OUTPUT_HIGH_PERIOD
Time base counter equals period and set output pins to high.
Definition: etpwm.h:624
@ EPWM_CLOCK_DIVIDER_128
Divide clock by 128.
Definition: etpwm.h:156
EPWM_CounterCompareLoadMode
Definition: etpwm.h:467
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
Sync-in source is EPWM6 sync-out signal.
Definition: etpwm.h:200
@ EPWM_TZ_ACTION_EVENT_TZA
TZ1 - TZ6, DCAEVT2, DCAEVT1.
Definition: etpwm.h:938
static void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9283
static void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource)
Definition: etpwm.h:6841
@ EPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2014
@ EPWM_AQ_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:512
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
Sync-in source is EPWM7 sync-out signal.
Definition: etpwm.h:202
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
Sync-in source is ECAP3 sync-out signal.
Definition: etpwm.h:258
static void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5119
@ EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
Time base counter blank pulse mix.
Definition: etpwm.h:1393
EPWM_DeadBandClockMode
Definition: etpwm.h:847
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:1608
EPWM_XCMPXloadCtlLoadMode
Definition: etpwm.h:2146
@ EPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:1989
static void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
Definition: etpwm.h:5390
static void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:5761
@ HRPWM_PWMSYNC_SOURCE_PERIOD
Counter equals Period.
Definition: etpwm.h:1917
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
Sync-in source is FSI-RX3 RX Trigger 3 signal.
Definition: etpwm.h:310
static uint16_t HRPWM_getHiResTimeBasePeriod(uint32_t base)
Definition: etpwm.h:8566
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
load when counter is equal to cmpc and cmpc is decrementing
Definition: etpwm.h:1551
#define EPWM_DE_COUNT_DOWN
Definition: etpwm.h:2353
@ EPWM_TZ_ACTION_EVENT_DCAEVT2
DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:941
static void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource, uint16_t mixedSource)
Definition: etpwm.h:5530
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
Sync-in source is EPWM2 sync-out signal.
Definition: etpwm.h:192
@ EPWM_DC_TYPE_DCBH
Digital Compare B High.
Definition: etpwm.h:1310
static void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7003
static void EPWM_clearSyncEvent(uint32_t base)
Definition: etpwm.h:2994
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2167
@ EPWM_EMULATION_FREE_RUN
Free run.
Definition: etpwm.h:126
static bool EPWM_getDigitalCompareCBCLatchStatus(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent)
Definition: etpwm.h:7184
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
Sync-in source is EPWM22 sync-out signal.
Definition: etpwm.h:232
static void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
Definition: etpwm.h:6668
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
SHDW1 and Active registers are available.
Definition: etpwm.h:2165
@ EPWM_AQ_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:516
@ EPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:1995
@ EPWM_DC_TRIP_TRIPIN5
Trip 5.
Definition: etpwm.h:1326
@ HRPWM_PWMSYNC_SOURCE_COMPC_UP
Counter equals COMPC when counting up.
Definition: etpwm.h:1921
@ EPWM_VALLEY_DELAY_MODE_SW_DELAY
Delay value equals the offset value defines by software.
Definition: etpwm.h:1636
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
Trip source is INPUTXBAR out10 signal.
Definition: etpwm.h:2236
@ EPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2041
@ EPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2027
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
Trip source is INPUTXBAR out27 signal.
Definition: etpwm.h:2270
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
Time base counter up equals COMPA.
Definition: etpwm.h:559
@ EPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2016
@ EPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:1991
static void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
Definition: etpwm.h:3070
@ HRPWM_CHANNEL_A
HRPWM A.
Definition: etpwm.h:1839
@ EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
Dead band counter runs at TBCLK rate.
Definition: etpwm.h:849
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
Sync-in source is Input XBAR out20 signal.
Definition: etpwm.h:274
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
Sync-in source is EPWM29 sync-out signal.
Definition: etpwm.h:246
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
Definition: etpwm.h:2180
@ EPWM_DC_WINDOW_SOURCE_DCAEVT2
DC filter signal source is DCAEVT2.
Definition: etpwm.h:1432
@ EPWM_LINK_WITH_EPWM_31
link current ePWM with ePWM31
Definition: etpwm.h:419
static uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9018
@ EPWM_DC_TRIP_TRIPIN1
Trip 1.
Definition: etpwm.h:1322
@ EPWM_DB_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:795
@ EPWM_TZ_DC_OUTPUT_A1
Digital Compare output 1 A.
Definition: etpwm.h:908
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
Time base counter down equals COMPB and set output pins to high.
Definition: etpwm.h:656