AM263x MCU+ SDK  08.02.00
uart/v2/uart.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define UART_FIFO_SIZE (64U)
73 
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
80 
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
83 
85 typedef void *UART_Handle;
86 
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
97 
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
99 
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
101 
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
103 
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
105 
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
107 
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
109 
110 #define UART_TRANSFER_STATUS_STARTED (7U)
111 
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
113 
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
115 
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
117 
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
139 
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
144 
166 #define UART_READ_RETURN_MODE_FULL (0U)
167 
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
171 
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
185 
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
197 
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
212 
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
224 
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
239 
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
254 
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
269 
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
284 
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
302 
313 #define UART_TX_FIFO_NOT_FULL ( \
314  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
317 
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
328  << \
329  UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
331  << \
332  UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
334  << \
335  UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
337  << \
338  UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
340  << \
341  UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
343  << \
344  UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
346  << \
347  UART_IIR_IT_TYPE_SHIFT)
348 
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
352 
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
369 
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
372 
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
386 
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
398 
409 #define UART_CONFIG_MODE_POLLED (0x00U)
410 #define UART_CONFIG_MODE_INTERRUPT (0x01U)
411 #define UART_CONFIG_MODE_USER_INTR (0x02U)
412 #define UART_CONFIG_MODE_DMA (0x03U)
413 
414 /* ========================================================================== */
415 /* Structures and Enums */
416 /* ========================================================================== */
417 
422 typedef struct
423 {
424  void *buf;
427  uint32_t count;
431  uint32_t timeout;
433  uint32_t status;
435  void *args;
437 } UART_Transaction;
438 
446 typedef void (*UART_CallbackFxn) (UART_Handle handle,
447  UART_Transaction *transaction);
448 
459 typedef struct
460 {
461  uint32_t baudRate;
463  uint32_t dataLength;
465  uint32_t stopBits;
467  uint32_t parityType;
469  uint32_t readMode;
471  uint32_t readReturnMode;
473  uint32_t writeMode;
475  UART_CallbackFxn readCallbackFxn;
477  UART_CallbackFxn writeCallbackFxn;
479  uint32_t hwFlowControl;
481  uint32_t hwFlowControlThr;
484  /*
485  * Driver configuration
486  */
487  uint32_t transferMode;
489  uint32_t intrNum;
491  uint8_t intrPriority;
493  uint32_t skipIntrReg;
495  int32_t uartDmaIndex;
501  /*
502  * UART configuration
503  */
504  uint32_t operMode;
506  uint32_t rxTrigLvl;
508  uint32_t txTrigLvl;
510  uint32_t rxEvtNum;
512  uint32_t txEvtNum;
514 } UART_Params;
515 
517 typedef struct
518 {
519  /*
520  * SOC configuration
521  */
522  uint32_t baseAddr;
524  uint32_t inputClkFreq;
526 } UART_Attrs;
527 
528 /* ========================================================================== */
529 /* Internal/Private Structure Declarations */
530 /* ========================================================================== */
531 
535 typedef struct
536 {
537  /*
538  * User parameters
539  */
540  UART_Handle handle;
542  UART_Params prms;
544  /*
545  * UART write variables
546  */
547  const void *writeBuf;
549  uint32_t writeCount;
551  uint32_t writeSizeRemaining;
553  /*
554  * UART receive variables
555  */
556  void *readBuf;
558  uint32_t readCount;
560  uint32_t readSizeRemaining;
562  uint32_t rxTimeoutCnt;
564  uint32_t readErrorCnt;
566  /*
567  * UART ransaction status variables
568  */
569  UART_Transaction *readTrans;
571  UART_Transaction *writeTrans;
573  /*
574  * State variables
575  */
576  uint32_t isOpen;
578  void *lock;
580  SemaphoreP_Object lockObj;
582  void *readTransferSem;
585  SemaphoreP_Object readTransferSemObj;
587  void *writeTransferSem;
590  SemaphoreP_Object writeTransferSemObj;
592  void *hwiHandle;
594  HwiP_Object hwiObj;
596  void* uartDmaHandle;
598 } UART_Object;
599 
606 typedef struct
607 {
608  UART_Attrs *attrs;
610  UART_Object *object;
612 } UART_Config;
613 
615 extern UART_Config gUartConfig[];
617 extern uint32_t gUartConfigNum;
618 
619 /* ========================================================================== */
620 /* Global Variables Declarations */
621 /* ========================================================================== */
622 
623 /* None */
624 
625 /* ========================================================================== */
626 /* Function Declarations */
627 /* ========================================================================== */
628 
632 void UART_init(void);
633 
637 void UART_deinit(void);
638 
655 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
656 
666 void UART_close(UART_Handle handle);
667 
706 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
707 
742 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
743 
775 int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans);
776 
808 int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans);
809 
818 UART_Handle UART_getHandle(uint32_t index);
819 
829 void UART_flushTxFifo(UART_Handle handle);
830 
836 static inline void UART_Params_init(UART_Params *prms);
837 
844 static inline void UART_Transaction_init(UART_Transaction *trans);
845 
846 /* ========================================================================== */
847 /* Static Function Definitions */
848 /* ========================================================================== */
849 
850 static inline void UART_Params_init(UART_Params *prms)
851 {
852  if(prms != NULL)
853  {
854  prms->baudRate = 115200U;
855  prms->dataLength = UART_LEN_8;
856  prms->stopBits = UART_STOPBITS_1;
857  prms->parityType = UART_PARITY_NONE;
858  prms->readMode = UART_TRANSFER_MODE_BLOCKING;
859  prms->readReturnMode = UART_READ_RETURN_MODE_FULL;
860  prms->writeMode = UART_TRANSFER_MODE_BLOCKING;
861  prms->readCallbackFxn = NULL;
862  prms->writeCallbackFxn = NULL;
863  prms->hwFlowControl = FALSE;
864  prms->hwFlowControlThr = UART_RXTRIGLVL_16;
865  prms->intrNum = 0xFFFF;
866  prms->transferMode = UART_CONFIG_MODE_INTERRUPT;
867  prms->intrPriority = 4U;
868  prms->skipIntrReg = FALSE;
869  prms->uartDmaIndex = -1;
870  prms->operMode = UART_OPER_MODE_16X;
871  prms->rxTrigLvl = UART_RXTRIGLVL_8;
872  prms->txTrigLvl = UART_TXTRIGLVL_32;
873  }
874 }
875 
876 static inline void UART_Transaction_init(UART_Transaction *trans)
877 {
878  if(trans != NULL)
879  {
880  trans->buf = NULL;
881  trans->count = 0U;
882  trans->timeout = SystemP_WAIT_FOREVER;
883  trans->status = UART_TRANSFER_STATUS_SUCCESS;
884  trans->args = NULL;
885  }
886 }
887 
888 /* ========================================================================== */
889 /* Advanced Function Declarations */
890 /* ========================================================================== */
899 uint32_t UART_getBaseAddr(UART_Handle handle);
900 
909 void UART_enableLoopbackMode(uint32_t baseAddr);
910 
919 void UART_disableLoopbackMode(uint32_t baseAddr);
920 
938 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
939 
954 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
955 
984 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
985 
1010 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
1011 
1030 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
1031 
1049 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
1050 
1076 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
1077 
1090 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1091 
1106 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr);
1107 
1118 static inline uint32_t UART_readLineStatus(uint32_t baseAddr);
1119 
1133 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1134 /* ========================================================================== */
1135 /* Advanced Function Definitions */
1136 /* ========================================================================== */
1137 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1138 {
1139  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1140  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1141 }
1142 
1143 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1144 {
1145  uint32_t lcrRegValue = 0U;
1146  uint32_t retVal = FALSE;
1147 
1148  /* Preserving the current value of LCR. */
1149  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1150 
1151  /* Switching to Register Operational Mode of operation. */
1152  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1153  & 0x7FU);
1154 
1155  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1156  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1157  (HW_RD_REG32(baseAddr + UART_LSR) &
1158  UART_LSR_RX_FIFO_E_MASK))
1159  {
1160  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1161  *pChar = (uint8_t)tempRetVal;
1162  retVal = TRUE;
1163  }
1164 
1165  /* Restoring the value of LCR. */
1166  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1167 
1168  return retVal;
1169 }
1170 
1171 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1172 {
1173  uint32_t enhanFnBitVal = 0U;
1174  uint32_t lcrRegValue = 0U;
1175 
1176  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1177  if ((intrFlag & 0xF0U) > 0U)
1178  {
1179  /* Preserving the current value of LCR. */
1180  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1181  /* Switching to Register Configuration Mode B. */
1182  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1183 
1184  /* Collecting the current value of EFR[4] and later setting it. */
1185  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1186 
1187  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1188  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1189 
1190  /* Restoring the value of LCR. */
1191  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1192 
1193  /* Preserving the current value of LCR. */
1194  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1195 
1196  /* Switching to Register Operational Mode of operation. */
1197  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1198  & 0x7FU);
1199 
1200  /*
1201  ** It is suggested that the System Interrupts for UART in the
1202  ** Interrupt Controller are enabled after enabling the peripheral
1203  ** interrupts of the UART using this API. If done otherwise, there
1204  ** is a risk of LCR value not getting restored and illicit characters
1205  ** transmitted or received from/to the UART. The situation is explained
1206  ** below.
1207  ** The scene is that the system interrupt for UART is already enabled
1208  ** and the current API is invoked. On enabling the interrupts
1209  ** corresponding to IER[7:4] bits below, if any of those interrupt
1210  ** conditions already existed, there is a possibility that the control
1211  ** goes to Interrupt Service Routine (ISR) without executing the
1212  ** remaining statements in this API. Executing the remaining statements
1213  ** is critical in that the LCR value is restored in them.
1214  ** However, there seems to be no risk in this API for enabling
1215  ** interrupts corresponding to IER[3:0] because it is done at the end
1216  ** and no statements follow that.
1217  */
1218 
1219  /************* ATOMIC STATEMENTS START *************************/
1220 
1221  /* Programming the bits IER[7:4]. */
1222  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1223 
1224  /* Restoring the value of LCR. */
1225  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1226 
1227  /* Preserving the current value of LCR. */
1228  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1229  /* Switching to Register Configuration Mode B. */
1230  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1231 
1232  /* Restoring the value of EFR[4] to its original value. */
1233  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1234 
1235  /* Restoring the value of LCR. */
1236  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1237 
1238  /************** ATOMIC STATEMENTS END *************************/
1239  }
1240 
1241  /* Programming the bits IER[3:0]. */
1242  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1243  (intrFlag & 0x0FU));
1244 }
1245 
1246 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1247 {
1248  uint32_t enhanFnBitVal;
1249  uint32_t lcrRegValue;
1250 
1251  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1252  if((intrFlag & 0xF0U) > 0U)
1253  {
1254  /* Preserving the current value of LCR. */
1255  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1256  /* Switching to Register Configuration Mode B. */
1257  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1258 
1259  /* Collecting the current value of EFR[4] and later setting it. */
1260  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1261 
1262  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1263  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1264 
1265  /* Restoring the value of LCR. */
1266  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1267  }
1268 
1269  /* Preserving the current value of LCR. */
1270  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1271 
1272  /* Switching to Register Operational Mode of operation. */
1273  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1274  & 0x7FU);
1275 
1276  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1277  ~(intrFlag & 0xFFU));
1278 
1279  /* Restoring the value of LCR. */
1280  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1281 
1282  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1283  if((intrFlag & 0xF0U) > 0U)
1284  {
1285  /* Preserving the current value of LCR. */
1286  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1287  /* Switching to Register Configuration Mode B. */
1288  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1289 
1290  /* Restoring the value of EFR[4] to its original value. */
1291  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1292 
1293  /* Restoring the value of LCR. */
1294  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1295  }
1296 }
1297 
1298 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1299 {
1300  /* Programming the bits IER2[1:0]. */
1301  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1302  (intrFlag & 0x03U));
1303 }
1304 
1305 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1306 {
1307  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1308  ~(intrFlag & 0x3U));
1309 }
1310 
1311 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1312 {
1313  uint32_t lcrRegValue = 0U;
1314  uint32_t retVal = 0U;
1315 
1316  /* Preserving the current value of LCR. */
1317  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1318 
1319  /* Switching to Register Operational Mode of operation. */
1320  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1321  & 0x7FU);
1322 
1323  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1324 
1325  /* Restoring the value of LCR. */
1326  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1327 
1328  return retVal;
1329 }
1330 
1331 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1332 {
1333  uint32_t retVal = 0U;
1334 
1335  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1336  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1337 
1338  return retVal;
1339 }
1340 
1341 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
1342 {
1343  uint32_t lcrRegValue = 0;
1344  uint32_t retVal = FALSE;
1345 
1346  /* Preserving the current value of LCR. */
1347  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1348 
1349  /* Switching to Register Operational Mode of operation. */
1350  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1351  & 0x7FU);
1352 
1353  /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */
1354  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1355  (HW_RD_REG32(baseAddr + UART_LSR) &
1356  UART_LSR_RX_FIFO_E_MASK))
1357  {
1358  retVal = (uint32_t) TRUE;
1359  }
1360 
1361  /* Restoring the value of LCR. */
1362  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1363 
1364  return retVal;
1365 }
1366 
1367 static inline uint32_t UART_readLineStatus(uint32_t baseAddr)
1368 {
1369  uint32_t lcrRegValue = 0U;
1370  uint32_t retVal = 0U;
1371 
1372  /* Preserving the current value of LCR. */
1373  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1374 
1375  /* Switching to Register Operational Mode of operation. */
1376  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1377  & 0x7FU);
1378 
1379  retVal = HW_RD_REG32(baseAddr + UART_LSR);
1380 
1381  /* Restoring the value of LCR. */
1382  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1383 
1384  return retVal;
1385 }
1386 
1387 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
1388 {
1389  uint8_t readByte = 0;
1390  uint32_t waitCount = UART_ERROR_COUNT;
1391  uint32_t errorVal;
1392  uint32_t lcrRegValue = 0;
1393 
1394  /* Preserving the current value of LCR. */
1395  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1396 
1397  /* Switching to Register Operational Mode of operation. */
1398  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1399  & 0x7FU);
1400 
1401  /* Read Rx Error Status */
1402  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1403  (UART_LSR_RX_FIFO_STS_MASK |
1404  UART_LSR_RX_BI_MASK |
1405  UART_LSR_RX_FE_MASK |
1406  UART_LSR_RX_PE_MASK |
1407  UART_LSR_RX_OE_MASK);
1408 
1409  /* Restoring the value of LCR. */
1410  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1411 
1412  /* Read and throw Erroneous bytes from RxFIFO */
1413  while ((UART_LSR_RX_FIFO_STS_MASK |
1414  UART_LSR_RX_BI_MASK |
1415  UART_LSR_RX_FE_MASK |
1416  UART_LSR_RX_PE_MASK |
1417  UART_LSR_RX_OE_MASK) == errorVal)
1418  {
1419  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1420  waitCount--;
1421  if (0U == waitCount)
1422  {
1423  break;
1424  }
1425 
1426  /* Preserving the current value of LCR. */
1427  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1428 
1429  /* Switching to Register Operational Mode of operation. */
1430  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1431  & 0x7FU);
1432 
1433  /* Read Rx Error Status */
1434  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1435  (UART_LSR_RX_FIFO_STS_MASK |
1436  UART_LSR_RX_BI_MASK |
1437  UART_LSR_RX_FE_MASK |
1438  UART_LSR_RX_PE_MASK |
1439  UART_LSR_RX_OE_MASK);
1440 
1441  /* Restoring the value of LCR. */
1442  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1443  }
1444 
1445  /* Read non-erroneous byte from RxFIFO */
1446  readByte = HW_RD_REG32(baseAddr + UART_RHR);
1447 
1448  return readByte;
1449 }
1450 
1451 #ifdef __cplusplus
1452 }
1453 #endif
1454 
1455 #endif /* #ifndef UART_V0_H_ */
1456 
UART_enableLoopbackMode
void UART_enableLoopbackMode(uint32_t baseAddr)
Function to enable loopback mode. This function is for internal use. Not recommended for customers to...
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v2/uart.h:582
UART_ERROR_COUNT
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v2/uart.h:82
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v2/uart.h:138
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v2/uart.h:580
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v2/uart.h:876
UART_Object::readTransferSemObj
SemaphoreP_Object readTransferSemObj
Definition: uart/v2/uart.h:585
UART_REG_CONFIG_MODE_B
#define UART_REG_CONFIG_MODE_B
Definition: uart/v2/uart.h:396
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v2/uart.h:195
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v2/uart.h:96
UART_Object::handle
UART_Handle handle
Definition: uart/v2/uart.h:540
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v2/uart.h:1298
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v2/uart.h:592
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v2/uart.h:547
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v2/uart.h:431
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v2/uart.h:85
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v2/uart.h:571
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v2/uart.h:607
UART_Params::writeMode
uint32_t writeMode
Definition: uart/v2/uart.h:473
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v2/uart.h:1331
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v2/uart.h:551
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v2/uart.h:446
UART_Params::dataLength
uint32_t dataLength
Definition: uart/v2/uart.h:463
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v2/uart.h:491
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v2/uart.h:469
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v2/uart.h:265
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v2/uart.h:1246
UART_disableLoopbackMode
void UART_disableLoopbackMode(uint32_t baseAddr)
Function to disable loopback mode. This function is for internal use. Not recommended for customers t...
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v2/uart.h:207
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v2/uart.h:506
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v2/uart.h:1143
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v2/uart.h:1311
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void * args
Definition: uart/v2/uart.h:435
UART_Params::uartDmaIndex
int32_t uartDmaIndex
Definition: uart/v2/uart.h:495
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void * uartDmaHandle
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UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v2/uart.h:166
UART_Object::isOpen
uint32_t isOpen
Definition: uart/v2/uart.h:576
UART_flushTxFifo
void UART_flushTxFifo(UART_Handle handle)
Function to flush a TX FIFO of peripheral specified by the UART handle.
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uint32_t transferMode
Definition: uart/v2/uart.h:487
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Definition: uart/v2/uart.h:493
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UART_Attrs * attrs
Definition: uart/v2/uart.h:608
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SemaphoreP_Object writeTransferSemObj
Definition: uart/v2/uart.h:590
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uint32_t readCount
Definition: uart/v2/uart.h:558
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uint32_t rxTimeoutCnt
Definition: uart/v2/uart.h:562
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static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v2/uart.h:1137
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uint32_t writeCount
Definition: uart/v2/uart.h:549
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uint32_t hwFlowControl
Definition: uart/v2/uart.h:479
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uint32_t readSizeRemaining
Definition: uart/v2/uart.h:560
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uint32_t readReturnMode
Definition: uart/v2/uart.h:471
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v2/uart.h:460
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
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uint32_t baudRate
Definition: uart/v2/uart.h:461
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Definition: uart/v2/uart.h:475
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uint32_t readErrorCnt
Definition: uart/v2/uart.h:564
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void * writeTransferSem
Definition: uart/v2/uart.h:587
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uint32_t status
Definition: uart/v2/uart.h:433
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Definition: uart/v2/uart.h:610
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Data structure used with UART_read() and UART_write()
Definition: uart/v2/uart.h:423
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uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
UART_LEN_8
#define UART_LEN_8
Definition: uart/v2/uart.h:184
UART_checkCharsAvailInFifo
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v2/uart.h:1341
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uint32_t intrNum
Definition: uart/v2/uart.h:489
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uint32_t inputClkFreq
Definition: uart/v2/uart.h:524
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UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_CONFIG_MODE_INTERRUPT
#define UART_CONFIG_MODE_INTERRUPT
Definition: uart/v2/uart.h:410
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UART_CallbackFxn writeCallbackFxn
Definition: uart/v2/uart.h:477
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART_Object
UART driver object.
Definition: uart/v2/uart.h:536
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uint32_t hwFlowControlThr
Definition: uart/v2/uart.h:481
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UART_Transaction * readTrans
Definition: uart/v2/uart.h:569
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uint32_t stopBits
Definition: uart/v2/uart.h:465
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v2/uart.h:1305
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void * readBuf
Definition: uart/v2/uart.h:556
UART_Params::rxEvtNum
uint32_t rxEvtNum
Definition: uart/v2/uart.h:510
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v2/uart.h:850
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v2/uart.h:282
UART_OPER_MODE_16X
#define UART_OPER_MODE_16X
Definition: uart/v2/uart.h:294
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v2/uart.h:518
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v2/uart.h:266
UART_readLineStatus
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v2/uart.h:1367
UART_Params::txEvtNum
uint32_t txEvtNum
Definition: uart/v2/uart.h:512
UART_getCharFifo
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v2/uart.h:1387
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v2/uart.h:522
UART_Transaction::buf
void * buf
Definition: uart/v2/uart.h:424
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v2/uart.h:1171
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v2/uart.h:594
UART_Object::prms
UART_Params prms
Definition: uart/v2/uart.h:542
UART_Transaction::count
uint32_t count
Definition: uart/v2/uart.h:427
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v2/uart.h:508
UART_Params::operMode
uint32_t operMode
Definition: uart/v2/uart.h:504