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AM263x MCU+ SDK
08.02.00
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Go to the documentation of this file.
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
72 #define UART_FIFO_SIZE (64U)
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
110 #define UART_TRANSFER_STATUS_STARTED (7U)
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
166 #define UART_READ_RETURN_MODE_FULL (0U)
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
313 #define UART_TX_FIFO_NOT_FULL ( \
314 UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316 UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
329 UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
332 UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
335 UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
338 UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
341 UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
344 UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
347 UART_IIR_IT_TYPE_SHIFT)
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
409 #define UART_CONFIG_MODE_POLLED (0x00U)
410 #define UART_CONFIG_MODE_INTERRUPT (0x01U)
411 #define UART_CONFIG_MODE_USER_INTR (0x02U)
412 #define UART_CONFIG_MODE_DMA (0x03U)
938 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
954 static inline uint32_t
UART_getChar(uint32_t baseAddr, uint8_t *pChar);
984 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
1133 static inline uint8_t
UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1140 HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1145 uint32_t lcrRegValue = 0U;
1146 uint32_t retVal = FALSE;
1149 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1152 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1156 if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1157 (HW_RD_REG32(baseAddr + UART_LSR) &
1158 UART_LSR_RX_FIFO_E_MASK))
1160 uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1161 *pChar = (uint8_t)tempRetVal;
1166 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1173 uint32_t enhanFnBitVal = 0U;
1174 uint32_t lcrRegValue = 0U;
1177 if ((intrFlag & 0xF0U) > 0U)
1180 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1185 enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1187 HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1188 UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1191 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1194 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1197 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1222 HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1225 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1228 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1233 HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1236 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1242 HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1243 (intrFlag & 0x0FU));
1248 uint32_t enhanFnBitVal;
1249 uint32_t lcrRegValue;
1252 if((intrFlag & 0xF0U) > 0U)
1255 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1260 enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1262 HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1263 UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1266 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1270 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1273 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1276 HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1277 ~(intrFlag & 0xFFU));
1280 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1283 if((intrFlag & 0xF0U) > 0U)
1286 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1291 HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1294 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1301 HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1302 (intrFlag & 0x03U));
1307 HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1308 ~(intrFlag & 0x3U));
1313 uint32_t lcrRegValue = 0U;
1314 uint32_t retVal = 0U;
1317 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1320 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1323 retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1326 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1333 uint32_t retVal = 0U;
1335 retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1336 (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1343 uint32_t lcrRegValue = 0;
1344 uint32_t retVal = FALSE;
1347 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1350 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1354 if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1355 (HW_RD_REG32(baseAddr + UART_LSR) &
1356 UART_LSR_RX_FIFO_E_MASK))
1358 retVal = (uint32_t) TRUE;
1362 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1369 uint32_t lcrRegValue = 0U;
1370 uint32_t retVal = 0U;
1373 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1376 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1379 retVal = HW_RD_REG32(baseAddr + UART_LSR);
1382 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1389 uint8_t readByte = 0;
1392 uint32_t lcrRegValue = 0;
1395 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1398 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1402 errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1403 (UART_LSR_RX_FIFO_STS_MASK |
1404 UART_LSR_RX_BI_MASK |
1405 UART_LSR_RX_FE_MASK |
1406 UART_LSR_RX_PE_MASK |
1407 UART_LSR_RX_OE_MASK);
1410 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1413 while ((UART_LSR_RX_FIFO_STS_MASK |
1414 UART_LSR_RX_BI_MASK |
1415 UART_LSR_RX_FE_MASK |
1416 UART_LSR_RX_PE_MASK |
1417 UART_LSR_RX_OE_MASK) == errorVal)
1419 readByte = HW_RD_REG32(baseAddr + UART_RHR);
1421 if (0U == waitCount)
1427 lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1430 HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1434 errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1435 (UART_LSR_RX_FIFO_STS_MASK |
1436 UART_LSR_RX_BI_MASK |
1437 UART_LSR_RX_FE_MASK |
1438 UART_LSR_RX_PE_MASK |
1439 UART_LSR_RX_OE_MASK);
1442 HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1446 readByte = HW_RD_REG32(baseAddr + UART_RHR);
void UART_enableLoopbackMode(uint32_t baseAddr)
Function to enable loopback mode. This function is for internal use. Not recommended for customers to...
void UART_deinit(void)
This function de-initializes the UART module.
void * readTransferSem
Definition: uart/v2/uart.h:582
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v2/uart.h:82
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v2/uart.h:138
SemaphoreP_Object lockObj
Definition: uart/v2/uart.h:580
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v2/uart.h:876
SemaphoreP_Object readTransferSemObj
Definition: uart/v2/uart.h:585
#define UART_REG_CONFIG_MODE_B
Definition: uart/v2/uart.h:396
#define UART_STOPBITS_1
Definition: uart/v2/uart.h:195
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v2/uart.h:96
UART_Handle handle
Definition: uart/v2/uart.h:540
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v2/uart.h:1298
void * hwiHandle
Definition: uart/v2/uart.h:592
const void * writeBuf
Definition: uart/v2/uart.h:547
uint32_t timeout
Definition: uart/v2/uart.h:431
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v2/uart.h:85
UART_Transaction * writeTrans
Definition: uart/v2/uart.h:571
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART global configuration array.
Definition: uart/v2/uart.h:607
uint32_t writeMode
Definition: uart/v2/uart.h:473
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v2/uart.h:1331
uint32_t writeSizeRemaining
Definition: uart/v2/uart.h:551
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v2/uart.h:446
uint32_t dataLength
Definition: uart/v2/uart.h:463
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
uint8_t intrPriority
Definition: uart/v2/uart.h:491
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
uint32_t readMode
Definition: uart/v2/uart.h:469
#define UART_RXTRIGLVL_8
Definition: uart/v2/uart.h:265
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v2/uart.h:1246
void UART_disableLoopbackMode(uint32_t baseAddr)
Function to disable loopback mode. This function is for internal use. Not recommended for customers t...
#define UART_PARITY_NONE
Definition: uart/v2/uart.h:207
uint32_t rxTrigLvl
Definition: uart/v2/uart.h:506
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v2/uart.h:1143
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
UART_Config gUartConfig[]
Externally defined driver configuration array.
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v2/uart.h:1311
void * args
Definition: uart/v2/uart.h:435
int32_t uartDmaIndex
Definition: uart/v2/uart.h:495
void * uartDmaHandle
Definition: uart/v2/uart.h:596
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v2/uart.h:166
uint32_t isOpen
Definition: uart/v2/uart.h:576
void UART_flushTxFifo(UART_Handle handle)
Function to flush a TX FIFO of peripheral specified by the UART handle.
uint32_t transferMode
Definition: uart/v2/uart.h:487
uint32_t skipIntrReg
Definition: uart/v2/uart.h:493
UART_Attrs * attrs
Definition: uart/v2/uart.h:608
SemaphoreP_Object writeTransferSemObj
Definition: uart/v2/uart.h:590
void * lock
Definition: uart/v2/uart.h:578
uint32_t readCount
Definition: uart/v2/uart.h:558
uint32_t parityType
Definition: uart/v2/uart.h:467
uint32_t rxTimeoutCnt
Definition: uart/v2/uart.h:562
static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v2/uart.h:1137
uint32_t writeCount
Definition: uart/v2/uart.h:549
uint32_t hwFlowControl
Definition: uart/v2/uart.h:479
uint32_t readSizeRemaining
Definition: uart/v2/uart.h:560
uint32_t readReturnMode
Definition: uart/v2/uart.h:471
void UART_init(void)
This function initializes the UART module.
UART Parameters.
Definition: uart/v2/uart.h:460
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
uint32_t baudRate
Definition: uart/v2/uart.h:461
UART_CallbackFxn readCallbackFxn
Definition: uart/v2/uart.h:475
uint32_t readErrorCnt
Definition: uart/v2/uart.h:564
void * writeTransferSem
Definition: uart/v2/uart.h:587
uint32_t status
Definition: uart/v2/uart.h:433
UART_Object * object
Definition: uart/v2/uart.h:610
Data structure used with UART_read() and UART_write()
Definition: uart/v2/uart.h:423
uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
#define UART_LEN_8
Definition: uart/v2/uart.h:184
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v2/uart.h:1341
uint32_t intrNum
Definition: uart/v2/uart.h:489
uint32_t inputClkFreq
Definition: uart/v2/uart.h:524
UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
#define UART_CONFIG_MODE_INTERRUPT
Definition: uart/v2/uart.h:410
UART_CallbackFxn writeCallbackFxn
Definition: uart/v2/uart.h:477
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART driver object.
Definition: uart/v2/uart.h:536
uint32_t hwFlowControlThr
Definition: uart/v2/uart.h:481
UART_Transaction * readTrans
Definition: uart/v2/uart.h:569
uint32_t stopBits
Definition: uart/v2/uart.h:465
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v2/uart.h:1305
void * readBuf
Definition: uart/v2/uart.h:556
uint32_t rxEvtNum
Definition: uart/v2/uart.h:510
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v2/uart.h:850
uint32_t gUartConfigNum
Externally defined driver configuration array size.
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
#define UART_TXTRIGLVL_32
Definition: uart/v2/uart.h:282
#define UART_OPER_MODE_16X
Definition: uart/v2/uart.h:294
UART instance attributes - used during init time.
Definition: uart/v2/uart.h:518
#define UART_RXTRIGLVL_16
Definition: uart/v2/uart.h:266
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v2/uart.h:1367
uint32_t txEvtNum
Definition: uart/v2/uart.h:512
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v2/uart.h:1387
uint32_t baseAddr
Definition: uart/v2/uart.h:522
void * buf
Definition: uart/v2/uart.h:424
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v2/uart.h:1171
HwiP_Object hwiObj
Definition: uart/v2/uart.h:594
UART_Params prms
Definition: uart/v2/uart.h:542
uint32_t count
Definition: uart/v2/uart.h:427
uint32_t txTrigLvl
Definition: uart/v2/uart.h:508
uint32_t operMode
Definition: uart/v2/uart.h:504