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AM263x MCU+ SDK
08.02.00
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Go to the documentation of this file.
96 #ifndef DISABLE_UART_PRINT
100 #include <industrial_comms/ethercat_slave/icss_fwhal/tiesc_pruss_intc_mapping.h>
102 #include <industrial_comms/ethercat_slave/icss_fwhal/tiesc_def.h>
117 #define TIESC_MAX_FRAME_SIZE (0x7CF)
124 #define ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM 0
126 #define MAX_SYNC_MAN 8
127 #define SIZEOF_SM_REGISTER 8
129 #define TIESC_EEPROM_SIZE 0x800
131 #define MAILBOX_WRITE 0
132 #define MAILBOX_READ 1
133 #define PROCESS_DATA_OUT 2
134 #define PROCESS_DATA_IN 3
136 #define MBX_WRITE_EVENT ((uint16_t) 0x0100)
137 #define MBX_READ_EVENT ((uint16_t) 0x0200)
140 #define ESC_ADDR_REV_TYPE 0x000
141 #define ESC_ADDR_BUILD 0x002
143 #define ESC_ADDR_CONFIG_STATION_ALIAS 0x012
144 #define ESC_ADDR_DLSTATUS 0x110
145 #define ESC_ADDR_ALCONTROL 0x120
146 #define ESC_ADDR_ALSTATUS 0x130
147 #define ESC_ADDR_PDI_CONTROL 0x140
148 #define ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK (1 << 1)
149 #define ESC_ADDR_PDI_CONFIG 0x150
150 #define ESC_ADDR_AL_EVENT_MASK 0x204
151 #define ESC_ADDR_AL_EVENT_REQ 0x220
152 #define ESC_ADDR_SM_WD_STATUS 0x440
153 #define ESC_ADDR_EEPROM_CTRL 0x502
154 #define ESC_ADDR_MI_ECAT_ACCESS 0x516
155 #define ESC_ADDR_MI_PDI_ACCESS 0x517
157 #define ESC_EEPROM_CMD_MASK 0x0700 //Description (0x502.8:10): Command bit mask
158 #define ESC_EEPROM_CMD_READ_MASK 0x0100 //Description (0x502.8): Currently executed read command
159 #define ESC_EEPROM_CMD_WRITE_MASK 0x0200 //Description (0x502.9): Initialize Write Command
160 #define ESC_EEPROM_CMD_RELOAD_MASK 0x0400 //Description (0x502.10): Trigger EEPROM reload
161 #define ESC_EEPROM_ERROR_MASK 0x7800 //Description : Mask all EEPROM error bits; Checksum error (0x0502.11); EEPROM not loaded (0x0502.12); Missing EEPROM Acknowledge (0x0502.13); Write Error (0x0502.14)
162 #define ESC_EEPROM_ERROR_CRC 0x0800 //Description (0x502.11): EEPROM CRC Error
163 #define ESC_EEPROM_ERROR_CMD_ACK 0x2000 //Description (0x502.13): EEPROM Busy
164 #define ESC_EEPROM_BUSY_MASK 0x8000 //Description (0x502.15): EEPROM Busy
166 #define ESC_ADDR_SYNCMAN 0x800
168 #define ESC_ADDR_SM1_STATUS 0x80D
169 #define SM_STATUS_MBX_FULL 0x08
171 #define ESC_ADDR_SM0_STATUS 0x805
172 #define ESC_ADDR_SM0_ACTIVATE 0x806
173 #define ESC_ADDR_SM1_ACTIVATE 0x806+8
174 #define ESC_ADDR_SM2_ACTIVATE 0x806+8*2
175 #define ESC_ADDR_SM3_ACTIVATE 0x806+8*3
176 #define ESC_ADDR_SM4_ACTIVATE 0x806+8*4
177 #define ESC_ADDR_SM5_ACTIVATE 0x806+8*5
178 #define ESC_ADDR_SM6_ACTIVATE 0x806+8*6
179 #define ESC_ADDR_SM7_ACTIVATE 0x806+8*7
180 #define ESC_ADDR_SM0_PDI_CONTROL 0x807
181 #define ESC_ADDR_SM1_PDI_CONTROL 0x807+8
182 #define ESC_ADDR_SM2_PDI_CONTROL 0x807+8*2
183 #define ESC_ADDR_SM3_PDI_CONTROL 0x807+8*3
184 #define ESC_ADDR_SM4_PDI_CONTROL 0x807+8*4
185 #define ESC_ADDR_SM5_PDI_CONTROL 0x807+8*5
186 #define ESC_ADDR_SM6_PDI_CONTROL 0x807+8*6
187 #define ESC_ADDR_SM7_PDI_CONTROL 0x807+8*7
189 #define SM_PDI_CONTROL_SM_DISABLE 1
191 #define ESC_ADDR_SYSTIME 0x910
192 #define ESC_ADDR_SYSTIME_HIGH 0x914
193 #define ESC_ADDR_SYSTIME_OFFSET 0x920
194 #define ESC_ADDR_SYSTIME_DELAY 0x928
195 #define ESC_ADDR_SPEEDCOUNTER_START 0x930
196 #define ESC_ADDR_TIMEDIFF_FILTDEPTH 0x934
197 #define ESC_ADDR_SPEEDDIFF_FILTDEPTH 0x935
198 #define ESC_ADDR_SYNC_PULSE_LENGTH 0x982
199 #define ESC_ADDR_SYNC_STATUS 0x98E
200 #define ESC_ADDR_LATCH0_CONTROL 0x9A8
201 #define ESC_ADDR_LATCH1_CONTROL 0x9A9
202 #define ESC_ADDR_LATCH0_POS_EDGE 0x9B0
203 #define ESC_ADDR_LATCH0_NEG_EDGE 0x9B8
204 #define ESC_ADDR_LATCH1_POS_EDGE 0x9C0
205 #define ESC_ADDR_LATCH1_NEG_EDGE 0x9C8
206 #define ESC_ADDR_TI_PORT0_ACTIVITY 0xE00
207 #define ESC_ADDR_TI_PORT1_ACTIVITY 0xE04
208 #define ESC_ADDR_TI_PORT0_PHYADDR 0xE08
209 #define ESC_ADDR_TI_PORT1_PHYADDR 0xE09
210 #define ESC_ADDR_TI_PDI_ISR_PINSEL 0xE0A
211 #define ESC_ADDR_TI_PHY_LINK_POLARITY 0XE0C
212 #define ESC_ADDR_TI_PORT0_TX_START_DELAY 0xE10
213 #define ESC_ADDR_TI_PORT1_TX_START_DELAY 0xE12
214 #define ESC_ADDR_TI_ESC_RESET 0xE14
215 #define ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT 0xE24
216 #define TI_ESC_RST_CMD_U 0x545352
217 #define TI_ESC_RST_CMD_L 0x747372
219 #define ESC_ADDR_MEMORY 0x1000
221 #define CMD_DL_USER_CLEAR_AL_EVENT_HIGH 0x0
222 #define CMD_DL_USER_GET_BUFFER_READ_ADDR 0x1
223 #define CMD_DL_USER_GET_BUFFER_WRITE_ADDR 0x2
224 #define CMD_DL_USER_SET_BUFFER_WRITE_DONE 0x3
229 #define CMD_DL_USER_ACK_MBX_READ 0x4
234 #define CMD_DL_USER_ACK_MBX_WRITE 0x5
239 #define CMD_DL_USER_EEPROM_CMD_ACK 0x6
244 #define CMD_DL_USER_READ_SYNC_STATUS 0x7
251 #define CMD_DL_USER_READ_AL_CONTROL 0x8
256 #define CMD_DL_USER_WRITE_AL_STATUS 0x9
261 #define CMD_DL_USER_READ_PD_WD_STATUS 0xA
266 #define CMD_DL_USER_READ_SM_ACTIVATE 0xB
271 #define CMD_DL_USER_WRITE_SM_PDI_CTRL 0xC
276 #define CMD_DL_USER_READ_LATCH_TIME 0xD
277 #define LATCH0_POS_EDGE 0
278 #define LATCH0_NEG_EDGE 1
279 #define LATCH1_POS_EDGE 2
280 #define LATCH1_NEG_EDGE 3
286 #define CMD_DL_USER_READ_SYS_TIME 0xE
291 #define CMD_DL_USER_CLEAR_AL_EVENT_LOW 0xF
292 #ifdef SYSTEM_TIME_PDI_CONTROLLED
297 #define CMD_DL_USER_SYSTIME_PDI_CONTROL 0x10
298 #define WRITE_SYSTIME 0
299 #define WRITE_SYSTIME_OFFSET 1
300 #define WRITE_FILTER_CONFIG 2
306 #define ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE 0x40
307 #define ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK 0x80
309 #define TIESC_PERM_RW 0x0
310 #define TIESC_PERM_WRITE_ONLY 0x1
311 #define TIESC_PERM_READ_ONLY 0x2
313 #define TIESC_PERM_WRITE TIESC_PERM_WRITE_ONLY
314 #define TIESC_PERM_READ TIESC_PERM_READ_ONLY
316 #define PDI_PERM_RW 0x0
317 #define PDI_PERM_READ_ONLY 0x1
319 #define PDI_PERM_WRITE PDI_PERM_RW
320 #define PDI_PERM_READ PDI_PERM_READ_ONLY
322 #define TIESC_MDIO_CLKDIV 79 //For 2.5MHz MDIO clock: 200/(TIESC_MDIO_CLKDIV+1)
324 #define TIESC_MDIO_RX_LINK_DISABLE 0 //Slow MDIO state m/c based link detection
325 #define TIESC_MDIO_RX_LINK_ENABLE 1 //Fast link detect using RXLINK forward from PHY to MDIO MLINK
326 #define TIESC_LINK_POL_ACTIVE_LOW 1
327 #define TIESC_LINK_POL_ACTIVE_HIGH 0
333 #define PDI_WD_TRIGGER_RX_SOF (0 << 4)
339 #define PDI_WD_TRIGGER_LATCH_IN (1 << 4)
345 #define PDI_WD_TRIGGER_SYNC0_OUT (2 << 4)
351 #define PDI_WD_TRIGGER_SYNC1_OUT (3 << 4)
353 #if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
354 #define TIESC_PORT0_TX_DELAY 0xA0
356 #define TIESC_PORT0_TX_DELAY 0x50
358 #define TIESC_PORT1_TX_DELAY 0x50
360 #define PDI_ISR_EDIO_NUM 7 //GPMC_CSN(2) -> pr1_edio_data_out7 for ICEv2.J4.Pin21
366 #define USE_ECAT_TIMER
373 #define ENABLE_PDI_TASK
374 #define ENABLE_SYNC_TASK
384 #if defined (__aarch64__)
385 #define ASSERT_DMB() __asm__(" dmb ISH")
386 #define ASSERT_DSB() __asm__(" dsb ISH")
388 #define ASSERT_DMB() __asm__(" dmb")
389 #define ASSERT_DSB() __asm__(" dsb")
392 #ifdef USE_ECAT_TIMER
393 #define ECAT_TIMER_INC_P_MS 1000000
395 #define ECAT_TIMER_INC_P_MS ecat_timer_inc_p_ms
396 extern volatile uint32_t ecat_timer_inc_p_ms;
399 #define ESC_SYSTEMTIME_OFFSET_OFFSET 0x0920
400 #define ESC_SPEED_COUNTER_START_OFFSET 0x0930
401 #define ESC_DC_START_TIME_CYCLIC_OFFSET 0x0990
403 #define DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST 0xE0 //PRU_DMEM0
409 #define LOCK_PD_BUF_AVAILABLE_FOR_HOST 0
414 #define LOCK_PD_BUF_HOST_ACCESS_START 1
419 #define LOCK_PD_BUF_HOST_ACCESS_FINISH 2
427 #define LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT (10U)
445 typedef struct bsp_params_s
506 uint8_t reserved1[0x90];
510 uint8_t reserved2[7];
517 #ifndef SYSTEM_TIME_PDI_CONTROLLED
518 uint8_t reserved3[212];
520 uint8_t reserved3[24];
521 uint32_t systime_offset_low;
522 uint32_t systime_offset_high;
523 uint8_t reserved4[180];
533 uint8_t reserved[1024];
534 uint8_t reg_properties[4096];
696 uint32_t command, uint16_t param1, uint16_t param2);
723 int32_t reload_flag);
816 uint16_t address, uint16_t len);
903 uint16_t address, uint16_t len, int16_t *p_sm_index);
917 uint16_t address, uint16_t len, int16_t sm_index);
1026 uint16_t address, uint16_t length);
1042 uint16_t address, uint16_t length,
1087 uint16_t address, uint16_t len);
1098 uint32_t regoffset);
1109 uint32_t regoffset);
1120 uint32_t regoffset);
1131 uint32_t regoffset);
1274 uint8_t phyaddr, uint8_t regoffset, uint16_t *regval);
1287 uint8_t phyaddr, uint8_t regoffset, uint16_t regval);
1363 #ifdef SYSTEM_TIME_PDI_CONTROLLED
1371 extern void bsp_pdi_latch0_control(
PRUICSS_Handle pruIcssHandle, uint8_t val);
1380 extern void bsp_pdi_latch1_control(
PRUICSS_Handle pruIcssHandle, uint8_t val);
1388 extern void bsp_pdi_write_system_time(
PRUICSS_Handle pruIcssHandle,
1396 extern void bsp_pdi_write_system_timeoffset(
PRUICSS_Handle pruIcssHandle,
1397 unsigned long long systime);
1404 extern void bsp_pdi_write_systime_delay(
PRUICSS_Handle pruIcssHandle,
1414 extern void bsp_pdi_write_filterconfig(
PRUICSS_Handle pruIcssHandle,
1415 uint16_t speedcount_start,
1416 uint8_t speedcount_filtdepth, uint8_t systime_filtdepth);
1444 uint32_t *systime_high);
1454 uint32_t *systime_low, uint32_t *systime_high);
1464 uint32_t *systime_low, uint32_t *systime_high);
1474 uint32_t *systime_low, uint32_t *systime_high);
1484 uint32_t *systime_low, uint32_t *systime_high);
1523 #ifndef SUPPORT_CMDACK_POLL_MODE
1547 uint32_t *hostProc, uint32_t hostProcLen);
void bsp_set_eeprom_update_status(uint8_t status)
Indicate to FWHAL whether EEPROM is written for flushing to non-volatile storage. Typically called on...
uint32_t phy1_address
Definition: tiescbsp.h:475
uint8_t sm_buf_index
Definition: tiescbsp.h:495
uint32_t bsp_get_pdi_read_access_fail_cnt()
Returns the count of PDI read access failures.
uint32_t bsp_hwspinlock_lock(int num)
Acquire selected spinlock instance.
uint16_t resp2low
Definition: tiescbsp.h:516
void bsp_pdi_post_read_indication(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t length)
Invoked after reading a register or mailbox buffer from PDI side .
void EscCmdLowAckIsr(void *args)
ESC CMD Low ACK IRQ Handler.
void bsp_eeprom_emulation_exit(void)
Call EEPROM flush on exit.
void bsp_get_latch0_posedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 posedge timestamp for application use(nanosec resolution)
void bsp_pdi_mbx_write_start(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side write to read mailbox has started.
uint32_t(* bsp_hwspinlock_lock_t)(int num)
Definition: tiescbsp.h:432
void bsp_global_mutex_lock(void)
Critical section enter API using semaphore/mutex/interrupt disable primitives from RTOS....
uint8_t bsp_pdi_access_perm_dword(uint16_t address, uint8_t access)
Checks if the PDI register [Four bytes] has the requested access permission and returns the result.
uint8_t ** eeprom_pointer_for_stack
Definition: tiescbsp.h:479
int32_t(* bsp_eeprom_read_t)(uint8_t *buf, uint32_t len)
Definition: tiescbsp.h:429
uint32_t system_time_low
Definition: tiescbsp.h:507
uint16_t cmdlow_ack
Definition: tiescbsp.h:512
int32_t(* bsp_eeprom_write_t)(uint8_t *buf, uint32_t len)
Definition: tiescbsp.h:430
Struct for host to PRU-ICSS command interface.
Definition: tiescbsp.h:494
uint8_t addr0
Definition: tiescbsp.h:549
void bsp_process_data_access_complete(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t len, int16_t sm_index)
This API is invoked after PDI side completes read/write to PD address returned by bsp_get_process_dat...
bsp_ethphy_init_t ethphy_init
Definition: tiescbsp.h:464
uint16_t bsp_read_word(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 16-bit value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
uint8_t lock_state
Definition: tiescbsp.h:496
void bsp_get_latch1_posedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch1 posedge timestamp for application use(nanosec resolution)
int8_t(* bsp_get_phy_address_t)(uint8_t instance, uint8_t portNumber)
Definition: tiescbsp.h:435
void bsp_hwspinlock_unlock(int num)
Release selected spinlock instance.
uint8_t bsp_is_pdi_perm_read_only(uint16_t *perm_array, uint16_t address)
Checks if the PDI register [byte] has read only access permission and returns the result.
void bsp_send_command_to_firmware(PRUICSS_Handle pruIcssHandle, uint32_t command, uint16_t param1, uint16_t param2)
Send command and parameters from stack to firmware to perform some action based on stack state or in ...
uint8_t bsp_read_byte(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a byte value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
void bsp_pdi_write_indication(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t length, uint16_t value)
Invoked after writing a register or mailbox buffer from PDI side .
uint16_t length
Definition: tiescbsp.h:540
void bsp_params_init(bsp_params *init_params)
Initialize the members of bsp_params with default values.
Definition: tiescbsp.h:538
void bsp_pruss_iepreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val, uint32_t regoffset)
Write a 32-bit value from PRU-ICSS IEP register at 'regoffset'.
uint32_t bsp_pruss_mdioreg_read(PRUICSS_Handle pruIcssHandle, uint32_t regoffset)
Read a 32-bit value from PRU-ICSS MDIO register at 'regoffset'.
uint32_t bsp_read_dword_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 32-bit value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
int32_t bsp_eeprom_emulation_reload(PRUICSS_Handle pruIcssHandle)
Perform reload operation after validating EEPROM CRC.
void bsp_set_pdi_wd_trigger_mode(PRUICSS_Handle pruIcssHandle, uint32_t mode)
Configure PDI WD trigger mode, PDI WD is triggered automatically by h/w on RX_SOF(port0/port1),...
void bsp_eeprom_emulation_flush(void)
Flush the EEPROM cache to non-volatile storage. Write is performed using eeprom_write callback from b...
void bsp_read(PRUICSS_Handle pruIcssHandle, uint8_t *pdata, uint16_t address, uint16_t len)
Read a byte array at 'address' from ESC memory.
uint16_t bsp_get_process_data_address(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t len, int16_t *p_sm_index)
Get the actual address of the buffer for PDI side read/write from host in 3-buffer mode.
uint16_t bsp_read_word_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 16-bit value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
void bsp_set_sm_properties(PRUICSS_Handle pruIcssHandle, uint8_t sm, uint16_t address, uint16_t len)
Set the address, length info from register to FWHAL layer. During INIT to PREOP transition in Mailbox...
uint32_t system_time_high
Definition: tiescbsp.h:508
bsp_ethercat_stack_isr_function pdi_isr
Definition: tiescbsp.h:482
void(* bsp_ethercat_stack_isr_function)(void)
Definition: tiescbsp.h:436
int16_t bsp_pruss_mdio_phy_write(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr, uint8_t regoffset, uint16_t regval)
API to write PHY register via PRU-ICSS MDIO.
uint32_t spinlock_base_address
Definition: tiescbsp.h:461
Struct for register permission array.
Definition: tiescbsp.h:532
void bsp_get_latch1_negedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 negedge timestamp for application use(nanosec resolution)
void bsp_set_pru_firmware(uint32_t *frameProc, uint32_t frameProcLen, uint32_t *hostProc, uint32_t hostProcLen)
This function internally sets the location from which PRU firmwares can be loaded.
uint8_t bsp_pdi_access_perm_word(uint16_t address, uint8_t access)
Checks if the PDI register [Two bytes] has the requested access permission and returns the result.
void bsp_set_pdi_perm_read_only(uint16_t *perm_array, uint16_t address)
Set the PDI register [byte] access permission to read only.
uint8_t enhancedlink_enable
Definition: tiescbsp.h:553
void bsp_set_eeprom_updated_time(void)
Set EEPROM update time.
void bsp_write_byte(PRUICSS_Handle pruIcssHandle, uint8_t val, uint16_t address)
Write a byte value at 'address' in ESC memory.
int32_t bsp_eeprom_load_esc_registers(PRUICSS_Handle pruIcssHandle, int32_t reload_flag)
For loading ESC registers from EEPROM during first boot/reload after validating CRC.
void bsp_esc_reg_perm_init(PRUICSS_Handle pruIcssHandle)
Sets up register permissions for ECAT side access for TI ESC, if ENABLE_PDI_REG_PERMISSIONS is define...
void bsp_write(PRUICSS_Handle pruIcssHandle, uint8_t *pdata, uint16_t address, uint16_t len)
Write 'len' bytes from pdata to 'address' in ESC memory.
uint8_t addr1
Definition: tiescbsp.h:550
uint16_t resp1low
Definition: tiescbsp.h:515
void bsp_write_word(PRUICSS_Handle pruIcssHandle, uint16_t val, uint16_t address)
Write a 16-bit value at 'address' in ESC memory.
void bsp_eeprom_emulation_command_ack(PRUICSS_Handle pruIcssHandle)
Perform reload operation after validating EEPROM CRC, Wrapper API for SSC.
int16_t bsp_pruss_mdio_phy_read(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr, uint8_t regoffset, uint16_t *regval)
API to read PHY register via PRU-ICSS MDIO.
uint8_t link1pol
Definition: tiescbsp.h:552
Struct for MDIO initialization parameters.
Definition: tiescbsp.h:547
void(* bsp_hwspinlock_unlock_t)(int num)
Definition: tiescbsp.h:433
void bsp_set_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num)
Set selected digital output pin.
uint8_t bsp_get_pdi_access_perm(uint16_t address, uint8_t access)
Checks if the PDI register [byte] has the requested access permission and returns the result.
void bsp_global_mutex_unlock(void)
Critical section leave API using semaphore/mutex/interrupt enable primitives from RTOS....
uint16_t param2low
Definition: tiescbsp.h:514
int32_t interrupt_offset
Definition: tiescbsp.h:449
void bsp_exit(PRUICSS_Handle pruIcssHandle)
Cleanup of EtherCAT FWHAL It does following things: .
Struct for host to PRU-ICSS command interface Starts at PRU0 DMEM.
Definition: tiescbsp.h:505
uint32_t link0_polarity
Definition: tiescbsp.h:469
int32_t bsp_init(bsp_params *init_params)
Initialize the EtherCAT FWHAL It does following things: .
uint32_t bsp_read_dword(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 32-bit value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
void bsp_start_esc_isr(PRUICSS_Handle pruIcssHandle)
Register IRQ handlers for various PRU-ICSS interrupts from firmware to host to clear corresponding ev...
uint32_t bsp_get_timer_register(void)
Returns the time difference from last call of bsp_clear_timer_register to this bsp_get_timer_register...
uint32_t bsp_get_eeprom_updated_time(void)
Get EEPROM Updated time.
PRUICSS_Handle pruicss_handle
Definition: tiescbsp.h:447
void bsp_pruss_cmd_intfc_write_word(uint16_t val, volatile uint16_t *ptr)
Read a 16-bit value from PRU-ICSS IEP command interface.
uint16_t param1low
Definition: tiescbsp.h:513
uint8_t link0pol
Definition: tiescbsp.h:551
void bsp_get_local_sys_time(uint32_t *systime_low, uint32_t *systime_high)
Return EtherCAT time base for application use.
void bsp_write_dword(PRUICSS_Handle pruIcssHandle, uint32_t val, uint16_t address)
Write a 32-bit value at 'address' in ESC memory.
uint16_t bsp_pruss_cmd_intfc_read_word(volatile uint16_t *ptr)
Read a 16-bit value from PRU-ICSS IEP command interface.
uint32_t bsp_pruss_iepreg_read(PRUICSS_Handle pruIcssHandle, uint32_t regoffset)
Read a 32-bit value from PRU-ICSS IEP register at 'regoffset'.
void bsp_eeprom_emulation_init(void)
Initialize the EEPROM cache in volatile RAM. If the non-volatile storage has valid data(read is perfo...
uint8_t bsp_pdi_access_perm_array(uint16_t address, uint8_t access, uint16_t size)
Checks if all PDI registers starting from 'address' has the requested access permission and returns t...
uint16_t addr
Definition: tiescbsp.h:497
void bsp_set_pdi_perm_read_write(uint16_t *perm_array, uint16_t address)
Set the PDI register [byte] access permission to read and write.
uint32_t phy0_address
Definition: tiescbsp.h:473
bsp_eeprom_write_t eeprom_write
Definition: tiescbsp.h:459
void bsp_clear_timer_register(void)
Update the time when bsp_clear_timer_register last invoked. This is a wrapper API used by SSC.
void Sync1Isr(void *args)
SYNC1 IRQ Handler.
void bsp_pdi_mbx_read_start(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side read from write mailbox has started.
uint16_t clkdiv
Definition: tiescbsp.h:548
uint32_t bsp_get_pdi_write_access_fail_cnt()
Returns the count of PDI write access failures.
void bsp_pdi_mbx_read_complete(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side read from write mailbox has completed.
void Sync0Isr(void *args)
SYNC0 IRQ handler.
int16_t bsp_pruss_mdio_init(PRUICSS_Handle pruIcssHandle, t_mdio_params *pmdio_params)
Initializes PRU-ICSS MDIO for EtherCAT firmware to communicate with PHYs. Must be called after poweri...
void bsp_pdi_mbx_write_complete(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side write to read mailbox has completed.
void bsp_clear_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num)
Clear selected digital output pin.
t_sm_properties * bsp_get_sm_properties(uint8_t sm)
Get the pointer to requested SM properties. It is used for Buffer/Mailbox read/write detection from H...
bsp_ethercat_stack_isr_function sync1_isr
Definition: tiescbsp.h:486
uint8_t bsp_get_eeprom_update_status(void)
Read the EEPROM update status from FWHAL. Typically called from low priority task periodically check ...
uint16_t cmdlow
Definition: tiescbsp.h:511
uint8_t enhancedlink_enable
Definition: tiescbsp.h:466
int16_t bsp_get_sm_index(uint16_t address, uint16_t len)
void(* bsp_init_spinlock_t)(void)
Definition: tiescbsp.h:431
uint8_t bsp_read_byte_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a byte value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
void bsp_set_digio_sw_dataout_enable(PRUICSS_Handle pruIcssHandle)
Configure digio for sw controlled dataout mode.
void EcatIsr(void *args)
ECAT IRQ Handler.
void(* bsp_ethphy_init_t)(PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable)
Definition: tiescbsp.h:434
Struct for FWHAL initialization Parameters.
Definition: tiescbsp.h:446
uint8_t * bsp_get_eeprom_cache_base(void)
Return pointer to volatile EEPROM cache in FWHAL for processing to access the EEPROM.
void bsp_pruss_mdioreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val, uint32_t regoffset)
Write a 32-bit value from PRU-ICSS MDIO register at 'regoffset'.
uint32_t link1_polarity
Definition: tiescbsp.h:471
uint8_t bsp_pdi_sm_config_ongoing(PRUICSS_Handle pruIcssHandle)
Checks whether firmware has finished updating internal state for SM configuration change initiated by...
bsp_ethercat_stack_isr_function sync0_isr
Definition: tiescbsp.h:484
bsp_eeprom_read_t eeprom_read
Definition: tiescbsp.h:457
uint8_t sm_config_ongoing
Definition: tiescbsp.h:509
uint32_t bsp_pruss_mdio_phy_link_state(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr)
Get the link status for selected PHY, this API considers MII_link signal polarity differences and rec...
struct PRUICSS_Config_s * PRUICSS_Handle
A handle that is returned from a PRUICSS_open() call. This handle is required for calling other APIs.
Definition: pruicss/m_v0/pruicss.h:226
uint16_t physical_start_addr
Definition: tiescbsp.h:539
const unsigned char * default_tiesc_eeprom
Definition: tiescbsp.h:477
void bsp_get_latch0_negedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 negedge timestamp for application use(nanosec resolution)
void bsp_hwspinlock_init(void)
Initialize SOC spinlock, enable clocks and init spinlock instance 0 through 7 to unlocked state.